iCE40/yosys - [no description]

	Commit message (Collapse)	Author	Age	Files	Lines
*	Fixed build with gcc-4.6	Clifford Wolf	2014-08-07	1	-6/+6
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*	Various fixes and improvements in wreduce pass	Clifford Wolf	2014-08-05	1	-29/+47
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*	Removed old "constmap" from wreduce code	Clifford Wolf	2014-08-05	1	-3/+2
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*	Added support for truncating of wires to wreduce pass	Clifford Wolf	2014-08-05	1	-4/+40
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*	Cleanups and improvements in wreduce pass	Clifford Wolf	2014-08-05	1	-47/+77
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*	Added mux support to wreduce command	Clifford Wolf	2014-08-05	1	-36/+82
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*	Added "show -signed"	Clifford Wolf	2014-08-04	1	-5/+17
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*	Added RTLIL::IdString::in(...)	Clifford Wolf	2014-08-04	1	-4/+3
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*	Progress in "wreduce" pass	Clifford Wolf	2014-08-03	1	-43/+16
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*	Added "wreduce" command (work in progress)	Clifford Wolf	2014-08-03	2	-0/+253
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*	Fixes in show command (related to new IdString)	Clifford Wolf	2014-08-03	1	-20/+18
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*	No implicit conversion from IdString to anything else	Clifford Wolf	2014-08-02	3	-4/+4
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*	More bugfixes related to new RTLIL::IdString	Clifford Wolf	2014-08-02	1	-3/+3
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*	More cleanups related to RTLIL::IdString usage	Clifford Wolf	2014-08-02	4	-19/+21
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*	Preparations for RTLIL::IdString redesign: cleanup of existing code	Clifford Wolf	2014-08-02	3	-6/+6
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*	Added ModIndex helper class, some changes to RTLIL::Monitor	Clifford Wolf	2014-08-01	1	-3/+3
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*	Renamed port access function on RTLIL::Cell, added param access functions	Clifford Wolf	2014-07-31	3	-10/+10
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*	Added "trace" command	Clifford Wolf	2014-07-31	3	-2/+100
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*	Added module->design and cell->module, wire->module pointers	Clifford Wolf	2014-07-31	2	-4/+6
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*	Moved some stuff to kernel/yosys.{h,cc}, using Yosys:: namespace	Clifford Wolf	2014-07-31	1	-0/+4
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*	Added write_file command	Clifford Wolf	2014-07-30	2	-0/+77
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*	Using log_assert() instead of assert()	Clifford Wolf	2014-07-28	3	-5/+5
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*	Refactoring: Renamed RTLIL::Design::modules to modules_	Clifford Wolf	2014-07-27	16	-62/+62
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*	Refactoring: Renamed RTLIL::Module::cells to cells_	Clifford Wolf	2014-07-27	14	-38/+38
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*	Refactoring: Renamed RTLIL::Module::wires to wires_	Clifford Wolf	2014-07-27	11	-35/+35
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*	Changed more code to the new RTLIL::Wire constructors	Clifford Wolf	2014-07-26	2	-15/+9
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*	Changed a lot of code to the new RTLIL::Wire constructors	Clifford Wolf	2014-07-26	4	-58/+25
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*	Added RTLIL::Cell::has(portname)	Clifford Wolf	2014-07-26	1	-1/+1
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*	Manual fixes for new cell connections API	Clifford Wolf	2014-07-26	6	-10/+10
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*	Changed users of cell->connections_ to the new API (sed command)	Clifford Wolf	2014-07-26	10	-33/+33
\| \| \| \| \| \| \| \| \|	git grep -l 'connections_' \| xargs sed -i -r -e ' s/(->\|\.)connections_\["([^"])"\] = (.);/\1set("\2", \3);/g; s/(->\|\.)connections_\["([^"])"\]/\1get("\2")/g; s/(->\|\.)connections_.at\("([^"])"\)/\1get("\2")/g; s/(->\|\.)connections_.push_back/\1connect/g; s/(->\|\.)connections_/\1connections()/g;'
*	Renamed RTLIL::{Module,Cell}::connections to connections_	Clifford Wolf	2014-07-26	10	-33/+33
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*	Use only module->addCell() and module->remove() to create and delete cells	Clifford Wolf	2014-07-25	2	-13/+6
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*	Various RTLIL::SigSpec related code cleanups	Clifford Wolf	2014-07-25	1	-3/+3
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*	Disabled cover() for non-linux builds	Clifford Wolf	2014-07-25	1	-2/+5
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*	Improvements in "cover" command	Clifford Wolf	2014-07-25	1	-11/+37
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*	Replaced more old SigChunk programming patterns	Clifford Wolf	2014-07-24	1	-2/+2
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*	Added "cover" command	Clifford Wolf	2014-07-24	3	-1/+117
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*	Removed RTLIL::SigSpec::optimize()	Clifford Wolf	2014-07-23	4	-7/+1
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*	Fixed all users of SigSpec::chunks_rw() and removed it	Clifford Wolf	2014-07-23	3	-36/+34
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*	SigSpec refactoring: change RTLIL::SigSpec::chunks() to be read-only, ↵	Clifford Wolf	2014-07-22	4	-5/+5
\| \| \| \|	created interim RTLIL::SigSpec::chunks_rw()
*	SigSpec refactoring: using the accessor functions everywhere	Clifford Wolf	2014-07-22	10	-39/+39
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*	SigSpec refactoring: renamed chunks and width to __chunks and __width	Clifford Wolf	2014-07-22	10	-39/+39
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*	Removed deprecated module->new_wire()	Clifford Wolf	2014-07-21	3	-4/+4
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*	Added "select -assert-count"	Clifford Wolf	2014-07-20	1	-6/+43
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*	Improved seeding of color rng in show command	Clifford Wolf	2014-07-18	1	-1/+3
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*	Added %D and %c select commands	Clifford Wolf	2014-06-14	1	-2/+20
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*	added tee cmd	Clifford Wolf	2014-06-03	2	-0/+89
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*	fixed syntax error in dot file created by "show" command	Clifford Wolf	2014-05-10	1	-1/+1
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*	- kernel/register.h, kernel/driver.cc: refactor ↵	Siesh1oo	2014-03-12	1	-1/+2
\| \| \| \| \| \| \|	rewrite_yosys_exe()/get_share_file_name() to portable proc_self_dirname()/proc_share_dirname(). This refactoring improves robustness and allows OSX support with only 7 new lines of code, and easy extension for other systems. - passes/abc/abc.cc, passes/cmds/show.cc, passes/techmap/techmap.cc: use new, refactored semantics.
*	Merged a few fixes for non-posix systems from github.com/Siesh1oo/yosys	Clifford Wolf	2014-03-11	1	-0/+1
\| \| \| \|	(see https://github.com/cliffordwolf/yosys/pull/28)