Added module->design and cell->module, wire->module pointers

2 files changed, 6 insertions, 4 deletions

diff --git a/passes/cmds/copy.cc b/passes/cmds/copy.cc
index fc801f61f..be7758200 100644
--- a/passes/cmds/copy.cc
+++ b/passes/cmds/copy.cc
@@ -47,8 +47,9 @@ struct CopyPass : public Pass {
 		if (design->modules_.count(trg_name) != 0)
 			log_cmd_error("Target module name %s already exists.\n", trg_name.c_str());
 
-		design->modules_[trg_name] = design->modules_.at(src_name)->clone();
-		design->modules_[trg_name]->name = trg_name;
+		RTLIL::Module *new_mod = design->module(src_name)->clone();
+		new_mod->name = trg_name;
+		design->add(new_mod);
 	}
 } CopyPass;
  
diff --git a/passes/cmds/design.cc b/passes/cmds/design.cc
index 79695c635..41548f621 100644
--- a/passes/cmds/design.cc
+++ b/passes/cmds/design.cc
@@ -198,6 +198,7 @@ struct DesignPass : public Pass {
 					delete copy_to_design->modules_.at(trg_name);
 				copy_to_design->modules_[trg_name] = mod->clone();
 				copy_to_design->modules_[trg_name]->name = trg_name;
+				copy_to_design->modules_[trg_name]->design = copy_to_design;
 			}
 		}
 
@@ -206,7 +207,7 @@ struct DesignPass : public Pass {
 			RTLIL::Design *design_copy = new RTLIL::Design;
 
 			for (auto &it : design->modules_)
-				design_copy->modules_[it.first] = it.second->clone();
+				design_copy->add(it.second->clone());
 
 			design_copy->selection_stack = design->selection_stack;
 			design_copy->selection_vars = design->selection_vars;
@@ -242,7 +243,7 @@ struct DesignPass : public Pass {
 				pushed_designs.pop_back();
 
 			for (auto &it : saved_design->modules_)
-				design->modules_[it.first] = it.second->clone();
+				design->add(it.second->clone());
 
 			design->selection_stack = saved_design->selection_stack;
 			design->selection_vars = saved_design->selection_vars;