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| author | Clifford Wolf <clifford@clifford.at> | 2014-07-22 20:58:44 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2014-07-22 20:58:44 +0200 |
| commit | 28b3fd05fa9cf6d469fdec95e247a7ffe5bc001d (patch) | |
| tree | 9a847fc2fc608ce9ffbc947bcb18eea2205bb2d5 /passes/cmds | |
| parent | 7bffde6abdaf6fc2ed090946442f90b2438e6126 (diff) | |
| download | yosys-28b3fd05fa9cf6d469fdec95e247a7ffe5bc001d.tar.gz yosys-28b3fd05fa9cf6d469fdec95e247a7ffe5bc001d.tar.bz2 yosys-28b3fd05fa9cf6d469fdec95e247a7ffe5bc001d.zip | |
SigSpec refactoring: change RTLIL::SigSpec::chunks() to be read-only, created interim RTLIL::SigSpec::chunks_rw()
Diffstat (limited to 'passes/cmds')
| -rw-r--r-- | passes/cmds/delete.cc | 2 | ||||
| -rw-r--r-- | passes/cmds/setundef.cc | 2 | ||||
| -rw-r--r-- | passes/cmds/show.cc | 4 | ||||
| -rw-r--r-- | passes/cmds/splitnets.cc | 2 |
4 files changed, 5 insertions, 5 deletions
diff --git a/passes/cmds/delete.cc b/passes/cmds/delete.cc index c5aa196c6..f433c4b4a 100644 --- a/passes/cmds/delete.cc +++ b/passes/cmds/delete.cc @@ -28,7 +28,7 @@ struct DeleteWireWorker void operator()(RTLIL::SigSpec &sig) { sig.optimize(); - for (auto &c : sig.chunks()) + for (auto &c : sig.chunks_rw()) if (c.wire != NULL && delete_wires_p->count(c.wire->name)) { c.wire = module->addWire(NEW_ID, c.width); c.offset = 0; diff --git a/passes/cmds/setundef.cc b/passes/cmds/setundef.cc index 7558a4e9a..619930b3a 100644 --- a/passes/cmds/setundef.cc +++ b/passes/cmds/setundef.cc @@ -48,7 +48,7 @@ struct SetundefWorker void operator()(RTLIL::SigSpec &sig) { sig.expand(); - for (auto &c : sig.chunks()) + for (auto &c : sig.chunks_rw()) if (c.wire == NULL && c.data.bits.at(0) > RTLIL::State::S1) c.data.bits.at(0) = next_bit(); sig.optimize(); diff --git a/passes/cmds/show.cc b/passes/cmds/show.cc index fde96d537..37fe44047 100644 --- a/passes/cmds/show.cc +++ b/passes/cmds/show.cc @@ -179,7 +179,7 @@ struct ShowWorker } if (sig.chunks().size() == 1) { - RTLIL::SigChunk &c = sig.chunks()[0]; + const RTLIL::SigChunk &c = sig.chunks()[0]; if (c.wire != NULL && design->selected_member(module->name, c.wire->name)) { if (!range_check || c.wire->width == c.width) return stringf("n%d", id2num(c.wire->name)); @@ -203,7 +203,7 @@ struct ShowWorker int pos = sig.size()-1; int idx = single_idx_count++; for (int i = int(sig.chunks().size())-1; i >= 0; i--) { - RTLIL::SigChunk &c = sig.chunks()[i]; + const RTLIL::SigChunk &c = sig.chunks()[i]; net = gen_signode_simple(c, false); assert(!net.empty()); if (driver) { diff --git a/passes/cmds/splitnets.cc b/passes/cmds/splitnets.cc index 8cc6a5152..d71e9727c 100644 --- a/passes/cmds/splitnets.cc +++ b/passes/cmds/splitnets.cc @@ -63,7 +63,7 @@ struct SplitnetsWorker void operator()(RTLIL::SigSpec &sig) { sig.expand(); - for (auto &c : sig.chunks()) + for (auto &c : sig.chunks_rw()) if (splitmap.count(c.wire) > 0) c = splitmap.at(c.wire).at(c.offset); sig.optimize(); |