Manual fixes for new cell connections API

6 files changed, 10 insertions, 10 deletions

diff --git a/passes/cmds/add.cc b/passes/cmds/add.cc
index 9004bf75b..1401193fd 100644
--- a/passes/cmds/add.cc
+++ b/passes/cmds/add.cc
@@ -78,7 +78,7 @@ static void add_wire(RTLIL::Design *design, RTLIL::Module *module, std::string n
 		if (it.second->connections().count(name) > 0)
 			continue;
 
-		it.second->connections()[name] = wire;
+		it.second->set(name, wire);
 		log("Added connection %s to cell %s.%s (%s).\n", name.c_str(), module->name.c_str(), it.first.c_str(), it.second->type.c_str());
 	}
 }
diff --git a/passes/cmds/connect.cc b/passes/cmds/connect.cc
index ffe7a5efa..99a28d4a0 100644
--- a/passes/cmds/connect.cc
+++ b/passes/cmds/connect.cc
@@ -30,11 +30,11 @@ static void unset_drivers(RTLIL::Design *design, RTLIL::Module *module, SigMap &
 	RTLIL::Wire *dummy_wire = module->addWire(NEW_ID, sig.size());
 
 	for (auto &it : module->cells)
-	for (auto &port : it.second->connections())
+	for (auto &port : it.second->connections_)
 		if (ct.cell_output(it.second->type, port.first))
 			sigmap(port.second).replace(sig, dummy_wire, &port.second);
 
-	for (auto &conn : module->connections())
+	for (auto &conn : module->connections_)
 		sigmap(conn.first).replace(sig, dummy_wire, &conn.first);
 }
 
@@ -176,7 +176,7 @@ struct ConnectPass : public Pass {
 			if (!RTLIL::SigSpec::parse_sel(sig, design, module, port_expr))
 				log_cmd_error("Failed to parse port expression `%s'.\n", port_expr.c_str());
 
-			module->cells.at(RTLIL::escape_id(port_cell))->connections()[RTLIL::escape_id(port_port)] = sigmap(sig);
+			module->cells.at(RTLIL::escape_id(port_cell))->set(RTLIL::escape_id(port_port), sigmap(sig));
 		}
 		else
 			log_cmd_error("Expected -set, -unset, or -port.\n");
diff --git a/passes/cmds/connwrappers.cc b/passes/cmds/connwrappers.cc
index d7560ab1a..9faeffafa 100644
--- a/passes/cmds/connwrappers.cc
+++ b/passes/cmds/connwrappers.cc
@@ -109,7 +109,7 @@ struct ConnwrappersWorker
 			if (!design->selected(module, cell))
 				continue;
 
-			for (auto &conn : cell->connections())
+			for (auto &conn : cell->connections_)
 			{
 				std::vector<RTLIL::SigBit> sigbits = sigmap(conn.second).to_sigbit_vector();
 				RTLIL::SigSpec old_sig;
diff --git a/passes/cmds/scatter.cc b/passes/cmds/scatter.cc
index 1a780466a..35ce0a110 100644
--- a/passes/cmds/scatter.cc
+++ b/passes/cmds/scatter.cc
@@ -49,7 +49,7 @@ struct ScatterPass : public Pass {
 				continue;
 
 			for (auto &c : mod_it.second->cells)
-			for (auto &p : c.second->connections())
+			for (auto &p : c.second->connections_)
 			{
 				RTLIL::Wire *wire = new RTLIL::Wire;
 				wire->name = NEW_ID;
diff --git a/passes/cmds/show.cc b/passes/cmds/show.cc
index 441268ee9..d63d98972 100644
--- a/passes/cmds/show.cc
+++ b/passes/cmds/show.cc
@@ -87,17 +87,17 @@ struct ShowWorker
 		return defaultColor;
 	}
 
-	std::string nextColor(RTLIL::SigSig &conn, std::string defaultColor)
+	std::string nextColor(const RTLIL::SigSig &conn, std::string defaultColor)
 	{
 		return nextColor(conn.first, nextColor(conn.second, defaultColor));
 	}
 
-	std::string nextColor(RTLIL::SigSpec &sig)
+	std::string nextColor(const RTLIL::SigSpec &sig)
 	{
 		return nextColor(sig, nextColor());
 	}
 
-	std::string nextColor(RTLIL::SigSig &conn)
+	std::string nextColor(const RTLIL::SigSig &conn)
 	{
 		return nextColor(conn, nextColor());
 	}
diff --git a/passes/cmds/splice.cc b/passes/cmds/splice.cc
index 94f8365bc..8b7e04062 100644
--- a/passes/cmds/splice.cc
+++ b/passes/cmds/splice.cc
@@ -182,7 +182,7 @@ struct SpliceWorker
 		for (auto &it : module->cells) {
 			if (!sel_by_wire && !design->selected(module, it.second))
 				continue;
-			for (auto &conn : it.second->connections())
+			for (auto &conn : it.second->connections_)
 				if (ct.cell_input(it.second->type, conn.first)) {
 					if (ports.size() > 0 && !ports.count(conn.first))
 						continue;