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| author | Clifford Wolf <clifford@clifford.at> | 2014-07-25 14:23:31 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2014-07-25 14:25:42 +0200 |
| commit | 5826670009e1018734de49aaf1554cb8a43d09d7 (patch) | |
| tree | e44a029cf89de640ad4761ff5144538a0549fc16 /passes/cmds | |
| parent | c762050e7fc2c733210f8cd2b147e6084af0afe1 (diff) | |
| download | yosys-5826670009e1018734de49aaf1554cb8a43d09d7.tar.gz yosys-5826670009e1018734de49aaf1554cb8a43d09d7.tar.bz2 yosys-5826670009e1018734de49aaf1554cb8a43d09d7.zip | |
Various RTLIL::SigSpec related code cleanups
Diffstat (limited to 'passes/cmds')
| -rw-r--r-- | passes/cmds/show.cc | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/passes/cmds/show.cc b/passes/cmds/show.cc index 0a1d584ca..8ff068999 100644 --- a/passes/cmds/show.cc +++ b/passes/cmds/show.cc @@ -171,13 +171,13 @@ struct ShowWorker std::string gen_signode_simple(RTLIL::SigSpec sig, bool range_check = true) { - if (sig.chunks().size() == 0) { + if (SIZE(sig) == 0) { fprintf(f, "v%d [ label=\"\" ];\n", single_idx_count); return stringf("v%d", single_idx_count++); } - if (sig.chunks().size() == 1) { - const RTLIL::SigChunk &c = sig.chunks().front(); + if (sig.is_chunk()) { + const RTLIL::SigChunk &c = sig.as_chunk(); if (c.wire != NULL && design->selected_member(module->name, c.wire->name)) { if (!range_check || c.wire->width == c.width) return stringf("n%d", id2num(c.wire->name)); |