Commit message (Collapse) | Author | Age | Files | Lines | |
---|---|---|---|---|---|
* | Markdownify README | Aleks-Daniel Jakimenko-Aleksejev | 2016-11-12 | 1 | -451/+0 |
| | | | | | This is the first commit in series. There are many other things that could be improved, this is just the first renderable version. | ||||
* | Added notes about some formal features to README | Clifford Wolf | 2016-10-14 | 1 | -2/+23 |
| | |||||
* | Fix spelling and grammar in README | Larry Doolittle | 2016-09-06 | 1 | -4/+4 |
| | |||||
* | Minor README updates | Clifford Wolf | 2016-09-03 | 1 | -4/+4 |
| | |||||
* | After reading the SV spec, using non-standard predict() instead of expect() | Clifford Wolf | 2016-07-21 | 1 | -2/+2 |
| | |||||
* | Added basic support for $expect cells | Clifford Wolf | 2016-07-13 | 1 | -0/+7 |
| | |||||
* | Small improvements in Verilog front-end docs | Clifford Wolf | 2016-05-20 | 1 | -0/+5 |
| | |||||
* | Added manual download link to README | Clifford Wolf | 2016-05-09 | 1 | -0/+4 |
| | |||||
* | Add instructions for building manual on Ubuntu | Wladimir J. van der Laan | 2016-04-03 | 1 | -0/+29 |
| | |||||
* | We have 2016 for a while now | Clifford Wolf | 2016-03-30 | 1 | -1/+1 |
| | |||||
* | Link to vlsitechnology.org for liberty files | Clifford Wolf | 2015-11-12 | 1 | -6/+4 |
| | |||||
* | Added examples/ top-level directory | Clifford Wolf | 2015-10-13 | 1 | -1/+1 |
| | |||||
* | Added $finish and $display to README | Clifford Wolf | 2015-09-18 | 1 | -0/+4 |
| | |||||
* | Switched to Python 3 | Clifford Wolf | 2015-08-22 | 1 | -1/+1 |
| | |||||
* | Another block of spelling fixes | Larry Doolittle | 2015-08-14 | 1 | -10/+10 |
| | | | | Smaller this time | ||||
* | Fixed trailing whitespaces | Clifford Wolf | 2015-07-02 | 1 | -1/+1 |
| | |||||
* | Improved attributes API and handling of "src" attributes | Clifford Wolf | 2015-04-24 | 1 | -0/+5 |
| | |||||
* | Added support for initialized xilinx brams | Clifford Wolf | 2015-04-06 | 1 | -1/+1 |
| | |||||
* | Added "keep_hierarchy" attribute | Clifford Wolf | 2015-02-25 | 1 | -0/+3 |
| | |||||
* | Added "read_verilog -nomeminit" and "nomeminit" attribute | Clifford Wolf | 2015-02-14 | 1 | -0/+5 |
| | |||||
* | Auto-detect TCL version | Clifford Wolf | 2015-02-05 | 1 | -1/+1 |
| | |||||
* | Added onehot attribute | Clifford Wolf | 2015-02-04 | 1 | -0/+3 |
| | |||||
* | Minor README changes | Clifford Wolf | 2015-02-01 | 1 | -3/+2 |
| | |||||
* | Removed TODO list from README file | Clifford Wolf | 2015-02-01 | 1 | -30/+0 |
| | |||||
* | Added yosys_banner(), Updated Copyright range | Clifford Wolf | 2015-02-01 | 1 | -1/+1 |
| | |||||
* | README stuff | Clifford Wolf | 2015-01-20 | 1 | -2/+3 |
| | |||||
* | Removed psmisc from deps list (usually fuser is already installed and the ↵ | Clifford Wolf | 2014-12-14 | 1 | -3/+2 |
| | | | | package name for it varies) | ||||
* | Added psmisc to prerequisites | Clifford Wolf | 2014-12-12 | 1 | -1/+1 |
| | |||||
* | Added missing prerequisites to README | Clifford Wolf | 2014-12-12 | 1 | -1/+2 |
| | |||||
* | Improved nomem2reg documentation | Clifford Wolf | 2014-10-30 | 1 | -1/+4 |
| | |||||
* | Added support for $readmemh/$readmemb | Clifford Wolf | 2014-10-26 | 1 | -1/+0 |
| | |||||
* | Added support for "keep" on modules | Clifford Wolf | 2014-09-29 | 1 | -0/+2 |
| | |||||
* | Added "synth" command | Clifford Wolf | 2014-09-14 | 1 | -8/+13 |
| | |||||
* | Removed yosys-svgviewer | Clifford Wolf | 2014-09-02 | 1 | -19/+18 |
| | |||||
* | Using "xdot" instead of "yosys-svgviewer" in show command | Clifford Wolf | 2014-09-02 | 1 | -1/+1 |
| | |||||
* | Added DPI-C documentation to README file | Clifford Wolf | 2014-08-22 | 1 | -0/+12 |
| | |||||
* | Archibald Rust and Clifford Wolf: ffi-based dpi_call() | Clifford Wolf | 2014-08-22 | 1 | -2/+2 |
| | |||||
* | Added "via_celltype" attribute on task/func | Clifford Wolf | 2014-08-18 | 1 | -0/+27 |
| | |||||
* | Added support for non-standard """ macro bodies | Clifford Wolf | 2014-08-13 | 1 | -0/+9 |
| | |||||
* | Added AST_MULTIRANGE (arrays with more than 1 dimension) | Clifford Wolf | 2014-08-06 | 1 | -1/+0 |
| | |||||
* | Added support for non-standard "module mod_name(...);" syntax | Clifford Wolf | 2014-08-04 | 1 | -0/+5 |
| | |||||
* | Renamed "stdcells.v" to "techmap.v" | Clifford Wolf | 2014-07-31 | 1 | -2/+1 |
| | |||||
* | Added links to some liberty files to README | Clifford Wolf | 2014-06-28 | 1 | -0/+8 |
| | |||||
* | Added more calls to "hierarchy" to README file | Clifford Wolf | 2014-06-15 | 1 | -3/+8 |
| | |||||
* | Added read_verilog -sv options, added support for bit, logic, | Clifford Wolf | 2014-06-12 | 1 | -3/+13 |
| | | | | allways_ff, always_comb, and always_latch | ||||
* | Updated README | Clifford Wolf | 2014-04-18 | 1 | -18/+11 |
| | |||||
* | Added libs/minisat (copy of minisat git master) | Clifford Wolf | 2014-03-12 | 1 | -15/+0 |
| | |||||
* | Merged a few fixes for non-posix systems from github.com/Siesh1oo/yosys | Clifford Wolf | 2014-03-11 | 1 | -1/+1 |
| | | | | (see https://github.com/cliffordwolf/yosys/pull/28) | ||||
* | Updated todo items in README file | Clifford Wolf | 2014-02-05 | 1 | -2/+2 |
| | |||||
* | Added constant size expression support of sized constants | Clifford Wolf | 2014-02-01 | 1 | -0/+4 |
| |