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Author
Age
Files
Lines
*
Cleanup
Eddie Hung
2019-06-05
2
-17
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+0
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Call shregmap -tech xilinx_static
Eddie Hung
2019-06-05
1
-1
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+1
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Revert "Move ff_map back after ABC for shregmap"
Eddie Hung
2019-06-05
1
-4
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+4
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Add -tech xilinx_static
Eddie Hung
2019-06-05
1
-2
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+13
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Refactor to ShregmapTechXilinx7Static
Eddie Hung
2019-06-05
1
-46
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+86
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shregmap -tech xilinx_dynamic to work -params and -enpol
Eddie Hung
2019-06-05
1
-6
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+26
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Merge remote-tracking branch 'origin/master' into xc7mux
Eddie Hung
2019-06-05
3
-28
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+95
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Merge pull request #1066 from YosysHQ/clifford/fix1056
Clifford Wolf
2019-06-05
1
-1
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+0
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Remove yosys_banner() from python wrapper init, fixes #1056
Clifford Wolf
2019-06-05
1
-1
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+0
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Major rewrite of wire selection in setundef -init
Clifford Wolf
2019-06-05
1
-30
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+89
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Indent fix
Clifford Wolf
2019-06-05
1
-23
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+25
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Merge pull request #999 from jakobwenzel/setundefInitFix
Clifford Wolf
2019-06-05
1
-16
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+23
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initialize more registers in setundef -init
Jakob Wenzel
2019-05-09
1
-16
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+23
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Fix typo in fmcombine log message, fixes #1063
Clifford Wolf
2019-06-05
1
-2
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+2
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Merge remote-tracking branch 'origin/clifford/fix1065' into xc7mux
Eddie Hung
2019-06-05
2
-2
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+2
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Suppress driver-driver conflict warning for unknown cell types, fixes #1065
Clifford Wolf
2019-06-05
1
-1
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+1
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Merge pull request #1062 from tux3/patch-1
Clifford Wolf
2019-06-04
1
-1
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+1
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README.md: Missing formatting for <tag>
Tux3
2019-06-04
1
-1
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+1
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Rename shregmap -tech xilinx -> xilinx_dynamic
Eddie Hung
2019-06-04
2
-6
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+6
*
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Add log_assert to ensure no loops
Eddie Hung
2019-06-04
1
-1
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+15
*
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Only toposort builtin and abc types
Eddie Hung
2019-06-04
1
-6
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+9
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Add space between -D and _ABC
Eddie Hung
2019-06-04
1
-2
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+2
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Add (* abc_flop_q *) to brams_bb.v
Eddie Hung
2019-06-04
1
-8
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+8
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Fix name clash
Eddie Hung
2019-06-04
1
-11
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+11
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Add mux_map.v for wide mux
Eddie Hung
2019-06-04
4
-30
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+82
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Move ff_map back after ABC for shregmap
Eddie Hung
2019-06-03
1
-4
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+4
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Respect -nocarry
Eddie Hung
2019-06-03
1
-1
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+3
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Fix pmux2shiftx logic
Eddie Hung
2019-06-03
1
-1
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+1
*
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Merge mistake
Eddie Hung
2019-06-03
1
-14
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+6
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Merge remote-tracking branch 'origin/master' into xc7mux
Eddie Hung
2019-06-03
6
-5
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+40
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Merge pull request #1061 from YosysHQ/eddie/techmap_and_arith_map
Eddie Hung
2019-06-03
1
-6
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+5
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Remove extra newline
Eddie Hung
2019-06-03
1
-1
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+0
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Execute techmap and arith_map simultaneously
Eddie Hung
2019-06-03
1
-6
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+6
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Only support Symbiotic EDA flavored Verific
Clifford Wolf
2019-06-02
1
-0
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+8
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Fix "tee" handling of log_streams
Clifford Wolf
2019-05-31
1
-0
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+5
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Enable Verific flag veri_elaborate_top_level_modules_having_interface_ports, ...
Clifford Wolf
2019-05-30
1
-0
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+3
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Merge pull request #1057 from mmicko/fix_478
Clifford Wolf
2019-05-30
1
-0
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+4
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Aded one more load of .conf to support change of prefix
Miodrag Milanovic
2019-05-29
1
-0
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+4
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Merge pull request #1049 from YosysHQ/clifford/fix1047
Clifford Wolf
2019-05-28
2
-4
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+15
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Do not use shiftmul peepopt pattern when mul result is truncated, fixes #1047
Clifford Wolf
2019-05-28
2
-4
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+15
*
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Typo
Eddie Hung
2019-06-03
1
-1
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+1
*
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IS_C_INVERTED
Eddie Hung
2019-06-03
1
-4
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+4
*
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Fix `ifndef
Eddie Hung
2019-06-03
1
-1
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+1
*
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Make SB_LUT4 a whitebox, SB_DFF a blackbox (for now)
Eddie Hung
2019-06-03
4
-8
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+8
*
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Assert that box_unique_id is indeed unique
Eddie Hung
2019-06-03
1
-2
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+3
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Remove dupe
Eddie Hung
2019-06-03
1
-7
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+7
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Skip internal modules when generating box_unique_id
Eddie Hung
2019-06-03
1
-0
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+1
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When creating new holes cell, inherit parameters too
Eddie Hung
2019-06-03
1
-1
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+3
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Ooopsie
Eddie Hung
2019-06-03
1
-1
/
+1
*
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Consistent with xilinx
Eddie Hung
2019-06-03
3
-4
/
+4
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