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| author | Eddie Hung <eddie@fpgeh.com> | 2019-06-05 09:56:51 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-06-05 09:56:51 -0700 |
| commit | b5aff1de0432e79fb26cc87a2bbd4aae5f4b0dfb (patch) | |
| tree | c7cc7ccdc1ac7c896d6c36e7754edc057e8e1435 | |
| parent | 94a5f4e60985fc1e3fea75eec85638fa29874bea (diff) | |
| parent | 8a6f9977f659d350cca936b45cb8b441d5a67eeb (diff) | |
| download | yosys-b5aff1de0432e79fb26cc87a2bbd4aae5f4b0dfb.tar.gz yosys-b5aff1de0432e79fb26cc87a2bbd4aae5f4b0dfb.tar.bz2 yosys-b5aff1de0432e79fb26cc87a2bbd4aae5f4b0dfb.zip | |
Merge remote-tracking branch 'origin/clifford/fix1065' into xc7mux
| -rw-r--r-- | README.md | 2 | ||||
| -rw-r--r-- | passes/opt/opt_clean.cc | 2 |
2 files changed, 2 insertions, 2 deletions
@@ -413,7 +413,7 @@ Verilog Attributes and non-standard features $ yosys -p 'plugin -a foo -i /lib/libm.so; read_verilog dpitest.v' - Sized constants (the syntax ``<size>'s?[bodh]<value>``) support constant - expressions as <size>. If the expression is not a simple identifier, it + expressions as ``<size>``. If the expression is not a simple identifier, it must be put in parentheses. Examples: ``WIDTH'd42``, ``(4+2)'b101010`` - The system tasks ``$finish``, ``$stop`` and ``$display`` are supported in diff --git a/passes/opt/opt_clean.cc b/passes/opt/opt_clean.cc index 7011d4602..cfb0f788a 100644 --- a/passes/opt/opt_clean.cc +++ b/passes/opt/opt_clean.cc @@ -106,7 +106,7 @@ void rmunused_module_cells(Module *module, bool verbose) if (raw_bit.wire == nullptr) continue; auto bit = sigmap(raw_bit); - if (bit.wire == nullptr) + if (bit.wire == nullptr && ct_all.cell_known(cell->type)) driver_driver_logs[raw_sigmap(raw_bit)].push_back(stringf("Driver-driver conflict " "for %s between cell %s.%s and constant %s in %s: Resolved using constant.", log_signal(raw_bit), log_id(cell), log_id(it2.first), log_signal(bit), log_id(module))); |