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author | Eddie Hung <eddie@fpgeh.com> | 2019-06-05 12:28:26 -0700 |
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committer | Eddie Hung <eddie@fpgeh.com> | 2019-06-05 12:28:26 -0700 |
commit | 2c18d530ea69094e7ed46dcf781d8f2517d4c61e (patch) | |
tree | 9a639e985e7c6c0ad9dd9b87b740cbbbb8c43e34 | |
parent | e473e7456545d702c011ee7872956f94a8522865 (diff) | |
download | yosys-2c18d530ea69094e7ed46dcf781d8f2517d4c61e.tar.gz yosys-2c18d530ea69094e7ed46dcf781d8f2517d4c61e.tar.bz2 yosys-2c18d530ea69094e7ed46dcf781d8f2517d4c61e.zip |
Call shregmap -tech xilinx_static
-rw-r--r-- | techlibs/xilinx/synth_xilinx.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc index e825a032c..7686f2cbc 100644 --- a/techlibs/xilinx/synth_xilinx.cc +++ b/techlibs/xilinx/synth_xilinx.cc @@ -304,7 +304,7 @@ struct SynthXilinxPass : public ScriptPass // This shregmap call infers fixed length shift registers after abc // has performed any necessary retiming if (!nosrl || help_mode) - run("shregmap -minlen 3 -init -params -enpol any_or_none", "(skip if '-nosrl')"); + run("shregmap -tech xilinx_static -minlen 3", "(skip if '-nosrl')"); run("techmap -map +/xilinx/lut_map.v -map +/xilinx/cells_map.v"); run("clean"); } |