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| author | Eddie Hung <eddie@fpgeh.com> | 2019-06-03 20:21:41 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-06-03 20:21:41 -0700 |
| commit | b6e59741ae6e4ec57affb9ab168a9d08cdb6d04f (patch) | |
| tree | e943b8ad9c7d81dc734fb76d2eaf8bbc32ef366b | |
| parent | c9a0bac5413dff55e141deb4098b63ca4c62e5b1 (diff) | |
| download | yosys-b6e59741ae6e4ec57affb9ab168a9d08cdb6d04f.tar.gz yosys-b6e59741ae6e4ec57affb9ab168a9d08cdb6d04f.tar.bz2 yosys-b6e59741ae6e4ec57affb9ab168a9d08cdb6d04f.zip | |
Typo
| -rw-r--r-- | techlibs/xilinx/cells_sim.v | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/techlibs/xilinx/cells_sim.v b/techlibs/xilinx/cells_sim.v index c8450f8d1..16b8b4949 100644 --- a/techlibs/xilinx/cells_sim.v +++ b/techlibs/xilinx/cells_sim.v @@ -262,7 +262,7 @@ module FDCE ((* abc_flop_q *) output reg Q, input C, CE, (* abc_flop_d *) input endmodule (* abc_box_id = 9, abc_flop /*, lib_whitebox*/ *) -module FDPE ((* abc_flop_q *) output reg Q, input C, CE, (* abc_flop_q *) input D, input PRE); +module FDPE ((* abc_flop_q *) output reg Q, input C, CE, (* abc_flop_d *) input D, input PRE); parameter [0:0] INIT = 1'b0; parameter [0:0] IS_C_INVERTED = 1'b0; parameter [0:0] IS_D_INVERTED = 1'b0; |