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| author | Eddie Hung <eddie@fpgeh.com> | 2019-06-04 11:54:08 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-06-04 11:54:08 -0700 |
| commit | 82d41bc2f2460a06e153eac4f3968ef29ce5a63d (patch) | |
| tree | cd75df1085cfaab7c6967aad716d73a4401790e0 | |
| parent | f0e93f33cf089a1c1924e569700792bf198b6810 (diff) | |
| download | yosys-82d41bc2f2460a06e153eac4f3968ef29ce5a63d.tar.gz yosys-82d41bc2f2460a06e153eac4f3968ef29ce5a63d.tar.bz2 yosys-82d41bc2f2460a06e153eac4f3968ef29ce5a63d.zip | |
Add space between -D and _ABC
| -rw-r--r-- | techlibs/xilinx/synth_xilinx.cc | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc index 360418975..e9eccfc0e 100644 --- a/techlibs/xilinx/synth_xilinx.cc +++ b/techlibs/xilinx/synth_xilinx.cc @@ -203,9 +203,9 @@ struct SynthXilinxPass : public ScriptPass { if (check_label("begin")) { if (vpr) - run("read_verilog -lib -D_ABC -D_EXPLICIT_CARRY +/xilinx/cells_sim.v"); + run("read_verilog -lib -D _ABC -D_EXPLICIT_CARRY +/xilinx/cells_sim.v"); else - run("read_verilog -lib -D_ABC +/xilinx/cells_sim.v"); + run("read_verilog -lib -D _ABC +/xilinx/cells_sim.v"); run("read_verilog -lib +/xilinx/cells_xtra.v"); |