| Commit message (Expand) | Author | Age | Files | Lines |
|---|
| * | simul: improve support of PSL endpoints | Tristan Gingold | 2023-02-08 | 1 | -8/+1 |
| * | simul: handle signal assignment to procedure individual associations | Tristan Gingold | 2023-02-08 | 1 | -8/+19 |
| * | synth: use same layout for records in memory as translate | Tristan Gingold | 2023-02-08 | 1 | -1/+1 |
| * | simul: refactoring, expose more subprograms | Tristan Gingold | 2023-02-04 | 3 | -35/+47 |
| * | elab-debugger: also pass top instance on break_time | Tristan Gingold | 2023-01-31 | 1 | -1/+1 |
| * | ghdlsimul: extract simul-main from simul-vhdl_simul | Tristan Gingold | 2023-01-31 | 5 | -108/+182 |
| * | simul-vhdl_elab: fix computation of nbr of sources | Tristan Gingold | 2023-01-30 | 1 | -2/+7 |
| * | simul: use same packing order for nets and for values. | Tristan Gingold | 2023-01-30 | 2 | -27/+25 |
| * | simul: improve info sig and info time | Tristan Gingold | 2023-01-30 | 1 | -52/+78 |
| * | synth: create sub-instace for processes | Tristan Gingold | 2023-01-20 | 1 | -0/+1 |
| * | simul: handle PSL endpoints | Tristan Gingold | 2023-01-18 | 2 | -10/+29 |
| * | simul: fix last_value for post vhdl 87 | Tristan Gingold | 2023-01-18 | 2 | -103/+145 |
| * | simul: disable --trace-signals | Tristan Gingold | 2023-01-15 | 1 | -0/+4 |
| * | synth: improve error propagation on slices | Tristan Gingold | 2023-01-14 | 1 | -1/+4 |
| * | synth: handle protected functions in conversion functions | Tristan Gingold | 2023-01-12 | 1 | -1/+2 |
| * | simul: handle PSL aborts | Tristan Gingold | 2023-01-12 | 2 | -0/+67 |
| * | simul: fix handling of drivers/sensitivity within processes | Tristan Gingold | 2023-01-12 | 2 | -21/+24 |
| * | simul: avoid a crash after an error in a condition | Tristan Gingold | 2023-01-11 | 1 | -1/+6 |
| * | synth: improve support of PSL endpoints | Tristan Gingold | 2023-01-11 | 1 | -1/+2 |
| * | simul: allow function calls in signal association by value | Tristan Gingold | 2023-01-11 | 1 | -0/+2 |
| * | simul: handle psl assume directives | Tristan Gingold | 2023-01-11 | 1 | -0/+2 |
| * | simul: add sensitivity for psl processes | Tristan Gingold | 2023-01-11 | 1 | -4/+7 |
| * | simul: improve assertion messages for psl | Tristan Gingold | 2023-01-11 | 1 | -5/+15 |
| * | simul: add debug command 'run -s' | Tristan Gingold | 2023-01-11 | 3 | -8/+18 |
| * | simul: handle array element resolution | Tristan Gingold | 2023-01-11 | 1 | -1/+6 |
| * | simul: improve debugger output | Tristan Gingold | 2023-01-11 | 1 | -5/+5 |
| * | simul: enable all debug features during elaboration | Tristan Gingold | 2023-01-10 | 2 | -5/+3 |
| * | synth: handle indexes in arrays conversion | Tristan Gingold | 2023-01-10 | 1 | -2/+2 |
| * | simul: handle inertial assignments | Tristan Gingold | 2023-01-10 | 1 | -2/+14 |
| * | synth-vhdl_aggr: optimize common aggregate | Tristan Gingold | 2023-01-10 | 1 | -6/+8 |
| * | synth: always create shared variables | Tristan Gingold | 2023-01-09 | 1 | -21/+2 |
| * | simul: set assertion hook before elaboration | Tristan Gingold | 2023-01-09 | 1 | -3/+3 |
| * | simul-vhdl_simul: fix effective value writes | Tristan Gingold | 2023-01-09 | 1 | -1/+20 |
| * | simul: handle function calls in sensitivity compute. | Tristan Gingold | 2023-01-09 | 1 | -0/+6 |
| * | simul: improve error recovery during elaboration | Tristan Gingold | 2023-01-09 | 1 | -3/+12 |
| * | simul: handle PSL cover | Tristan Gingold | 2023-01-09 | 2 | -3/+7 |
| * | simul: handle force/release signal assignments | Tristan Gingold | 2023-01-03 | 1 | -0/+174 |
| * | synth: introduce type_array_unbounded | Tristan Gingold | 2023-01-03 | 3 | -0/+4 |
| * | simul: skip psl default clock in declarations | Tristan Gingold | 2023-01-03 | 1 | -0/+1 |
| * | synth: fix to_string for character | Tristan Gingold | 2023-01-02 | 1 | -0/+3 |
| * | synth: elaborate case generate statements | Tristan Gingold | 2023-01-01 | 1 | -1/+2 |
| * | simul: handle nested packages | Tristan Gingold | 2023-01-01 | 1 | -1/+5 |
| * | synth: add statement in context, adjust path/instance name attributes | Tristan Gingold | 2022-12-31 | 1 | -1/+1 |
| * | simul: handle driving and driving_value attributes | Tristan Gingold | 2022-12-26 | 1 | -6/+39 |
| * | simul: handle transaction attribute | Tristan Gingold | 2022-12-26 | 2 | -3/+13 |
| * | simul: handle aggregate is guarded signal assignment target | Tristan Gingold | 2022-12-26 | 1 | -7/+29 |
| * | vhdl-canon: handle unaffected | Tristan Gingold | 2022-12-26 | 1 | -0/+5 |
| * | synth: add value_sig_val to handle individual signal associations | Tristan Gingold | 2022-12-26 | 1 | -28/+166 |
| * | vhdl-sem_inst: add instantiate_interface_package_declaration | Tristan Gingold | 2022-12-18 | 1 | -0/+4 |
| * | vhdl: fix some compiler warnings | Tristan Gingold | 2022-11-08 | 2 | -4/+0 |
