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author | Tristan Gingold <tgingold@free.fr> | 2023-01-10 18:43:33 +0100 |
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committer | Tristan Gingold <tgingold@free.fr> | 2023-01-10 21:46:58 +0100 |
commit | 26ed24d29ba32865be97ff1023d6442021a4db60 (patch) | |
tree | d1b90d9aca10d5c4f76c28c1de309d275fcc229f /src/simul | |
parent | 8bb886e329c1a7cbf0187cbc7a0b177c7cdd0b79 (diff) | |
download | ghdl-26ed24d29ba32865be97ff1023d6442021a4db60.tar.gz ghdl-26ed24d29ba32865be97ff1023d6442021a4db60.tar.bz2 ghdl-26ed24d29ba32865be97ff1023d6442021a4db60.zip |
synth: handle indexes in arrays conversion
Diffstat (limited to 'src/simul')
-rw-r--r-- | src/simul/simul-vhdl_simul.adb | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/simul/simul-vhdl_simul.adb b/src/simul/simul-vhdl_simul.adb index a2a8b3cfb..cf9b1036e 100644 --- a/src/simul/simul-vhdl_simul.adb +++ b/src/simul/simul-vhdl_simul.adb @@ -904,7 +904,7 @@ package body Simul.Vhdl_Simul is Sub_Inst := Synth_Subprogram_Call_Instance (Inst, Imp, Imp); Synth_Subprogram_Associations - (Sub_Inst, Inst, Inter_Chain, Assoc_Chain); + (Sub_Inst, Inst, Inter_Chain, Assoc_Chain, Call); Synth.Vhdl_Static_Proc.Synth_Static_Procedure (Sub_Inst, Imp, Call); @@ -937,7 +937,7 @@ package body Simul.Vhdl_Simul is -- one! Set_Uninstantiated_Scope (Sub_Inst, Imp); Synth_Subprogram_Associations - (Sub_Inst, Inst, Inter_Chain, Assoc_Chain); + (Sub_Inst, Inst, Inter_Chain, Assoc_Chain, Call); Process.Instance := Sub_Inst; Synth.Vhdl_Decls.Synth_Declarations |