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authorTristan Gingold <tgingold@free.fr>2023-01-18 21:32:59 +0100
committerTristan Gingold <tgingold@free.fr>2023-01-20 21:54:35 +0100
commit418800b56e3296eec94e56707ebad7dcd1d1c6ee (patch)
tree3dc316321d3bdef39629dc57dde9651e276b9f2b /src/simul
parenta53b01b53c3c8225a832e8f20d019ac39d68ce38 (diff)
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synth: create sub-instace for processes
Diffstat (limited to 'src/simul')
-rw-r--r--src/simul/simul-vhdl_elab.adb1
1 files changed, 1 insertions, 0 deletions
diff --git a/src/simul/simul-vhdl_elab.adb b/src/simul/simul-vhdl_elab.adb
index eb481479b..8e2db63ad 100644
--- a/src/simul/simul-vhdl_elab.adb
+++ b/src/simul/simul-vhdl_elab.adb
@@ -1125,6 +1125,7 @@ package body Simul.Vhdl_Elab is
if Get_Kind (Proc) in Iir_Kinds_Process_Statement then
Proc_Inst := Make_Elab_Instance (Processes_Table.Table (I).Inst,
Proc, Proc, Null_Node);
+ Set_Sub_Instance (Processes_Table.Table (I).Inst, Proc, Proc_Inst);
Processes_Table.Table (I).Inst := Proc_Inst;
Set_Instance_Const (Proc_Inst, True);
Synth.Vhdl_Decls.Synth_Declarations