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| author | Tristan Gingold <tgingold@free.fr> | 2023-02-08 16:51:19 +0100 |
|---|---|---|
| committer | Tristan Gingold <tgingold@free.fr> | 2023-02-08 16:51:19 +0100 |
| commit | 5c18960e811ace9ad7418e452c4d5c802ad30e2f (patch) | |
| tree | 6059f42cebf652808c85eec46c74bdaf43321d09 /src/simul | |
| parent | b0bfbef2ef699e5b2823f9a4941b8690628b9b7a (diff) | |
| download | ghdl-5c18960e811ace9ad7418e452c4d5c802ad30e2f.tar.gz ghdl-5c18960e811ace9ad7418e452c4d5c802ad30e2f.tar.bz2 ghdl-5c18960e811ace9ad7418e452c4d5c802ad30e2f.zip | |
simul: improve support of PSL endpoints
Diffstat (limited to 'src/simul')
| -rw-r--r-- | src/simul/simul-vhdl_simul.adb | 9 |
1 files changed, 1 insertions, 8 deletions
diff --git a/src/simul/simul-vhdl_simul.adb b/src/simul/simul-vhdl_simul.adb index d93d13869..e898031bf 100644 --- a/src/simul/simul-vhdl_simul.adb +++ b/src/simul/simul-vhdl_simul.adb @@ -2245,14 +2245,7 @@ package body Simul.Vhdl_Simul is -- TODO null; when Iir_Kind_Psl_Endpoint_Declaration => - declare - Val : Valtyp; - begin - Val := Create_Value_Memory (Bit_Type, Global_Pool'Access); - Write_Discrete (Val, 0); - -- TODO: create the object/signal during elaboration - Create_Object (Proc.Instance, Proc.Proc, Val); - end; + null; when others => null; end case; |