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| author | Tristan Gingold <tgingold@free.fr> | 2023-01-14 21:24:58 +0100 |
|---|---|---|
| committer | Tristan Gingold <tgingold@free.fr> | 2023-01-15 11:36:09 +0100 |
| commit | 84bf6bee9480a93b789a4d1ffee380117e3ab177 (patch) | |
| tree | 71e89aeb7fc80ce212d31a27058fceca5074cb85 /src/simul | |
| parent | ee94b3820724b653839ea7ad338b2d0d265e4066 (diff) | |
| download | ghdl-84bf6bee9480a93b789a4d1ffee380117e3ab177.tar.gz ghdl-84bf6bee9480a93b789a4d1ffee380117e3ab177.tar.bz2 ghdl-84bf6bee9480a93b789a4d1ffee380117e3ab177.zip | |
simul: disable --trace-signals
Diffstat (limited to 'src/simul')
| -rw-r--r-- | src/simul/simul-vhdl_simul.adb | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/src/simul/simul-vhdl_simul.adb b/src/simul/simul-vhdl_simul.adb index 7d1a4312a..c03da08f1 100644 --- a/src/simul/simul-vhdl_simul.adb +++ b/src/simul/simul-vhdl_simul.adb @@ -4128,8 +4128,12 @@ package body Simul.Vhdl_Simul is pragma Assert (Areapools.Is_Empty (Expr_Pool)); pragma Assert (Areapools.Is_Empty (Process_Pool)); + -- Copy flag. Synth.Flags.Severity_Level := Grt.Options.Severity_Level; + -- Not supported. + Grt.Options.Trace_Signals := False; + if Flag_Interractive then Elab.Debugger.Debug_Elab (Vhdl_Elab.Top_Instance); end if; |