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| author | root <root@no.no.james.local> | 2018-05-17 18:12:57 +0100 |
|---|---|---|
| committer | root <root@no.no.james.local> | 2018-05-17 18:12:57 +0100 |
| commit | 85b8cf5877ed7082564a47d94917ca7151977625 (patch) | |
| tree | 31cec84d278a478105c3f12c9d04158315c40053 /silence_detector.vhd | |
| parent | 3769dd04597e39140755bd4b92023570e6fcde3c (diff) | |
| download | rob_spdif-85b8cf5877ed7082564a47d94917ca7151977625.tar.gz rob_spdif-85b8cf5877ed7082564a47d94917ca7151977625.tar.bz2 rob_spdif-85b8cf5877ed7082564a47d94917ca7151977625.zip | |
minor fixes, make clock simulator happy and fix AS programming
Diffstat (limited to 'silence_detector.vhd')
| -rw-r--r-- | silence_detector.vhd | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/silence_detector.vhd b/silence_detector.vhd index 14cc72e..820beed 100644 --- a/silence_detector.vhd +++ b/silence_detector.vhd @@ -53,7 +53,7 @@ begin pulse_out => interval ); - process (last_d, d, clk, sos, silent_thresh, silence) + process (last_d, d, clk, sos, silent_thresh, silence, n_reset) begin if n_reset = '0' then silence <= (others => '0'); @@ -74,7 +74,7 @@ begin end if; end process; - process (clk, sos, interval, valid_thresh, validity) + process (clk, sos, interval, valid_thresh, validity, n_reset) begin if n_reset = '0' then validity <= (others => '0'); |