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authorroot <root@no.no.james.local>2018-05-17 18:12:57 +0100
committerroot <root@no.no.james.local>2018-05-17 18:12:57 +0100
commit85b8cf5877ed7082564a47d94917ca7151977625 (patch)
tree31cec84d278a478105c3f12c9d04158315c40053
parent3769dd04597e39140755bd4b92023570e6fcde3c (diff)
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minor fixes, make clock simulator happy and fix AS programming
-rw-r--r--Makefile17
-rw-r--r--pll200.vhd2
-rw-r--r--silence_detector.vhd4
-rw-r--r--spdif.qsf1
-rw-r--r--spdif.sdc5
5 files changed, 11 insertions, 18 deletions
diff --git a/Makefile b/Makefile
index b73ea37..7d2149e 100644
--- a/Makefile
+++ b/Makefile
@@ -6,8 +6,7 @@ S2=${S1:pll200.vhd=}
TIDY_SRC=${S2}
SOF=output_files/${PROJ}.sof
-POF=${PROJ}.pof
-JIC=${PROJ}.jic
+POF=output_files/${PROJ}.pof
default: load_sof.stamp sim.stamp
@@ -38,8 +37,8 @@ sim.stamp: fit.stamp
load_sof.stamp: ${SOF}
tools/wrap quartus_pgm -m JTAG -o "p;${SOF}"
-#flash: ${POF}
-# tools/wrap quartus_pgm -m AS -o "p;${POF}"
+flash: ${POF}
+ tools/wrap quartus_pgm -m AS -o "p;${POF}"
quartus:
tools/wrap quartus ${PROJ}.qpf
@@ -57,16 +56,6 @@ clean:
-${JIC}:${SOF}
- tools/wrap quartus_cpf -c ${PROJ}.cof
-
-
-flash:${JIC}
- tools/wrap quartus_pgm -m JTAG -o "ip;${JIC}"
- tools/wrap quartus_pgm -m JTAG -o "p;${SOF}"
-
-
-
tidy:
for i in ${TIDY_SRC}; do tools/vhdl-pretty < $$i > $$i.pp && mv -f $$i $$i.orig && mv $$i.pp $$i ; done
diff --git a/pll200.vhd b/pll200.vhd
index ab2858f..142cd94 100644
--- a/pll200.vhd
+++ b/pll200.vhd
@@ -144,7 +144,7 @@ BEGIN
clk0_phase_shift => "0",
compensate_clock => "CLK0",
gate_lock_signal => "NO",
- inclk0_input_frequency => 41666,
+ inclk0_input_frequency => 20000,
intended_device_family => "Cyclone II",
invalid_lock_multiplier => 5,
lpm_hint => "CBX_MODULE_PREFIX=pll200",
diff --git a/silence_detector.vhd b/silence_detector.vhd
index 14cc72e..820beed 100644
--- a/silence_detector.vhd
+++ b/silence_detector.vhd
@@ -53,7 +53,7 @@ begin
pulse_out => interval
);
- process (last_d, d, clk, sos, silent_thresh, silence)
+ process (last_d, d, clk, sos, silent_thresh, silence, n_reset)
begin
if n_reset = '0' then
silence <= (others => '0');
@@ -74,7 +74,7 @@ begin
end if;
end process;
- process (clk, sos, interval, valid_thresh, validity)
+ process (clk, sos, interval, valid_thresh, validity, n_reset)
begin
if n_reset = '0' then
validity <= (others => '0');
diff --git a/spdif.qsf b/spdif.qsf
index 12a4f19..31333b7 100644
--- a/spdif.qsf
+++ b/spdif.qsf
@@ -24,6 +24,7 @@ set_global_assignment -name FAMILY "Cyclone II"
set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL"
set_location_assignment PIN_143 -to spdif_in
set_location_assignment PIN_73 -to n_rst_in
+ set_global_assignment -name STRATIX_CONFIGURATION_DEVICE EPCS4
set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to spdif_in
set_location_assignment PIN_112 -to n_mute_out
diff --git a/spdif.sdc b/spdif.sdc
index f74ef07..e0eb00c 100644
--- a/spdif.sdc
+++ b/spdif.sdc
@@ -7,9 +7,12 @@ set_time_format -unit ns -decimal_places 3
##############################################################################
# Create Input reference clocks
create_clock -name {xtal_50mhz} -period 20.000 -waveform { 0.000 10.000 } [get_ports { xtal_50mhz }]
+create_clock -name {det1_clk} -period 10.000 -waveform { 0.000 5.000 } [get_nets { det1|divider:div1|q }]
+create_clock -name {det2_clk} -period 25.000 -waveform { 0.000 12.500 } [get_nets { det2|divider:div1|q }]
+create_clock -name {det3_clk} -period 40.000 -waveform { 0.000 20.000 } [get_nets { det3|divider:div1|q }]
##############################################################################
# Now that we have created the custom clocks which will be base clocks,
# derive_pll_clock is used to calculate all remaining clocks for PLLs
derive_pll_clocks -create_base_clocks
-derive_clock_uncertainty \ No newline at end of file
+derive_clock_uncertainty