diff options
| author | root <root@no.no.james.local> | 2018-05-17 18:12:57 +0100 |
|---|---|---|
| committer | root <root@no.no.james.local> | 2018-05-17 18:12:57 +0100 |
| commit | 85b8cf5877ed7082564a47d94917ca7151977625 (patch) | |
| tree | 31cec84d278a478105c3f12c9d04158315c40053 /pll200.vhd | |
| parent | 3769dd04597e39140755bd4b92023570e6fcde3c (diff) | |
| download | rob_spdif-85b8cf5877ed7082564a47d94917ca7151977625.tar.gz rob_spdif-85b8cf5877ed7082564a47d94917ca7151977625.tar.bz2 rob_spdif-85b8cf5877ed7082564a47d94917ca7151977625.zip | |
minor fixes, make clock simulator happy and fix AS programming
Diffstat (limited to 'pll200.vhd')
| -rw-r--r-- | pll200.vhd | 2 |
1 files changed, 1 insertions, 1 deletions
@@ -144,7 +144,7 @@ BEGIN clk0_phase_shift => "0", compensate_clock => "CLK0", gate_lock_signal => "NO", - inclk0_input_frequency => 41666, + inclk0_input_frequency => 20000, intended_device_family => "Cyclone II", invalid_lock_multiplier => 5, lpm_hint => "CBX_MODULE_PREFIX=pll200", |