From 85b8cf5877ed7082564a47d94917ca7151977625 Mon Sep 17 00:00:00 2001 From: root Date: Thu, 17 May 2018 18:12:57 +0100 Subject: minor fixes, make clock simulator happy and fix AS programming --- pll200.vhd | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'pll200.vhd') diff --git a/pll200.vhd b/pll200.vhd index ab2858f..142cd94 100644 --- a/pll200.vhd +++ b/pll200.vhd @@ -144,7 +144,7 @@ BEGIN clk0_phase_shift => "0", compensate_clock => "CLK0", gate_lock_signal => "NO", - inclk0_input_frequency => 41666, + inclk0_input_frequency => 20000, intended_device_family => "Cyclone II", invalid_lock_multiplier => 5, lpm_hint => "CBX_MODULE_PREFIX=pll200", -- cgit v1.2.3