diff options
Diffstat (limited to 'libopencm3/include/libopencm3/lpc43xx')
26 files changed, 9228 insertions, 0 deletions
diff --git a/libopencm3/include/libopencm3/lpc43xx/adc.h b/libopencm3/include/libopencm3/lpc43xx/adc.h new file mode 100644 index 0000000..c63c1e4 --- /dev/null +++ b/libopencm3/include/libopencm3/lpc43xx/adc.h @@ -0,0 +1,113 @@ +/** @defgroup adc_defines ADC Defines + +@brief <b>Defined Constants and Types for the LPC43xx A/D Converter</b> + +@ingroup LPC43xx_defines + +@version 1.0.0 + +@author @htmlonly © @endhtmlonly 2012 Michael Ossmann <mike@ossmann.com> + +@date 10 March 2013 + +LGPL License Terms @ref lgpl_license + */ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2012 Michael Ossmann <mike@ossmann.com> + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see <http://www.gnu.org/licenses/>. + */ + +#ifndef LPC43XX_ADC_H +#define LPC43XX_ADC_H + +/**@{*/ + +#include <libopencm3/cm3/common.h> +#include <libopencm3/lpc43xx/memorymap.h> + +/* --- Convenience macros -------------------------------------------------- */ + +/* ADC port base addresses (for convenience) */ +#define ADC0 ADC0_BASE +#define ADC1 ADC1_BASE + + +/* --- ADC registers ------------------------------------------------------- */ + +/* A/D Control Register */ +#define ADC_CR(port) MMIO32(port + 0x000) +#define ADC0_CR ADC_CR(ADC0) +#define ADC1_CR ADC_CR(ADC1) + +/* A/D Global Data Register */ +#define ADC_GDR(port) MMIO32(port + 0x004) +#define ADC0_GDR ADC_GDR(ADC0) +#define ADC1_GDR ADC_GDR(ADC1) + +/* A/D Interrupt Enable Register */ +#define ADC_INTEN(port) MMIO32(port + 0x00C) +#define ADC0_INTEN ADC_INTEN(ADC0) +#define ADC1_INTEN ADC_INTEN(ADC1) + +/* A/D Channel 0 Data Register */ +#define ADC_DR0(port) MMIO32(port + 0x010) +#define ADC0_DR0 ADC_DR0(ADC0) +#define ADC1_DR0 ADC_DR0(ADC1) + +/* A/D Channel 1 Data Register */ +#define ADC_DR1(port) MMIO32(port + 0x014) +#define ADC0_DR1 ADC_DR1(ADC0) +#define ADC1_DR1 ADC_DR1(ADC1) + +/* A/D Channel 2 Data Register */ +#define ADC_DR2(port) MMIO32(port + 0x018) +#define ADC0_DR2 ADC_DR2(ADC0) +#define ADC1_DR2 ADC_DR2(ADC1) + +/* A/D Channel 3 Data Register */ +#define ADC_DR3(port) MMIO32(port + 0x01C) +#define ADC0_DR3 ADC_DR3(ADC0) +#define ADC1_DR3 ADC_DR3(ADC1) + +/* A/D Channel 4 Data Register */ +#define ADC_DR4(port) MMIO32(port + 0x020) +#define ADC0_DR4 ADC_DR4(ADC0) +#define ADC1_DR4 ADC_DR4(ADC1) + +/* A/D Channel 5 Data Register */ +#define ADC_DR5(port) MMIO32(port + 0x024) +#define ADC0_DR5 ADC_DR5(ADC0) +#define ADC1_DR5 ADC_DR5(ADC1) + +/* A/D Channel 6 Data Register */ +#define ADC_DR6(port) MMIO32(port + 0x028) +#define ADC0_DR6 ADC_DR6(ADC0) +#define ADC1_DR6 ADC_DR6(ADC1) + +/* A/D Channel 7 Data Register */ +#define ADC_DR7(port) MMIO32(port + 0x02C) +#define ADC0_DR7 ADC_DR7(ADC0) +#define ADC1_DR7 ADC_DR7(ADC1) + +/* A/D Status Register */ +#define ADC_STAT(port) MMIO32(port + 0x030) +#define ADC0_STAT ADC_STAT(ADC0) +#define ADC1_STAT ADC_STAT(ADC1) + +/**@}*/ + +#endif diff --git a/libopencm3/include/libopencm3/lpc43xx/atimer.h b/libopencm3/include/libopencm3/lpc43xx/atimer.h new file mode 100644 index 0000000..cbb70d7 --- /dev/null +++ b/libopencm3/include/libopencm3/lpc43xx/atimer.h @@ -0,0 +1,70 @@ +/** @defgroup atimer_defines Alarm Timer Defines + +@brief <b>Defined Constants and Types for the LPC43xx Alarm Timer</b> + +@ingroup LPC43xx_defines + +@version 1.0.0 + +@author @htmlonly © @endhtmlonly 2012 Michael Ossmann <mike@ossmann.com> + +@date 10 March 2013 + +LGPL License Terms @ref lgpl_license + */ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2012 Michael Ossmann <mike@ossmann.com> + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see <http://www.gnu.org/licenses/>. + */ + +#ifndef LPC43XX_ATIMER_H +#define LPC43XX_ATIMER_H + +/**@{*/ + +#include <libopencm3/cm3/common.h> +#include <libopencm3/lpc43xx/memorymap.h> + +/* --- Alarm Timer registers ----------------------------------------------- */ + +/* Downcounter register */ +#define ATIMER_DOWNCOUNTER MMIO32(ATIMER_BASE + 0x000) + +/* Preset value register */ +#define ATIMER_PRESET MMIO32(ATIMER_BASE + 0x004) + +/* Interrupt clear enable register */ +#define ATIMER_CLR_EN MMIO32(ATIMER_BASE + 0xFD8) + +/* Interrupt set enable register */ +#define ATIMER_SET_EN MMIO32(ATIMER_BASE + 0xFDC) + +/* Status register */ +#define ATIMER_STATUS MMIO32(ATIMER_BASE + 0xFE0) + +/* Enable register */ +#define ATIMER_ENABLE MMIO32(ATIMER_BASE + 0xFE4) + +/* Clear register */ +#define ATIMER_CLR_STAT MMIO32(ATIMER_BASE + 0xFE8) + +/* Set register */ +#define ATIMER_SET_STAT MMIO32(ATIMER_BASE + 0xFEC) + +/**@}*/ + +#endif diff --git a/libopencm3/include/libopencm3/lpc43xx/ccu.h b/libopencm3/include/libopencm3/lpc43xx/ccu.h new file mode 100644 index 0000000..d3b1d50 --- /dev/null +++ b/libopencm3/include/libopencm3/lpc43xx/ccu.h @@ -0,0 +1,402 @@ +/** @defgroup ccu_defines Clock Control Unit Defines + +@brief <b>Defined Constants and Types for the LPC43xx Clock Control Unit</b> + +@ingroup LPC43xx_defines + +@version 1.0.0 + +@author @htmlonly © @endhtmlonly 2012 Michael Ossmann <mike@ossmann.com> + +@date 10 March 2013 + +LGPL License Terms @ref lgpl_license + */ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2012 Michael Ossmann <mike@ossmann.com> + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see <http://www.gnu.org/licenses/>. + */ + +#ifndef LPC43XX_CCU_H +#define LPC43XX_CCU_H + +/**@{*/ + +#include <libopencm3/cm3/common.h> +#include <libopencm3/lpc43xx/memorymap.h> + +/* --- CCU1 registers ------------------------------------------------------ */ + +/* CCU1 power mode register */ +#define CCU1_PM MMIO32(CCU1_BASE + 0x000) + +/* CCU1 base clock status register */ +#define CCU1_BASE_STAT MMIO32(CCU1_BASE + 0x004) + +/* CLK_APB3_BUS clock configuration register */ +#define CCU1_CLK_APB3_BUS_CFG MMIO32(CCU1_BASE + 0x100) + +/* CLK_APB3_BUS clock status register */ +#define CCU1_CLK_APB3_BUS_STAT MMIO32(CCU1_BASE + 0x104) + +/* CLK_APB3_I2C1 configuration register */ +#define CCU1_CLK_APB3_I2C1_CFG MMIO32(CCU1_BASE + 0x108) + +/* CLK_APB3_I2C1 status register */ +#define CCU1_CLK_APB3_I2C1_STAT MMIO32(CCU1_BASE + 0x10C) + +/* CLK_APB3_DAC configuration register */ +#define CCU1_CLK_APB3_DAC_CFG MMIO32(CCU1_BASE + 0x110) + +/* CLK_APB3_DAC status register */ +#define CCU1_CLK_APB3_DAC_STAT MMIO32(CCU1_BASE + 0x114) + +/* CLK_APB3_ADC0 configuration register */ +#define CCU1_CLK_APB3_ADC0_CFG MMIO32(CCU1_BASE + 0x118) + +/* CLK_APB3_ADC0 status register */ +#define CCU1_CLK_APB3_ADC0_STAT MMIO32(CCU1_BASE + 0x11C) + +/* CLK_APB3_ADC1 configuration register */ +#define CCU1_CLK_APB3_ADC1_CFG MMIO32(CCU1_BASE + 0x120) + +/* CLK_APB3_ADC1 status register */ +#define CCU1_CLK_APB3_ADC1_STAT MMIO32(CCU1_BASE + 0x124) + +/* CLK_APB3_CAN0 configuration register */ +#define CCU1_CLK_APB3_CAN0_CFG MMIO32(CCU1_BASE + 0x128) + +/* CLK_APB3_CAN0 status register */ +#define CCU1_CLK_APB3_CAN0_STAT MMIO32(CCU1_BASE + 0x12C) + +/* CLK_APB1_BUS configuration register */ +#define CCU1_CLK_APB1_BUS_CFG MMIO32(CCU1_BASE + 0x200) + +/* CLK_APB1_BUS status register */ +#define CCU1_CLK_APB1_BUS_STAT MMIO32(CCU1_BASE + 0x204) + +/* CLK_APB1_MOTOCON configuration register */ +#define CCU1_CLK_APB1_MOTOCONPWM_CFG MMIO32(CCU1_BASE + 0x208) + +/* CLK_APB1_MOTOCON status register */ +#define CCU1_CLK_APB1_MOTOCONPWM_STAT MMIO32(CCU1_BASE + 0x20C) + +/* CLK_APB1_I2C0 configuration register */ +#define CCU1_CLK_APB1_I2C0_CFG MMIO32(CCU1_BASE + 0x210) + +/* CLK_APB1_I2C0 status register */ +#define CCU1_CLK_APB1_I2C0_STAT MMIO32(CCU1_BASE + 0x214) + +/* CLK_APB1_I2S configuration register */ +#define CCU1_CLK_APB1_I2S_CFG MMIO32(CCU1_BASE + 0x218) + +/* CLK_APB1_I2S status register */ +#define CCU1_CLK_APB1_I2S_STAT MMIO32(CCU1_BASE + 0x21C) + +/* CLK_APB3_CAN1 configuration register */ +#define CCU1_CLK_APB1_CAN1_CFG MMIO32(CCU1_BASE + 0x220) + +/* CLK_APB3_CAN1 status register */ +#define CCU1_CLK_APB1_CAN1_STAT MMIO32(CCU1_BASE + 0x224) + +/* CLK_SPIFI configuration register */ +#define CCU1_CLK_SPIFI_CFG MMIO32(CCU1_BASE + 0x300) + +/* CLK_SPIFI status register */ +#define CCU1_CLK_SPIFI_STAT MMIO32(CCU1_BASE + 0x304) + +/* CLK_M4_BUS configuration register */ +#define CCU1_CLK_M4_BUS_CFG MMIO32(CCU1_BASE + 0x400) + +/* CLK_M4_BUS status register */ +#define CCU1_CLK_M4_BUS_STAT MMIO32(CCU1_BASE + 0x404) + +/* CLK_M4_SPIFI configuration register */ +#define CCU1_CLK_M4_SPIFI_CFG MMIO32(CCU1_BASE + 0x408) + +/* CLK_M4_SPIFI status register */ +#define CCU1_CLK_M4_SPIFI_STAT MMIO32(CCU1_BASE + 0x40C) + +/* CLK_M4_GPIO configuration register */ +#define CCU1_CLK_M4_GPIO_CFG MMIO32(CCU1_BASE + 0x410) + +/* CLK_M4_GPIO status register */ +#define CCU1_CLK_M4_GPIO_STAT MMIO32(CCU1_BASE + 0x414) + +/* CLK_M4_LCD configuration register */ +#define CCU1_CLK_M4_LCD_CFG MMIO32(CCU1_BASE + 0x418) + +/* CLK_M4_LCD status register */ +#define CCU1_CLK_M4_LCD_STAT MMIO32(CCU1_BASE + 0x41C) + +/* CLK_M4_ETHERNET configuration register */ +#define CCU1_CLK_M4_ETHERNET_CFG MMIO32(CCU1_BASE + 0x420) + +/* CLK_M4_ETHERNET status register */ +#define CCU1_CLK_M4_ETHERNET_STAT MMIO32(CCU1_BASE + 0x424) + +/* CLK_M4_USB0 configuration register */ +#define CCU1_CLK_M4_USB0_CFG MMIO32(CCU1_BASE + 0x428) + +/* CLK_M4_USB0 status register */ +#define CCU1_CLK_M4_USB0_STAT MMIO32(CCU1_BASE + 0x42C) + +/* CLK_M4_EMC configuration register */ +#define CCU1_CLK_M4_EMC_CFG MMIO32(CCU1_BASE + 0x430) + +/* CLK_M4_EMC status register */ +#define CCU1_CLK_M4_EMC_STAT MMIO32(CCU1_BASE + 0x434) + +/* CLK_M4_SDIO configuration register */ +#define CCU1_CLK_M4_SDIO_CFG MMIO32(CCU1_BASE + 0x438) + +/* CLK_M4_SDIO status register */ +#define CCU1_CLK_M4_SDIO_STAT MMIO32(CCU1_BASE + 0x43C) + +/* CLK_M4_DMA configuration register */ +#define CCU1_CLK_M4_DMA_CFG MMIO32(CCU1_BASE + 0x440) + +/* CLK_M4_DMA status register */ +#define CCU1_CLK_M4_DMA_STAT MMIO32(CCU1_BASE + 0x444) + +/* CLK_M4_M4CORE configuration register */ +#define CCU1_CLK_M4_M4CORE_CFG MMIO32(CCU1_BASE + 0x448) + +/* CLK_M4_M4CORE status register */ +#define CCU1_CLK_M4_M4CORE_STAT MMIO32(CCU1_BASE + 0x44C) + +/* CLK_M4_SCT configuration register */ +#define CCU1_CLK_M4_SCT_CFG MMIO32(CCU1_BASE + 0x468) + +/* CLK_M4_SCT status register */ +#define CCU1_CLK_M4_SCT_STAT MMIO32(CCU1_BASE + 0x46C) + +/* CLK_M4_USB1 configuration register */ +#define CCU1_CLK_M4_USB1_CFG MMIO32(CCU1_BASE + 0x470) + +/* CLK_M4_USB1 status register */ +#define CCU1_CLK_M4_USB1_STAT MMIO32(CCU1_BASE + 0x474) + +/* CLK_M4_EMCDIV configuration register */ +#define CCU1_CLK_M4_EMCDIV_CFG MMIO32(CCU1_BASE + 0x478) + +/* CLK_M4_EMCDIV status register */ +#define CCU1_CLK_M4_EMCDIV_STAT MMIO32(CCU1_BASE + 0x47C) + +/* CLK_M4_M0_CFG configuration register */ +#define CCU1_CLK_M4_M0APP_CFG MMIO32(CCU1_BASE + 0x490) + +/* CLK_M4_M0_STAT status register */ +#define CCU1_CLK_M4_M0APP_STAT MMIO32(CCU1_BASE + 0x494) + +/* CLK_M4_VADC_CFG configuration register */ +#define CCU1_CLK_M4_VADC_CFG MMIO32(CCU1_BASE + 0x498) + +/* CLK_M4_VADC_STAT configuration register */ +#define CCU1_CLK_M4_VADC_STAT MMIO32(CCU1_BASE + 0x49C) + +/* CLK_M4_WWDT configuration register */ +#define CCU1_CLK_M4_WWDT_CFG MMIO32(CCU1_BASE + 0x500) + +/* CLK_M4_WWDT status register */ +#define CCU1_CLK_M4_WWDT_STAT MMIO32(CCU1_BASE + 0x504) + +/* CLK_M4_UART0 configuration register */ +#define CCU1_CLK_M4_USART0_CFG MMIO32(CCU1_BASE + 0x508) + +/* CLK_M4_UART0 status register */ +#define CCU1_CLK_M4_USART0_STAT MMIO32(CCU1_BASE + 0x50C) + +/* CLK_M4_UART1 configuration register */ +#define CCU1_CLK_M4_UART1_CFG MMIO32(CCU1_BASE + 0x510) + +/* CLK_M4_UART1 status register */ +#define CCU1_CLK_M4_UART1_STAT MMIO32(CCU1_BASE + 0x514) + +/* CLK_M4_SSP0 configuration register */ +#define CCU1_CLK_M4_SSP0_CFG MMIO32(CCU1_BASE + 0x518) + +/* CLK_M4_SSP0 status register */ +#define CCU1_CLK_M4_SSP0_STAT MMIO32(CCU1_BASE + 0x51C) + +/* CLK_M4_TIMER0 configuration register */ +#define CCU1_CLK_M4_TIMER0_CFG MMIO32(CCU1_BASE + 0x520) + +/* CLK_M4_TIMER0 status register */ +#define CCU1_CLK_M4_TIMER0_STAT MMIO32(CCU1_BASE + 0x524) + +/* CLK_M4_TIMER1 configuration register */ +#define CCU1_CLK_M4_TIMER1_CFG MMIO32(CCU1_BASE + 0x528) + +/* CLK_M4_TIMER1 status register */ +#define CCU1_CLK_M4_TIMER1_STAT MMIO32(CCU1_BASE + 0x52C) + +/* CLK_M4_SCU configuration register */ +#define CCU1_CLK_M4_SCU_CFG MMIO32(CCU1_BASE + 0x530) + +/* CLK_M4_SCU status register */ +#define CCU1_CLK_M4_SCU_STAT MMIO32(CCU1_BASE + 0x534) + +/* CLK_M4_CREG configuration register */ +#define CCU1_CLK_M4_CREG_CFG MMIO32(CCU1_BASE + 0x538) + +/* CLK_M4_CREG status register */ +#define CCU1_CLK_M4_CREG_STAT MMIO32(CCU1_BASE + 0x53C) + +/* CLK_M4_RITIMER configuration register */ +#define CCU1_CLK_M4_RITIMER_CFG MMIO32(CCU1_BASE + 0x600) + +/* CLK_M4_RITIMER status register */ +#define CCU1_CLK_M4_RITIMER_STAT MMIO32(CCU1_BASE + 0x604) + +/* CLK_M4_UART2 configuration register */ +#define CCU1_CLK_M4_USART2_CFG MMIO32(CCU1_BASE + 0x608) + +/* CLK_M4_UART2 status register */ +#define CCU1_CLK_M4_USART2_STAT MMIO32(CCU1_BASE + 0x60C) + +/* CLK_M4_UART3 configuration register */ +#define CCU1_CLK_M4_USART3_CFG MMIO32(CCU1_BASE + 0x610) + +/* CLK_M4_UART3 status register */ +#define CCU1_CLK_M4_USART3_STAT MMIO32(CCU1_BASE + 0x614) + +/* CLK_M4_TIMER2 configuration register */ +#define CCU1_CLK_M4_TIMER2_CFG MMIO32(CCU1_BASE + 0x618) + +/* CLK_M4_TIMER2 status register */ +#define CCU1_CLK_M4_TIMER2_STAT MMIO32(CCU1_BASE + 0x61C) + +/* CLK_M4_TIMER3 configuration register */ +#define CCU1_CLK_M4_TIMER3_CFG MMIO32(CCU1_BASE + 0x620) + +/* CLK_M4_TIMER3 status register */ +#define CCU1_CLK_M4_TIMER3_STAT MMIO32(CCU1_BASE + 0x624) + +/* CLK_M4_SSP1 configuration register */ +#define CCU1_CLK_M4_SSP1_CFG MMIO32(CCU1_BASE + 0x628) + +/* CLK_M4_SSP1 status register */ +#define CCU1_CLK_M4_SSP1_STAT MMIO32(CCU1_BASE + 0x62C) + +/* CLK_M4_QEI configuration register */ +#define CCU1_CLK_M4_QEI_CFG MMIO32(CCU1_BASE + 0x630) + +/* CLK_M4_QEI status register */ +#define CCU1_CLK_M4_QEI_STAT MMIO32(CCU1_BASE + 0x634) + +/* CLK_PERIPH_BUS configuration register */ +#define CCU1_CLK_PERIPH_BUS_CFG MMIO32(CCU1_BASE + 0x700) + +/* CLK_PERIPH_BUS status register */ +#define CCU1_CLK_PERIPH_BUS_STAT MMIO32(CCU1_BASE + 0x704) + +/* CLK_PERIPH_CORE configuration register */ +#define CCU1_CLK_PERIPH_CORE_CFG MMIO32(CCU1_BASE + 0x710) + +/* CLK_PERIPH_CORE status register */ +#define CCU1_CLK_PERIPH_CORE_STAT MMIO32(CCU1_BASE + 0x714) + +/* CLK_PERIPH_SGPIO configuration register */ +#define CCU1_CLK_PERIPH_SGPIO_CFG MMIO32(CCU1_BASE + 0x718) + +/* CLK_PERIPH_SGPIO status register */ +#define CCU1_CLK_PERIPH_SGPIO_STAT MMIO32(CCU1_BASE + 0x71C) + +/* CLK_USB0 configuration register */ +#define CCU1_CLK_USB0_CFG MMIO32(CCU1_BASE + 0x800) + +/* CLK_USB0 status register */ +#define CCU1_CLK_USB0_STAT MMIO32(CCU1_BASE + 0x804) + +/* CLK_USB1 configuration register */ +#define CCU1_CLK_USB1_CFG MMIO32(CCU1_BASE + 0x900) + +/* CLK_USB1 status register */ +#define CCU1_CLK_USB1_STAT MMIO32(CCU1_BASE + 0x904) + +/* CLK_SPI configuration register */ +#define CCU1_CLK_SPI_CFG MMIO32(CCU1_BASE + 0xA00) + +/* CLK_SPI status register */ +#define CCU1_CLK_SPI_STAT MMIO32(CCU1_BASE + 0xA04) + +/* CLK_VADC configuration register */ +#define CCU1_CLK_VADC_CFG MMIO32(CCU1_BASE + 0xB00) + +/* CLK_VADC status register */ +#define CCU1_CLK_VADC_STAT MMIO32(CCU1_BASE + 0xB04) + +/* --- CCU2 registers ------------------------------------------------------ */ + +/* CCU2 power mode register */ +#define CCU2_PM MMIO32(CCU2_BASE + 0x000) + +/* CCU2 base clocks status register */ +#define CCU2_BASE_STAT MMIO32(CCU2_BASE + 0x004) + +/* CLK_APLL configuration register */ +#define CCU2_CLK_APLL_CFG MMIO32(CCU2_BASE + 0x100) + +/* CLK_APLL status register */ +#define CCU2_CLK_APLL_STAT MMIO32(CCU2_BASE + 0x104) + +/* CLK_APB2_UART3 configuration register */ +#define CCU2_CLK_APB2_USART3_CFG MMIO32(CCU2_BASE + 0x200) + +/* CLK_APB2_UART3 status register */ +#define CCU2_CLK_APB2_USART3_STAT MMIO32(CCU2_BASE + 0x204) + +/* CLK_APB2_UART2 configuration register */ +#define CCU2_CLK_APB2_USART2_CFG MMIO32(CCU2_BASE + 0x300) + +/* CLK_APB2_UART2 status register */ +#define CCU2_CLK_APB2_USART2_STAT MMIO32(CCU2_BASE + 0x304) + +/* CLK_APB0_UART1 configuration register */ +#define CCU2_CLK_APB0_UART1_CFG MMIO32(CCU2_BASE + 0x400) + +/* CLK_APB0_UART1 status register */ +#define CCU2_CLK_APB0_UART1_STAT MMIO32(CCU2_BASE + 0x404) + +/* CLK_APB0_UART0 configuration register */ +#define CCU2_CLK_APB0_USART0_CFG MMIO32(CCU2_BASE + 0x500) + +/* CLK_APB0_UART0 status register */ +#define CCU2_CLK_APB0_USART0_STAT MMIO32(CCU2_BASE + 0x504) + +/* CLK_APB2_SSP1 configuration register */ +#define CCU2_CLK_APB2_SSP1_CFG MMIO32(CCU2_BASE + 0x600) + +/* CLK_APB2_SSP1 status register */ +#define CCU2_CLK_APB2_SSP1_STAT MMIO32(CCU2_BASE + 0x604) + +/* CLK_APB0_SSP0 configuration register */ +#define CCU2_CLK_APB0_SSP0_CFG MMIO32(CCU2_BASE + 0x700) + +/* CLK_APB0_SSP0 status register */ +#define CCU2_CLK_APB0_SSP0_STAT MMIO32(CCU2_BASE + 0x704) + +/* CLK_SDIO configuration register (for SD/MMC) */ +#define CCU2_CLK_SDIO_CFG MMIO32(CCU2_BASE + 0x800) + +/* CLK_SDIO status register (for SD/MMC) */ +#define CCU2_CLK_SDIO_STAT MMIO32(CCU2_BASE + 0x804) + +/**@}*/ + +#endif diff --git a/libopencm3/include/libopencm3/lpc43xx/cgu.h b/libopencm3/include/libopencm3/lpc43xx/cgu.h new file mode 100644 index 0000000..0a169fd --- /dev/null +++ b/libopencm3/include/libopencm3/lpc43xx/cgu.h @@ -0,0 +1,964 @@ +/** @defgroup cgu_defines Clock Generation Unit Defines + * + * @brief <b>Defined Constants and Types for the LPC43xx Clock Generation + * Unit</b> + * + * @ingroup LPC43xx_defines + * + * @version 1.0.0 + * + * @author @htmlonly © @endhtmlonly 2012 Michael Ossmann + * <mike@ossmann.com> + * + * @date 10 March 2013 + * + * LGPL License Terms @ref lgpl_license + */ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2012 Michael Ossmann <mike@ossmann.com> + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see <http://www.gnu.org/licenses/>. + */ + +#ifndef LPC43XX_CGU_H +#define CGU_LPC43XX_CGU_H + +/**@{*/ + +#include <libopencm3/cm3/common.h> +#include <libopencm3/lpc43xx/memorymap.h> + +/* --- CGU registers ------------------------------------------------------- */ + +/* Frequency monitor register */ +#define CGU_FREQ_MON MMIO32(CGU_BASE + 0x014) + +/* Crystal oscillator control register */ +#define CGU_XTAL_OSC_CTRL MMIO32(CGU_BASE + 0x018) + +/* PLL0USB status register */ +#define CGU_PLL0USB_STAT MMIO32(CGU_BASE + 0x01C) + +/* PLL0USB control register */ +#define CGU_PLL0USB_CTRL MMIO32(CGU_BASE + 0x020) + +/* PLL0USB M-divider register */ +#define CGU_PLL0USB_MDIV MMIO32(CGU_BASE + 0x024) + +/* PLL0USB N/P-divider register */ +#define CGU_PLL0USB_NP_DIV MMIO32(CGU_BASE + 0x028) + +/* PLL0AUDIO status register */ +#define CGU_PLL0AUDIO_STAT MMIO32(CGU_BASE + 0x02C) + +/* PLL0AUDIO control register */ +#define CGU_PLL0AUDIO_CTRL MMIO32(CGU_BASE + 0x030) + +/* PLL0AUDIO M-divider register */ +#define CGU_PLL0AUDIO_MDIV MMIO32(CGU_BASE + 0x034) + +/* PLL0AUDIO N/P-divider register */ +#define CGU_PLL0AUDIO_NP_DIV MMIO32(CGU_BASE + 0x038) + +/* PLL0AUDIO fractional divider register */ +#define CGU_PLLAUDIO_FRAC MMIO32(CGU_BASE + 0x03C) + +/* PLL1 status register */ +#define CGU_PLL1_STAT MMIO32(CGU_BASE + 0x040) + +/* PLL1 control register */ +#define CGU_PLL1_CTRL MMIO32(CGU_BASE + 0x044) + +/* Integer divider A control register */ +#define CGU_IDIVA_CTRL MMIO32(CGU_BASE + 0x048) + +/* Integer divider B control register */ +#define CGU_IDIVB_CTRL MMIO32(CGU_BASE + 0x04C) + +/* Integer divider C control register */ +#define CGU_IDIVC_CTRL MMIO32(CGU_BASE + 0x050) + +/* Integer divider D control register */ +#define CGU_IDIVD_CTRL MMIO32(CGU_BASE + 0x054) + +/* Integer divider E control register */ +#define CGU_IDIVE_CTRL MMIO32(CGU_BASE + 0x058) + +/* Output stage 0 control register */ +#define CGU_BASE_SAFE_CLK MMIO32(CGU_BASE + 0x05C) + +/* Output stage 1 control register for base clock */ +#define CGU_BASE_USB0_CLK MMIO32(CGU_BASE + 0x060) + +/* Output stage 2 control register for base clock */ +#define CGU_BASE_PERIPH_CLK MMIO32(CGU_BASE + 0x064) + +/* Output stage 3 control register for base clock */ +#define CGU_BASE_USB1_CLK MMIO32(CGU_BASE + 0x068) + +/* Output stage 4 control register for base clock */ +#define CGU_BASE_M4_CLK MMIO32(CGU_BASE + 0x06C) + +/* Output stage 5 control register for base clock */ +#define CGU_BASE_SPIFI_CLK MMIO32(CGU_BASE + 0x070) + +/* Output stage 6 control register for base clock */ +#define CGU_BASE_SPI_CLK MMIO32(CGU_BASE + 0x074) + +/* Output stage 7 control register for base clock */ +#define CGU_BASE_PHY_RX_CLK MMIO32(CGU_BASE + 0x078) + +/* Output stage 8 control register for base clock */ +#define CGU_BASE_PHY_TX_CLK MMIO32(CGU_BASE + 0x07C) + +/* Output stage 9 control register for base clock */ +#define CGU_BASE_APB1_CLK MMIO32(CGU_BASE + 0x080) + +/* Output stage 10 control register for base clock */ +#define CGU_BASE_APB3_CLK MMIO32(CGU_BASE + 0x084) + +/* Output stage 11 control register for base clock */ +#define CGU_BASE_LCD_CLK MMIO32(CGU_BASE + 0x088) + +/* Output stage 12 control register for base clock */ +#define CGU_BASE_VADC_CLK MMIO32(CGU_BASE + 0x08C) + +/* Output stage 13 control register for base clock */ +#define CGU_BASE_SDIO_CLK MMIO32(CGU_BASE + 0x090) + +/* Output stage 14 control register for base clock */ +#define CGU_BASE_SSP0_CLK MMIO32(CGU_BASE + 0x094) + +/* Output stage 15 control register for base clock */ +#define CGU_BASE_SSP1_CLK MMIO32(CGU_BASE + 0x098) + +/* Output stage 16 control register for base clock */ +#define CGU_BASE_UART0_CLK MMIO32(CGU_BASE + 0x09C) + +/* Output stage 17 control register for base clock */ +#define CGU_BASE_UART1_CLK MMIO32(CGU_BASE + 0x0A0) + +/* Output stage 18 control register for base clock */ +#define CGU_BASE_UART2_CLK MMIO32(CGU_BASE + 0x0A4) + +/* Output stage 19 control register for base clock */ +#define CGU_BASE_UART3_CLK MMIO32(CGU_BASE + 0x0A8) + +/* Output stage 20 control register for base clock */ +#define CGU_BASE_OUT_CLK MMIO32(CGU_BASE + 0x0AC) + +/* Reserved output stage */ +#define CGU_OUTCLK_21_CTRL MMIO32(CGU_BASE + 0x0B0) + +/* Reserved output stage */ +#define CGU_OUTCLK_22_CTRL MMIO32(CGU_BASE + 0x0B4) + +/* Reserved output stage */ +#define CGU_OUTCLK_23_CTRL MMIO32(CGU_BASE + 0x0B8) + +/* Reserved output stage */ +#define CGU_OUTCLK_24_CTRL MMIO32(CGU_BASE + 0x0BC) + +/* Output stage 25 control register for base clock */ +#define CGU_BASE_APLL_CLK MMIO32(CGU_BASE + 0x0C0) + +/* Output stage 26 control CLK register for base clock */ +#define CGU_BASE_CGU_OUT0_CLK MMIO32(CGU_BASE + 0x0C4) + +/* Output stage 27 control CLK register for base clock */ +#define CGU_BASE_CGU_OUT1_CLK MMIO32(CGU_BASE + 0x0C8) + +/* --- CGU_FREQ_MON values -------------------------------------- */ + +/* RCNT: 9-bit reference clock-counter value */ +#define CGU_FREQ_MON_RCNT_SHIFT (0) +#define CGU_FREQ_MON_RCNT_MASK (0x1ff << CGU_FREQ_MON_RCNT_SHIFT) +#define CGU_FREQ_MON_RCNT(x) ((x) << CGU_FREQ_MON_RCNT_SHIFT) + +/* FCNT: 14-bit selected clock-counter value */ +#define CGU_FREQ_MON_FCNT_SHIFT (9) +#define CGU_FREQ_MON_FCNT_MASK (0x3fff << CGU_FREQ_MON_FCNT_SHIFT) +#define CGU_FREQ_MON_FCNT(x) ((x) << CGU_FREQ_MON_FCNT_SHIFT) + +/* MEAS: Measure frequency */ +#define CGU_FREQ_MON_MEAS_SHIFT (23) +#define CGU_FREQ_MON_MEAS (1 << CGU_FREQ_MON_MEAS_SHIFT) + +/* CLK_SEL: Clock-source selection for the clock to be measured */ +#define CGU_FREQ_MON_CLK_SEL_SHIFT (24) +#define CGU_FREQ_MON_CLK_SEL_MASK (0x1f << CGU_FREQ_MON_CLK_SEL_SHIFT) +#define CGU_FREQ_MON_CLK_SEL(x) ((x) << CGU_FREQ_MON_CLK_SEL_SHIFT) + +/* --- CGU_XTAL_OSC_CTRL values --------------------------------- */ + +/* ENABLE: Oscillator-pad enable */ +#define CGU_XTAL_OSC_CTRL_ENABLE_SHIFT (0) +#define CGU_XTAL_OSC_CTRL_ENABLE (1 << CGU_XTAL_OSC_CTRL_ENABLE_SHIFT) + +/* BYPASS: Configure crystal operation or external-clock input pin XTAL1 */ +#define CGU_XTAL_OSC_CTRL_BYPASS_SHIFT (1) +#define CGU_XTAL_OSC_CTRL_BYPASS (1 << CGU_XTAL_OSC_CTRL_BYPASS_SHIFT) + +/* HF: Select frequency range */ +#define CGU_XTAL_OSC_CTRL_HF_SHIFT (2) +#define CGU_XTAL_OSC_CTRL_HF (1 << CGU_XTAL_OSC_CTRL_HF_SHIFT) + +/* --- CGU_PLL0USB_STAT values ---------------------------------- */ + +/* LOCK: PLL0 lock indicator */ +#define CGU_PLL0USB_STAT_LOCK_SHIFT (0) +#define CGU_PLL0USB_STAT_LOCK (1 << CGU_PLL0USB_STAT_LOCK_SHIFT) + +/* FR: PLL0 free running indicator */ +#define CGU_PLL0USB_STAT_FR_SHIFT (1) +#define CGU_PLL0USB_STAT_FR (1 << CGU_PLL0USB_STAT_FR_SHIFT) + +/* --- CGU_PLL0USB_CTRL values ---------------------------------- */ + +/* PD: PLL0 power down */ +#define CGU_PLL0USB_CTRL_PD_SHIFT (0) +#define CGU_PLL0USB_CTRL_PD (1 << CGU_PLL0USB_CTRL_PD_SHIFT) + +/* BYPASS: Input clock bypass control */ +#define CGU_PLL0USB_CTRL_BYPASS_SHIFT (1) +#define CGU_PLL0USB_CTRL_BYPASS (1 << CGU_PLL0USB_CTRL_BYPASS_SHIFT) + +/* DIRECTI: PLL0 direct input */ +#define CGU_PLL0USB_CTRL_DIRECTI_SHIFT (2) +#define CGU_PLL0USB_CTRL_DIRECTI (1 << CGU_PLL0USB_CTRL_DIRECTI_SHIFT) + +/* DIRECTO: PLL0 direct output */ +#define CGU_PLL0USB_CTRL_DIRECTO_SHIFT (3) +#define CGU_PLL0USB_CTRL_DIRECTO (1 << CGU_PLL0USB_CTRL_DIRECTO_SHIFT) + +/* CLKEN: PLL0 clock enable */ +#define CGU_PLL0USB_CTRL_CLKEN_SHIFT (4) +#define CGU_PLL0USB_CTRL_CLKEN (1 << CGU_PLL0USB_CTRL_CLKEN_SHIFT) + +/* FRM: Free running mode */ +#define CGU_PLL0USB_CTRL_FRM_SHIFT (6) +#define CGU_PLL0USB_CTRL_FRM (1 << CGU_PLL0USB_CTRL_FRM_SHIFT) + +/* AUTOBLOCK: Block clock automatically during frequency change */ +#define CGU_PLL0USB_CTRL_AUTOBLOCK_SHIFT (11) +#define CGU_PLL0USB_CTRL_AUTOBLOCK (1 << CGU_PLL0USB_CTRL_AUTOBLOCK_SHIFT) + +/* CLK_SEL: Clock source selection */ +#define CGU_PLL0USB_CTRL_CLK_SEL_SHIFT (24) +#define CGU_PLL0USB_CTRL_CLK_SEL_MASK (0x1f << CGU_PLL0USB_CTRL_CLK_SEL_SHIFT) +#define CGU_PLL0USB_CTRL_CLK_SEL(x) ((x) << CGU_PLL0USB_CTRL_CLK_SEL_SHIFT) + +/* --- CGU_PLL0USB_MDIV values ---------------------------------- */ + +/* MDEC: Decoded M-divider coefficient value */ +#define CGU_PLL0USB_MDIV_MDEC_SHIFT (0) +#define CGU_PLL0USB_MDIV_MDEC_MASK (0x1ffff << CGU_PLL0USB_MDIV_MDEC_SHIFT) +#define CGU_PLL0USB_MDIV_MDEC(x) ((x) << CGU_PLL0USB_MDIV_MDEC_SHIFT) + +/* SELP: Bandwidth select P value */ +#define CGU_PLL0USB_MDIV_SELP_SHIFT (17) +#define CGU_PLL0USB_MDIV_SELP_MASK (0x1f << CGU_PLL0USB_MDIV_SELP_SHIFT) +#define CGU_PLL0USB_MDIV_SELP(x) ((x) << CGU_PLL0USB_MDIV_SELP_SHIFT) + +/* SELI: Bandwidth select I value */ +#define CGU_PLL0USB_MDIV_SELI_SHIFT (22) +#define CGU_PLL0USB_MDIV_SELI_MASK (0x3f << CGU_PLL0USB_MDIV_SELI_SHIFT) +#define CGU_PLL0USB_MDIV_SELI(x) ((x) << CGU_PLL0USB_MDIV_SELI_SHIFT) + +/* SELR: Bandwidth select R value */ +#define CGU_PLL0USB_MDIV_SELR_SHIFT (28) +#define CGU_PLL0USB_MDIV_SELR_MASK (0xf << CGU_PLL0USB_MDIV_SELR_SHIFT) +#define CGU_PLL0USB_MDIV_SELR(x) ((x) << CGU_PLL0USB_MDIV_SELR_SHIFT) + +/* --- CGU_PLL0USB_NP_DIV values -------------------------------- */ + +/* PDEC: Decoded P-divider coefficient value */ +#define CGU_PLL0USB_NP_DIV_PDEC_SHIFT (0) +#define CGU_PLL0USB_NP_DIV_PDEC_MASK (0x7f << CGU_PLL0USB_NP_DIV_PDEC_SHIFT) +#define CGU_PLL0USB_NP_DIV_PDEC(x) ((x) << CGU_PLL0USB_NP_DIV_PDEC_SHIFT) + +/* NDEC: Decoded N-divider coefficient value */ +#define CGU_PLL0USB_NP_DIV_NDEC_SHIFT (12) +#define CGU_PLL0USB_NP_DIV_NDEC_MASK (0x3ff << CGU_PLL0USB_NP_DIV_NDEC_SHIFT) +#define CGU_PLL0USB_NP_DIV_NDEC(x) ((x) << CGU_PLL0USB_NP_DIV_NDEC_SHIFT) + +/* --- CGU_PLL0AUDIO_STAT values -------------------------------- */ + +/* LOCK: PLL0 lock indicator */ +#define CGU_PLL0AUDIO_STAT_LOCK_SHIFT (0) +#define CGU_PLL0AUDIO_STAT_LOCK (1 << CGU_PLL0AUDIO_STAT_LOCK_SHIFT) + +/* FR: PLL0 free running indicator */ +#define CGU_PLL0AUDIO_STAT_FR_SHIFT (1) +#define CGU_PLL0AUDIO_STAT_FR (1 << CGU_PLL0AUDIO_STAT_FR_SHIFT) + +/* --- CGU_PLL0AUDIO_CTRL values -------------------------------- */ + +/* PD: PLL0 power down */ +#define CGU_PLL0AUDIO_CTRL_PD_SHIFT (0) +#define CGU_PLL0AUDIO_CTRL_PD (1 << CGU_PLL0AUDIO_CTRL_PD_SHIFT) + +/* BYPASS: Input clock bypass control */ +#define CGU_PLL0AUDIO_CTRL_BYPASS_SHIFT (1) +#define CGU_PLL0AUDIO_CTRL_BYPASS (1 << CGU_PLL0AUDIO_CTRL_BYPASS_SHIFT) + +/* DIRECTI: PLL0 direct input */ +#define CGU_PLL0AUDIO_CTRL_DIRECTI_SHIFT (2) +#define CGU_PLL0AUDIO_CTRL_DIRECTI (1 << CGU_PLL0AUDIO_CTRL_DIRECTI_SHIFT) + +/* DIRECTO: PLL0 direct output */ +#define CGU_PLL0AUDIO_CTRL_DIRECTO_SHIFT (3) +#define CGU_PLL0AUDIO_CTRL_DIRECTO (1 << CGU_PLL0AUDIO_CTRL_DIRECTO_SHIFT) + +/* CLKEN: PLL0 clock enable */ +#define CGU_PLL0AUDIO_CTRL_CLKEN_SHIFT (4) +#define CGU_PLL0AUDIO_CTRL_CLKEN (1 << CGU_PLL0AUDIO_CTRL_CLKEN_SHIFT) + +/* FRM: Free running mode */ +#define CGU_PLL0AUDIO_CTRL_FRM_SHIFT (6) +#define CGU_PLL0AUDIO_CTRL_FRM (1 << CGU_PLL0AUDIO_CTRL_FRM_SHIFT) + +/* AUTOBLOCK: Block clock automatically during frequency change */ +#define CGU_PLL0AUDIO_CTRL_AUTOBLOCK_SHIFT (11) +#define CGU_PLL0AUDIO_CTRL_AUTOBLOCK \ + (1 << CGU_PLL0AUDIO_CTRL_AUTOBLOCK_SHIFT) + +/* PLLFRACT_REQ: Fractional PLL word write request */ +#define CGU_PLL0AUDIO_CTRL_PLLFRACT_REQ_SHIFT (12) +#define CGU_PLL0AUDIO_CTRL_PLLFRACT_REQ \ + (1 << CGU_PLL0AUDIO_CTRL_PLLFRACT_REQ_SHIFT) + +/* SEL_EXT: Select fractional divider */ +#define CGU_PLL0AUDIO_CTRL_SEL_EXT_SHIFT (13) +#define CGU_PLL0AUDIO_CTRL_SEL_EXT (1 << CGU_PLL0AUDIO_CTRL_SEL_EXT_SHIFT) + +/* MOD_PD: Sigma-Delta modulator power-down */ +#define CGU_PLL0AUDIO_CTRL_MOD_PD_SHIFT (14) +#define CGU_PLL0AUDIO_CTRL_MOD_PD (1 << CGU_PLL0AUDIO_CTRL_MOD_PD_SHIFT) + +/* CLK_SEL: Clock source selection */ +#define CGU_PLL0AUDIO_CTRL_CLK_SEL_SHIFT (24) +#define CGU_PLL0AUDIO_CTRL_CLK_SEL_MASK \ + (0x1f << CGU_PLL0AUDIO_CTRL_CLK_SEL_SHIFT) +#define CGU_PLL0AUDIO_CTRL_CLK_SEL(x) \ + ((x) << CGU_PLL0AUDIO_CTRL_CLK_SEL_SHIFT) + +/* --- CGU_PLL0AUDIO_MDIV values -------------------------------- */ + +/* MDEC: Decoded M-divider coefficient value */ +#define CGU_PLL0AUDIO_MDIV_MDEC_SHIFT (0) +#define CGU_PLL0AUDIO_MDIV_MDEC_MASK \ + (0x1ffff << CGU_PLL0AUDIO_MDIV_MDEC_SHIFT) +#define CGU_PLL0AUDIO_MDIV_MDEC(x) \ + ((x) << CGU_PLL0AUDIO_MDIV_MDEC_SHIFT) + +/* --- CGU_PLL0AUDIO_NP_DIV values ------------------------------ */ + +/* PDEC: Decoded P-divider coefficient value */ +#define CGU_PLL0AUDIO_NP_DIV_PDEC_SHIFT (0) +#define CGU_PLL0AUDIO_NP_DIV_PDEC_MASK \ + (0x7f << CGU_PLL0AUDIO_NP_DIV_PDEC_SHIFT) +#define CGU_PLL0AUDIO_NP_DIV_PDEC(x) \ + ((x) << CGU_PLL0AUDIO_NP_DIV_PDEC_SHIFT) + +/* NDEC: Decoded N-divider coefficient value */ +#define CGU_PLL0AUDIO_NP_DIV_NDEC_SHIFT (12) +#define CGU_PLL0AUDIO_NP_DIV_NDEC_MASK \ + (0x3ff << CGU_PLL0AUDIO_NP_DIV_NDEC_SHIFT) +#define CGU_PLL0AUDIO_NP_DIV_NDEC(x) \ + ((x) << CGU_PLL0AUDIO_NP_DIV_NDEC_SHIFT) + +/* --- CGU_PLLAUDIO_FRAC values --------------------------------- */ + +/* PLLFRACT_CTRL: PLL fractional divider control word */ +#define CGU_PLLAUDIO_FRAC_PLLFRACT_CTRL_SHIFT (0) +#define CGU_PLLAUDIO_FRAC_PLLFRACT_CTRL_MASK \ + (0x3fffff << CGU_PLLAUDIO_FRAC_PLLFRACT_CTRL_SHIFT) +#define CGU_PLLAUDIO_FRAC_PLLFRACT_CTRL(x) \ + ((x) << CGU_PLLAUDIO_FRAC_PLLFRACT_CTRL_SHIFT) + +/* --- CGU_PLL1_STAT values ------------------------------------- */ + +/* LOCK: PLL1 lock indicator */ +#define CGU_PLL1_STAT_LOCK_SHIFT (0) +#define CGU_PLL1_STAT_LOCK (1 << CGU_PLL1_STAT_LOCK_SHIFT) + +/* --- CGU_PLL1_CTRL values ------------------------------------- */ + +/* PD: PLL1 power down */ +#define CGU_PLL1_CTRL_PD_SHIFT (0) +#define CGU_PLL1_CTRL_PD (1 << CGU_PLL1_CTRL_PD_SHIFT) + +/* BYPASS: Input clock bypass control */ +#define CGU_PLL1_CTRL_BYPASS_SHIFT (1) +#define CGU_PLL1_CTRL_BYPASS (1 << CGU_PLL1_CTRL_BYPASS_SHIFT) + +/* FBSEL: PLL feedback select */ +#define CGU_PLL1_CTRL_FBSEL_SHIFT (6) +#define CGU_PLL1_CTRL_FBSEL (1 << CGU_PLL1_CTRL_FBSEL_SHIFT) + +/* DIRECT: PLL direct CCO output */ +#define CGU_PLL1_CTRL_DIRECT_SHIFT (7) +#define CGU_PLL1_CTRL_DIRECT (1 << CGU_PLL1_CTRL_DIRECT_SHIFT) + +/* PSEL: Post-divider division ratio P */ +#define CGU_PLL1_CTRL_PSEL_SHIFT (8) +#define CGU_PLL1_CTRL_PSEL_MASK (0x3 << CGU_PLL1_CTRL_PSEL_SHIFT) +#define CGU_PLL1_CTRL_PSEL(x) ((x) << CGU_PLL1_CTRL_PSEL_SHIFT) + +/* AUTOBLOCK: Block clock automatically during frequency change */ +#define CGU_PLL1_CTRL_AUTOBLOCK_SHIFT (11) +#define CGU_PLL1_CTRL_AUTOBLOCK (1 << CGU_PLL1_CTRL_AUTOBLOCK_SHIFT) + +/* NSEL: Pre-divider division ratio N */ +#define CGU_PLL1_CTRL_NSEL_SHIFT (12) +#define CGU_PLL1_CTRL_NSEL_MASK (0x3 << CGU_PLL1_CTRL_NSEL_SHIFT) +#define CGU_PLL1_CTRL_NSEL(x) ((x) << CGU_PLL1_CTRL_NSEL_SHIFT) + +/* MSEL: Feedback-divider division ratio (M) */ +#define CGU_PLL1_CTRL_MSEL_SHIFT (16) +#define CGU_PLL1_CTRL_MSEL_MASK (0xff << CGU_PLL1_CTRL_MSEL_SHIFT) +#define CGU_PLL1_CTRL_MSEL(x) ((x) << CGU_PLL1_CTRL_MSEL_SHIFT) + +/* CLK_SEL: Clock-source selection */ +#define CGU_PLL1_CTRL_CLK_SEL_SHIFT (24) +#define CGU_PLL1_CTRL_CLK_SEL_MASK (0x1f << CGU_PLL1_CTRL_CLK_SEL_SHIFT) +#define CGU_PLL1_CTRL_CLK_SEL(x) ((x) << CGU_PLL1_CTRL_CLK_SEL_SHIFT) + +/* --- CGU_IDIVA_CTRL values ------------------------------------ */ + +/* PD: Integer divider power down */ +#define CGU_IDIVA_CTRL_PD_SHIFT (0) +#define CGU_IDIVA_CTRL_PD (1 << CGU_IDIVA_CTRL_PD_SHIFT) + +/* IDIV: Integer divider A divider value (1/(IDIV + 1)) */ +#define CGU_IDIVA_CTRL_IDIV_SHIFT (2) +#define CGU_IDIVA_CTRL_IDIV_MASK (0x3 << CGU_IDIVA_CTRL_IDIV_SHIFT) +#define CGU_IDIVA_CTRL_IDIV(x) ((x) << CGU_IDIVA_CTRL_IDIV_SHIFT) + +/* AUTOBLOCK: Block clock automatically during frequency change */ +#define CGU_IDIVA_CTRL_AUTOBLOCK_SHIFT (11) +#define CGU_IDIVA_CTRL_AUTOBLOCK (1 << CGU_IDIVA_CTRL_AUTOBLOCK_SHIFT) + +/* CLK_SEL: Clock source selection */ +#define CGU_IDIVA_CTRL_CLK_SEL_SHIFT (24) +#define CGU_IDIVA_CTRL_CLK_SEL_MASK (0x1f << CGU_IDIVA_CTRL_CLK_SEL_SHIFT) +#define CGU_IDIVA_CTRL_CLK_SEL(x) ((x) << CGU_IDIVA_CTRL_CLK_SEL_SHIFT) + +/* --- CGU_IDIVB_CTRL values ------------------------------------ */ + +/* PD: Integer divider power down */ +#define CGU_IDIVB_CTRL_PD_SHIFT (0) +#define CGU_IDIVB_CTRL_PD (1 << CGU_IDIVB_CTRL_PD_SHIFT) + +/* IDIV: Integer divider B divider value (1/(IDIV + 1)) */ +#define CGU_IDIVB_CTRL_IDIV_SHIFT (2) +#define CGU_IDIVB_CTRL_IDIV_MASK (0xf << CGU_IDIVB_CTRL_IDIV_SHIFT) +#define CGU_IDIVB_CTRL_IDIV(x) ((x) << CGU_IDIVB_CTRL_IDIV_SHIFT) + +/* AUTOBLOCK: Block clock automatically during frequency change */ +#define CGU_IDIVB_CTRL_AUTOBLOCK_SHIFT (11) +#define CGU_IDIVB_CTRL_AUTOBLOCK (1 << CGU_IDIVB_CTRL_AUTOBLOCK_SHIFT) + +/* CLK_SEL: Clock source selection */ +#define CGU_IDIVB_CTRL_CLK_SEL_SHIFT (24) +#define CGU_IDIVB_CTRL_CLK_SEL_MASK (0x1f << CGU_IDIVB_CTRL_CLK_SEL_SHIFT) +#define CGU_IDIVB_CTRL_CLK_SEL(x) ((x) << CGU_IDIVB_CTRL_CLK_SEL_SHIFT) + +/* --- CGU_IDIVC_CTRL values ------------------------------------ */ + +/* PD: Integer divider power down */ +#define CGU_IDIVC_CTRL_PD_SHIFT (0) +#define CGU_IDIVC_CTRL_PD (1 << CGU_IDIVC_CTRL_PD_SHIFT) + +/* IDIV: Integer divider C divider value (1/(IDIV + 1)) */ +#define CGU_IDIVC_CTRL_IDIV_SHIFT (2) +#define CGU_IDIVC_CTRL_IDIV_MASK (0xf << CGU_IDIVC_CTRL_IDIV_SHIFT) +#define CGU_IDIVC_CTRL_IDIV(x) ((x) << CGU_IDIVC_CTRL_IDIV_SHIFT) + +/* AUTOBLOCK: Block clock automatically during frequency change */ +#define CGU_IDIVC_CTRL_AUTOBLOCK_SHIFT (11) +#define CGU_IDIVC_CTRL_AUTOBLOCK (1 << CGU_IDIVC_CTRL_AUTOBLOCK_SHIFT) + +/* CLK_SEL: Clock source selection */ +#define CGU_IDIVC_CTRL_CLK_SEL_SHIFT (24) +#define CGU_IDIVC_CTRL_CLK_SEL_MASK (0x1f << CGU_IDIVC_CTRL_CLK_SEL_SHIFT) +#define CGU_IDIVC_CTRL_CLK_SEL(x) ((x) << CGU_IDIVC_CTRL_CLK_SEL_SHIFT) + +/* --- CGU_IDIVD_CTRL values ------------------------------------ */ + +/* PD: Integer divider power down */ +#define CGU_IDIVD_CTRL_PD_SHIFT (0) +#define CGU_IDIVD_CTRL_PD (1 << CGU_IDIVD_CTRL_PD_SHIFT) + +/* IDIV: Integer divider D divider value (1/(IDIV + 1)) */ +#define CGU_IDIVD_CTRL_IDIV_SHIFT (2) +#define CGU_IDIVD_CTRL_IDIV_MASK (0xf << CGU_IDIVD_CTRL_IDIV_SHIFT) +#define CGU_IDIVD_CTRL_IDIV(x) ((x) << CGU_IDIVD_CTRL_IDIV_SHIFT) + +/* AUTOBLOCK: Block clock automatically during frequency change */ +#define CGU_IDIVD_CTRL_AUTOBLOCK_SHIFT (11) +#define CGU_IDIVD_CTRL_AUTOBLOCK (1 << CGU_IDIVD_CTRL_AUTOBLOCK_SHIFT) + +/* CLK_SEL: Clock source selection */ +#define CGU_IDIVD_CTRL_CLK_SEL_SHIFT (24) +#define CGU_IDIVD_CTRL_CLK_SEL_MASK (0x1f << CGU_IDIVD_CTRL_CLK_SEL_SHIFT) +#define CGU_IDIVD_CTRL_CLK_SEL(x) ((x) << CGU_IDIVD_CTRL_CLK_SEL_SHIFT) + +/* --- CGU_IDIVE_CTRL values ------------------------------------ */ + +/* PD: Integer divider power down */ +#define CGU_IDIVE_CTRL_PD_SHIFT (0) +#define CGU_IDIVE_CTRL_PD (1 << CGU_IDIVE_CTRL_PD_SHIFT) + +/* IDIV: Integer divider E divider value (1/(IDIV + 1)) */ +#define CGU_IDIVE_CTRL_IDIV_SHIFT (2) +#define CGU_IDIVE_CTRL_IDIV_MASK (0xff << CGU_IDIVE_CTRL_IDIV_SHIFT) +#define CGU_IDIVE_CTRL_IDIV(x) ((x) << CGU_IDIVE_CTRL_IDIV_SHIFT) + +/* AUTOBLOCK: Block clock automatically during frequency change */ +#define CGU_IDIVE_CTRL_AUTOBLOCK_SHIFT (11) +#define CGU_IDIVE_CTRL_AUTOBLOCK (1 << CGU_IDIVE_CTRL_AUTOBLOCK_SHIFT) + +/* CLK_SEL: Clock source selection */ +#define CGU_IDIVE_CTRL_CLK_SEL_SHIFT (24) +#define CGU_IDIVE_CTRL_CLK_SEL_MASK (0x1f << CGU_IDIVE_CTRL_CLK_SEL_SHIFT) +#define CGU_IDIVE_CTRL_CLK_SEL(x) ((x) << CGU_IDIVE_CTRL_CLK_SEL_SHIFT) + +/* --- CGU_BASE_SAFE_CLK values --------------------------------- */ + +/* PD: Output stage power down */ +#define CGU_BASE_SAFE_CLK_PD_SHIFT (0) +#define CGU_BASE_SAFE_CLK_PD (1 << CGU_BASE_SAFE_CLK_PD_SHIFT) + +/* AUTOBLOCK: Block clock automatically during frequency change */ +#define CGU_BASE_SAFE_CLK_AUTOBLOCK_SHIFT (11) +#define CGU_BASE_SAFE_CLK_AUTOBLOCK (1 << CGU_BASE_SAFE_CLK_AUTOBLOCK_SHIFT) + +/* CLK_SEL: Clock source selection */ +#define CGU_BASE_SAFE_CLK_CLK_SEL_SHIFT (24) +#define CGU_BASE_SAFE_CLK_CLK_SEL_MASK \ + (0x1f << CGU_BASE_SAFE_CLK_CLK_SEL_SHIFT) +#define CGU_BASE_SAFE_CLK_CLK_SEL(x) \ + ((x) << CGU_BASE_SAFE_CLK_CLK_SEL_SHIFT) + +/* --- CGU_BASE_USB0_CLK values --------------------------------- */ + +/* PD: Output stage power down */ +#define CGU_BASE_USB0_CLK_PD_SHIFT (0) +#define CGU_BASE_USB0_CLK_PD (1 << CGU_BASE_USB0_CLK_PD_SHIFT) + +/* AUTOBLOCK: Block clock automatically during frequency change */ +#define CGU_BASE_USB0_CLK_AUTOBLOCK_SHIFT (11) +#define CGU_BASE_USB0_CLK_AUTOBLOCK (1 << CGU_BASE_USB0_CLK_AUTOBLOCK_SHIFT) + +/* CLK_SEL: Clock source selection */ +#define CGU_BASE_USB0_CLK_CLK_SEL_SHIFT (24) +#define CGU_BASE_USB0_CLK_CLK_SEL_MASK \ + (0x1f << CGU_BASE_USB0_CLK_CLK_SEL_SHIFT) +#define CGU_BASE_USB0_CLK_CLK_SEL(x) \ + ((x) << CGU_BASE_USB0_CLK_CLK_SEL_SHIFT) + +/* --- CGU_BASE_PERIPH_CLK values ------------------------------- */ + +/* PD: Output stage power down */ +#define CGU_BASE_PERIPH_CLK_PD_SHIFT (0) +#define CGU_BASE_PERIPH_CLK_PD (1 << CGU_BASE_PERIPH_CLK_PD_SHIFT) + +/* AUTOBLOCK: Block clock automatically during frequency change */ +#define CGU_BASE_PERIPH_CLK_AUTOBLOCK_SHIFT (11) +#define CGU_BASE_PERIPH_CLK_AUTOBLOCK \ + (1 << CGU_BASE_PERIPH_CLK_AUTOBLOCK_SHIFT) + +/* CLK_SEL: Clock source selection */ +#define CGU_BASE_PERIPH_CLK_CLK_SEL_SHIFT (24) +#define CGU_BASE_PERIPH_CLK_CLK_SEL_MASK \ + (0x1f << CGU_BASE_PERIPH_CLK_CLK_SEL_SHIFT) +#define CGU_BASE_PERIPH_CLK_CLK_SEL(x) \ + ((x) << CGU_BASE_PERIPH_CLK_CLK_SEL_SHIFT) + +/* --- CGU_BASE_USB1_CLK values --------------------------------- */ + +/* PD: Output stage power down */ +#define CGU_BASE_USB1_CLK_PD_SHIFT (0) +#define CGU_BASE_USB1_CLK_PD (1 << CGU_BASE_USB1_CLK_PD_SHIFT) + +/* AUTOBLOCK: Block clock automatically during frequency change */ +#define CGU_BASE_USB1_CLK_AUTOBLOCK_SHIFT (11) +#define CGU_BASE_USB1_CLK_AUTOBLOCK (1 << CGU_BASE_USB1_CLK_AUTOBLOCK_SHIFT) + +/* CLK_SEL: Clock source selection */ +#define CGU_BASE_USB1_CLK_CLK_SEL_SHIFT (24) +#define CGU_BASE_USB1_CLK_CLK_SEL_MASK \ + (0x1f << CGU_BASE_USB1_CLK_CLK_SEL_SHIFT) +#define CGU_BASE_USB1_CLK_CLK_SEL(x) \ + ((x) << CGU_BASE_USB1_CLK_CLK_SEL_SHIFT) + +/* --- CGU_BASE_M4_CLK values ----------------------------------- */ + +/* PD: Output stage power down */ +#define CGU_BASE_M4_CLK_PD_SHIFT (0) +#define CGU_BASE_M4_CLK_PD (1 << CGU_BASE_M4_CLK_PD_SHIFT) + +/* AUTOBLOCK: Block clock automatically during frequency change */ +#define CGU_BASE_M4_CLK_AUTOBLOCK_SHIFT (11) +#define CGU_BASE_M4_CLK_AUTOBLOCK (1 << CGU_BASE_M4_CLK_AUTOBLOCK_SHIFT) + +/* CLK_SEL: Clock source selection */ +#define CGU_BASE_M4_CLK_CLK_SEL_SHIFT (24) +#define CGU_BASE_M4_CLK_CLK_SEL_MASK (0x1f << CGU_BASE_M4_CLK_CLK_SEL_SHIFT) +#define CGU_BASE_M4_CLK_CLK_SEL(x) ((x) << CGU_BASE_M4_CLK_CLK_SEL_SHIFT) + +/* --- CGU_BASE_SPIFI_CLK values -------------------------------- */ + +/* PD: Output stage power down */ +#define CGU_BASE_SPIFI_CLK_PD_SHIFT (0) +#define CGU_BASE_SPIFI_CLK_PD (1 << CGU_BASE_SPIFI_CLK_PD_SHIFT) + +/* AUTOBLOCK: Block clock automatically during frequency change */ +#define CGU_BASE_SPIFI_CLK_AUTOBLOCK_SHIFT (11) +#define CGU_BASE_SPIFI_CLK_AUTOBLOCK \ + (1 << CGU_BASE_SPIFI_CLK_AUTOBLOCK_SHIFT) + +/* CLK_SEL: Clock source selection */ +#define CGU_BASE_SPIFI_CLK_CLK_SEL_SHIFT (24) +#define CGU_BASE_SPIFI_CLK_CLK_SEL_MASK \ + (0x1f << CGU_BASE_SPIFI_CLK_CLK_SEL_SHIFT) +#define CGU_BASE_SPIFI_CLK_CLK_SEL(x) \ + ((x) << CGU_BASE_SPIFI_CLK_CLK_SEL_SHIFT) + +/* --- CGU_BASE_SPI_CLK values ---------------------------------- */ + +/* PD: Output stage power down */ +#define CGU_BASE_SPI_CLK_PD_SHIFT (0) +#define CGU_BASE_SPI_CLK_PD (1 << CGU_BASE_SPI_CLK_PD_SHIFT) + +/* AUTOBLOCK: Block clock automatically during frequency change */ +#define CGU_BASE_SPI_CLK_AUTOBLOCK_SHIFT (11) +#define CGU_BASE_SPI_CLK_AUTOBLOCK (1 << CGU_BASE_SPI_CLK_AUTOBLOCK_SHIFT) + +/* CLK_SEL: Clock source selection */ +#define CGU_BASE_SPI_CLK_CLK_SEL_SHIFT (24) +#define CGU_BASE_SPI_CLK_CLK_SEL_MASK (0x1f << CGU_BASE_SPI_CLK_CLK_SEL_SHIFT) +#define CGU_BASE_SPI_CLK_CLK_SEL(x) ((x) << CGU_BASE_SPI_CLK_CLK_SEL_SHIFT) + +/* --- CGU_BASE_PHY_RX_CLK values ------------------------------- */ + +/* PD: Output stage power down */ +#define CGU_BASE_PHY_RX_CLK_PD_SHIFT (0) +#define CGU_BASE_PHY_RX_CLK_PD (1 << CGU_BASE_PHY_RX_CLK_PD_SHIFT) + +/* AUTOBLOCK: Block clock automatically during frequency change */ +#define CGU_BASE_PHY_RX_CLK_AUTOBLOCK_SHIFT (11) +#define CGU_BASE_PHY_RX_CLK_AUTOBLOCK \ + (1 << CGU_BASE_PHY_RX_CLK_AUTOBLOCK_SHIFT) + +/* CLK_SEL: Clock source selection */ +#define CGU_BASE_PHY_RX_CLK_CLK_SEL_SHIFT (24) +#define CGU_BASE_PHY_RX_CLK_CLK_SEL_MASK \ + (0x1f << CGU_BASE_PHY_RX_CLK_CLK_SEL_SHIFT) +#define CGU_BASE_PHY_RX_CLK_CLK_SEL(x) \ + ((x) << CGU_BASE_PHY_RX_CLK_CLK_SEL_SHIFT) + +/* --- CGU_BASE_PHY_TX_CLK values ------------------------------- */ + +/* PD: Output stage power down */ +#define CGU_BASE_PHY_TX_CLK_PD_SHIFT (0) +#define CGU_BASE_PHY_TX_CLK_PD (1 << CGU_BASE_PHY_TX_CLK_PD_SHIFT) + +/* AUTOBLOCK: Block clock automatically during frequency change */ +#define CGU_BASE_PHY_TX_CLK_AUTOBLOCK_SHIFT (11) +#define CGU_BASE_PHY_TX_CLK_AUTOBLOCK \ + (1 << CGU_BASE_PHY_TX_CLK_AUTOBLOCK_SHIFT) + +/* CLK_SEL: Clock source selection */ +#define CGU_BASE_PHY_TX_CLK_CLK_SEL_SHIFT (24) +#define CGU_BASE_PHY_TX_CLK_CLK_SEL_MASK \ + (0x1f << CGU_BASE_PHY_TX_CLK_CLK_SEL_SHIFT) +#define CGU_BASE_PHY_TX_CLK_CLK_SEL(x) \ + ((x) << CGU_BASE_PHY_TX_CLK_CLK_SEL_SHIFT) + +/* --- CGU_BASE_APB1_CLK values --------------------------------- */ + +/* PD: Output stage power down */ +#define CGU_BASE_APB1_CLK_PD_SHIFT (0) +#define CGU_BASE_APB1_CLK_PD (1 << CGU_BASE_APB1_CLK_PD_SHIFT) + +/* AUTOBLOCK: Block clock automatically during frequency change */ +#define CGU_BASE_APB1_CLK_AUTOBLOCK_SHIFT (11) +#define CGU_BASE_APB1_CLK_AUTOBLOCK (1 << CGU_BASE_APB1_CLK_AUTOBLOCK_SHIFT) + +/* CLK_SEL: Clock source selection */ +#define CGU_BASE_APB1_CLK_CLK_SEL_SHIFT (24) +#define CGU_BASE_APB1_CLK_CLK_SEL_MASK \ + (0x1f << CGU_BASE_APB1_CLK_CLK_SEL_SHIFT) +#define CGU_BASE_APB1_CLK_CLK_SEL(x) ((x) << CGU_BASE_APB1_CLK_CLK_SEL_SHIFT) + +/* --- CGU_BASE_APB3_CLK values --------------------------------- */ + +/* PD: Output stage power down */ +#define CGU_BASE_APB3_CLK_PD_SHIFT (0) +#define CGU_BASE_APB3_CLK_PD (1 << CGU_BASE_APB3_CLK_PD_SHIFT) + +/* AUTOBLOCK: Block clock automatically during frequency change */ +#define CGU_BASE_APB3_CLK_AUTOBLOCK_SHIFT (11) +#define CGU_BASE_APB3_CLK_AUTOBLOCK (1 << CGU_BASE_APB3_CLK_AUTOBLOCK_SHIFT) + +/* CLK_SEL: Clock source selection */ +#define CGU_BASE_APB3_CLK_CLK_SEL_SHIFT (24) +#define CGU_BASE_APB3_CLK_CLK_SEL_MASK \ + (0x1f << CGU_BASE_APB3_CLK_CLK_SEL_SHIFT) +#define CGU_BASE_APB3_CLK_CLK_SEL(x) ((x) << CGU_BASE_APB3_CLK_CLK_SEL_SHIFT) + +/* --- CGU_BASE_LCD_CLK values ---------------------------------- */ + +/* PD: Output stage power down */ +#define CGU_BASE_LCD_CLK_PD_SHIFT (0) +#define CGU_BASE_LCD_CLK_PD (1 << CGU_BASE_LCD_CLK_PD_SHIFT) + +/* AUTOBLOCK: Block clock automatically during frequency change */ +#define CGU_BASE_LCD_CLK_AUTOBLOCK_SHIFT (11) +#define CGU_BASE_LCD_CLK_AUTOBLOCK (1 << CGU_BASE_LCD_CLK_AUTOBLOCK_SHIFT) + +/* CLK_SEL: Clock source selection */ +#define CGU_BASE_LCD_CLK_CLK_SEL_SHIFT (24) +#define CGU_BASE_LCD_CLK_CLK_SEL_MASK (0x1f << CGU_BASE_LCD_CLK_CLK_SEL_SHIFT) +#define CGU_BASE_LCD_CLK_CLK_SEL(x) ((x) << CGU_BASE_LCD_CLK_CLK_SEL_SHIFT) + +/* --- CGU_BASE_VADC_CLK values --------------------------------- */ + +/* PD: Output stage power down */ +#define CGU_BASE_VADC_CLK_PD_SHIFT (0) +#define CGU_BASE_VADC_CLK_PD (1 << CGU_BASE_VADC_CLK_PD_SHIFT) + +/* AUTOBLOCK: Block clock automatically during frequency change */ +#define CGU_BASE_VADC_CLK_AUTOBLOCK_SHIFT (11) +#define CGU_BASE_VADC_CLK_AUTOBLOCK (1 << CGU_BASE_VADC_CLK_AUTOBLOCK_SHIFT) + +/* CLK_SEL: Clock source selection */ +#define CGU_BASE_VADC_CLK_CLK_SEL_SHIFT (24) +#define CGU_BASE_VADC_CLK_CLK_SEL_MASK \ + (0x1f << CGU_BASE_VADC_CLK_CLK_SEL_SHIFT) +#define CGU_BASE_VADC_CLK_CLK_SEL(x) ((x) << CGU_BASE_VADC_CLK_CLK_SEL_SHIFT) + +/* --- CGU_BASE_SDIO_CLK values --------------------------------- */ + +/* PD: Output stage power down */ +#define CGU_BASE_SDIO_CLK_PD_SHIFT (0) +#define CGU_BASE_SDIO_CLK_PD (1 << CGU_BASE_SDIO_CLK_PD_SHIFT) + +/* AUTOBLOCK: Block clock automatically during frequency change */ +#define CGU_BASE_SDIO_CLK_AUTOBLOCK_SHIFT (11) +#define CGU_BASE_SDIO_CLK_AUTOBLOCK (1 << CGU_BASE_SDIO_CLK_AUTOBLOCK_SHIFT) + +/* CLK_SEL: Clock source selection */ +#define CGU_BASE_SDIO_CLK_CLK_SEL_SHIFT (24) +#define CGU_BASE_SDIO_CLK_CLK_SEL_MASK \ + (0x1f << CGU_BASE_SDIO_CLK_CLK_SEL_SHIFT) +#define CGU_BASE_SDIO_CLK_CLK_SEL(x) ((x) << CGU_BASE_SDIO_CLK_CLK_SEL_SHIFT) + +/* --- CGU_BASE_SSP0_CLK values --------------------------------- */ + +/* PD: Output stage power down */ +#define CGU_BASE_SSP0_CLK_PD_SHIFT (0) +#define CGU_BASE_SSP0_CLK_PD (1 << CGU_BASE_SSP0_CLK_PD_SHIFT) + +/* AUTOBLOCK: Block clock automatically during frequency change */ +#define CGU_BASE_SSP0_CLK_AUTOBLOCK_SHIFT (11) +#define CGU_BASE_SSP0_CLK_AUTOBLOCK (1 << CGU_BASE_SSP0_CLK_AUTOBLOCK_SHIFT) + +/* CLK_SEL: Clock source selection */ +#define CGU_BASE_SSP0_CLK_CLK_SEL_SHIFT (24) +#define CGU_BASE_SSP0_CLK_CLK_SEL_MASK \ + (0x1f << CGU_BASE_SSP0_CLK_CLK_SEL_SHIFT) +#define CGU_BASE_SSP0_CLK_CLK_SEL(x) ((x) << CGU_BASE_SSP0_CLK_CLK_SEL_SHIFT) + +/* --- CGU_BASE_SSP1_CLK values --------------------------------- */ + +/* PD: Output stage power down */ +#define CGU_BASE_SSP1_CLK_PD_SHIFT (0) +#define CGU_BASE_SSP1_CLK_PD (1 << CGU_BASE_SSP1_CLK_PD_SHIFT) + +/* AUTOBLOCK: Block clock automatically during frequency change */ +#define CGU_BASE_SSP1_CLK_AUTOBLOCK_SHIFT (11) +#define CGU_BASE_SSP1_CLK_AUTOBLOCK (1 << CGU_BASE_SSP1_CLK_AUTOBLOCK_SHIFT) + +/* CLK_SEL: Clock source selection */ +#define CGU_BASE_SSP1_CLK_CLK_SEL_SHIFT (24) +#define CGU_BASE_SSP1_CLK_CLK_SEL_MASK \ + (0x1f << CGU_BASE_SSP1_CLK_CLK_SEL_SHIFT) +#define CGU_BASE_SSP1_CLK_CLK_SEL(x) \ + ((x) << CGU_BASE_SSP1_CLK_CLK_SEL_SHIFT) + +/* --- CGU_BASE_UART0_CLK values -------------------------------- */ + +/* PD: Output stage power down */ +#define CGU_BASE_UART0_CLK_PD_SHIFT (0) +#define CGU_BASE_UART0_CLK_PD (1 << CGU_BASE_UART0_CLK_PD_SHIFT) + +/* AUTOBLOCK: Block clock automatically during frequency change */ +#define CGU_BASE_UART0_CLK_AUTOBLOCK_SHIFT (11) +#define CGU_BASE_UART0_CLK_AUTOBLOCK \ + (1 << CGU_BASE_UART0_CLK_AUTOBLOCK_SHIFT) + +/* CLK_SEL: Clock source selection */ +#define CGU_BASE_UART0_CLK_CLK_SEL_SHIFT (24) +#define CGU_BASE_UART0_CLK_CLK_SEL_MASK \ + (0x1f << CGU_BASE_UART0_CLK_CLK_SEL_SHIFT) +#define CGU_BASE_UART0_CLK_CLK_SEL(x) \ + ((x) << CGU_BASE_UART0_CLK_CLK_SEL_SHIFT) + +/* --- CGU_BASE_UART1_CLK values -------------------------------- */ + +/* PD: Output stage power down */ +#define CGU_BASE_UART1_CLK_PD_SHIFT (0) +#define CGU_BASE_UART1_CLK_PD (1 << CGU_BASE_UART1_CLK_PD_SHIFT) + +/* AUTOBLOCK: Block clock automatically during frequency change */ +#define CGU_BASE_UART1_CLK_AUTOBLOCK_SHIFT (11) +#define CGU_BASE_UART1_CLK_AUTOBLOCK \ + (1 << CGU_BASE_UART1_CLK_AUTOBLOCK_SHIFT) + +/* CLK_SEL: Clock source selection */ +#define CGU_BASE_UART1_CLK_CLK_SEL_SHIFT (24) +#define CGU_BASE_UART1_CLK_CLK_SEL_MASK \ + (0x1f << CGU_BASE_UART1_CLK_CLK_SEL_SHIFT) +#define CGU_BASE_UART1_CLK_CLK_SEL(x) \ + ((x) << CGU_BASE_UART1_CLK_CLK_SEL_SHIFT) + +/* --- CGU_BASE_UART2_CLK values -------------------------------- */ + +/* PD: Output stage power down */ +#define CGU_BASE_UART2_CLK_PD_SHIFT (0) +#define CGU_BASE_UART2_CLK_PD (1 << CGU_BASE_UART2_CLK_PD_SHIFT) + +/* AUTOBLOCK: Block clock automatically during frequency change */ +#define CGU_BASE_UART2_CLK_AUTOBLOCK_SHIFT (11) +#define CGU_BASE_UART2_CLK_AUTOBLOCK \ + (1 << CGU_BASE_UART2_CLK_AUTOBLOCK_SHIFT) + +/* CLK_SEL: Clock source selection */ +#define CGU_BASE_UART2_CLK_CLK_SEL_SHIFT (24) +#define CGU_BASE_UART2_CLK_CLK_SEL_MASK \ + (0x1f << CGU_BASE_UART2_CLK_CLK_SEL_SHIFT) +#define CGU_BASE_UART2_CLK_CLK_SEL(x) \ + ((x) << CGU_BASE_UART2_CLK_CLK_SEL_SHIFT) + +/* --- CGU_BASE_UART3_CLK values -------------------------------- */ + +/* PD: Output stage power down */ +#define CGU_BASE_UART3_CLK_PD_SHIFT (0) +#define CGU_BASE_UART3_CLK_PD (1 << CGU_BASE_UART3_CLK_PD_SHIFT) + +/* AUTOBLOCK: Block clock automatically during frequency change */ +#define CGU_BASE_UART3_CLK_AUTOBLOCK_SHIFT (11) +#define CGU_BASE_UART3_CLK_AUTOBLOCK \ + (1 << CGU_BASE_UART3_CLK_AUTOBLOCK_SHIFT) + +/* CLK_SEL: Clock source selection */ +#define CGU_BASE_UART3_CLK_CLK_SEL_SHIFT (24) +#define CGU_BASE_UART3_CLK_CLK_SEL_MASK \ + (0x1f << CGU_BASE_UART3_CLK_CLK_SEL_SHIFT) +#define CGU_BASE_UART3_CLK_CLK_SEL(x) \ + ((x) << CGU_BASE_UART3_CLK_CLK_SEL_SHIFT) + +/* --- CGU_BASE_OUT_CLK values ---------------------------------- */ + +/* PD: Output stage power down */ +#define CGU_BASE_OUT_CLK_PD_SHIFT (0) +#define CGU_BASE_OUT_CLK_PD (1 << CGU_BASE_OUT_CLK_PD_SHIFT) + +/* AUTOBLOCK: Block clock automatically during frequency change */ +#define CGU_BASE_OUT_CLK_AUTOBLOCK_SHIFT (11) +#define CGU_BASE_OUT_CLK_AUTOBLOCK (1 << CGU_BASE_OUT_CLK_AUTOBLOCK_SHIFT) + +/* CLK_SEL: Clock source selection */ +#define CGU_BASE_OUT_CLK_CLK_SEL_SHIFT (24) +#define CGU_BASE_OUT_CLK_CLK_SEL_MASK (0x1f << CGU_BASE_OUT_CLK_CLK_SEL_SHIFT) +#define CGU_BASE_OUT_CLK_CLK_SEL(x) ((x) << CGU_BASE_OUT_CLK_CLK_SEL_SHIFT) + +/* --- CGU_BASE_APLL_CLK values --------------------------------- */ + +/* PD: Output stage power down */ +#define CGU_BASE_APLL_CLK_PD_SHIFT (0) +#define CGU_BASE_APLL_CLK_PD (1 << CGU_BASE_APLL_CLK_PD_SHIFT) + +/* AUTOBLOCK: Block clock automatically during frequency change */ +#define CGU_BASE_APLL_CLK_AUTOBLOCK_SHIFT (11) +#define CGU_BASE_APLL_CLK_AUTOBLOCK (1 << CGU_BASE_APLL_CLK_AUTOBLOCK_SHIFT) + +/* CLK_SEL: Clock source selection */ +#define CGU_BASE_APLL_CLK_CLK_SEL_SHIFT (24) +#define CGU_BASE_APLL_CLK_CLK_SEL_MASK \ + (0x1f << CGU_BASE_APLL_CLK_CLK_SEL_SHIFT) +#define CGU_BASE_APLL_CLK_CLK_SEL(x) ((x) << CGU_BASE_APLL_CLK_CLK_SEL_SHIFT) + +/* --- CGU_BASE_CGU_OUT0_CLK values ----------------------------- */ + +/* PD: Output stage power down */ +#define CGU_BASE_CGU_OUT0_CLK_PD_SHIFT (0) +#define CGU_BASE_CGU_OUT0_CLK_PD (1 << CGU_BASE_CGU_OUT0_CLK_PD_SHIFT) + +/* AUTOBLOCK: Block clock automatically during frequency change */ +#define CGU_BASE_CGU_OUT0_CLK_AUTOBLOCK_SHIFT (11) +#define CGU_BASE_CGU_OUT0_CLK_AUTOBLOCK \ + (1 << CGU_BASE_CGU_OUT0_CLK_AUTOBLOCK_SHIFT) + +/* CLK_SEL: Clock source selection */ +#define CGU_BASE_CGU_OUT0_CLK_CLK_SEL_SHIFT (24) +#define CGU_BASE_CGU_OUT0_CLK_CLK_SEL_MASK \ + (0x1f << CGU_BASE_CGU_OUT0_CLK_CLK_SEL_SHIFT) +#define CGU_BASE_CGU_OUT0_CLK_CLK_SEL(x) \ + ((x) << CGU_BASE_CGU_OUT0_CLK_CLK_SEL_SHIFT) + +/* --- CGU_BASE_CGU_OUT1_CLK values ----------------------------- */ + +/* PD: Output stage power down */ +#define CGU_BASE_CGU_OUT1_CLK_PD_SHIFT (0) +#define CGU_BASE_CGU_OUT1_CLK_PD (1 << CGU_BASE_CGU_OUT1_CLK_PD_SHIFT) + +/* AUTOBLOCK: Block clock automatically during frequency change */ +#define CGU_BASE_CGU_OUT1_CLK_AUTOBLOCK_SHIFT (11) +#define CGU_BASE_CGU_OUT1_CLK_AUTOBLOCK \ + (1 << CGU_BASE_CGU_OUT1_CLK_AUTOBLOCK_SHIFT) + +/* CLK_SEL: Clock source selection */ +#define CGU_BASE_CGU_OUT1_CLK_CLK_SEL_SHIFT (24) +#define CGU_BASE_CGU_OUT1_CLK_CLK_SEL_MASK \ + (0x1f << CGU_BASE_CGU_OUT1_CLK_CLK_SEL_SHIFT) +#define CGU_BASE_CGU_OUT1_CLK_CLK_SEL(x) \ + ((x) << CGU_BASE_CGU_OUT1_CLK_CLK_SEL_SHIFT) + +/* --- CGU_BASE_x_CLK clock sources --------------------------------------- */ + +#define CGU_SRC_32K 0x00 +#define CGU_SRC_IRC 0x01 +#define CGU_SRC_ENET_RX 0x02 +#define CGU_SRC_ENET_TX 0x03 +#define CGU_SRC_GP_CLKIN 0x04 +#define CGU_SRC_XTAL 0x06 +#define CGU_SRC_PLL0USB 0x07 +#define CGU_SRC_PLL0AUDIO 0x08 +#define CGU_SRC_PLL1 0x09 +#define CGU_SRC_IDIVA 0x0C +#define CGU_SRC_IDIVB 0x0D +#define CGU_SRC_IDIVC 0x0E +#define CGU_SRC_IDIVD 0x0F +#define CGU_SRC_IDIVE 0x10 + +/**@}*/ + +#endif diff --git a/libopencm3/include/libopencm3/lpc43xx/creg.h b/libopencm3/include/libopencm3/lpc43xx/creg.h new file mode 100644 index 0000000..2c69551 --- /dev/null +++ b/libopencm3/include/libopencm3/lpc43xx/creg.h @@ -0,0 +1,354 @@ +/** @defgroup creg_defines Configuration Registers Defines + +@brief <b>Defined Constants and Types for the LPC43xx Configuration +Registers</b> + +@ingroup LPC43xx_defines + +@version 1.0.0 + +@author @htmlonly © @endhtmlonly 2012 Michael Ossmann <mike@ossmann.com> + +@date 10 March 2013 + +LGPL License Terms @ref lgpl_license + */ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2012 Michael Ossmann <mike@ossmann.com> + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see <http://www.gnu.org/licenses/>. + */ + +#ifndef LPC43XX_CREG_H +#define LPC43XX_CREG_H + +/**@{*/ + +#include <libopencm3/cm3/common.h> +#include <libopencm3/lpc43xx/memorymap.h> + +/* --- CREG registers ----------------------------------------------------- */ + +/* + * Chip configuration register 32 kHz oscillator output and BOD control + * register + */ +#define CREG_CREG0 MMIO32(CREG_BASE + 0x004) + +/* ARM Cortex-M4 memory mapping */ +#define CREG_M4MEMMAP MMIO32(CREG_BASE + 0x100) + +/* Chip configuration register 1 */ +#define CREG_CREG1 MMIO32(CREG_BASE + 0x108) + +/* Chip configuration register 2 */ +#define CREG_CREG2 MMIO32(CREG_BASE + 0x10C) + +/* Chip configuration register 3 */ +#define CREG_CREG3 MMIO32(CREG_BASE + 0x110) + +/* Chip configuration register 4 */ +#define CREG_CREG4 MMIO32(CREG_BASE + 0x114) + +/* Chip configuration register 5 */ +#define CREG_CREG5 MMIO32(CREG_BASE + 0x118) + +/* DMA muxing control */ +#define CREG_DMAMUX MMIO32(CREG_BASE + 0x11C) + +/* Flash accelerator configuration register for flash bank A */ +#define CREG_FLASHCFGA MMIO32(CREG_BASE + 0x120) + +/* Flash accelerator configuration register for flash bank B */ +#define CREG_FLASHCFGB MMIO32(CREG_BASE + 0x124) + +/* ETB RAM configuration */ +#define CREG_ETBCFG MMIO32(CREG_BASE + 0x128) + +/* + * Chip configuration register 6. Controls multiple functions: Ethernet + * interface, SCT output, I2S0/1 inputs, EMC clock. + */ +#define CREG_CREG6 MMIO32(CREG_BASE + 0x12C) + +/* Cortex-M4 TXEV event clear */ +#define CREG_M4TXEVENT MMIO32(CREG_BASE + 0x130) + +/* Part ID (Boundary scan ID code, read-only) */ +#define CREG_CHIPID MMIO32(CREG_BASE + 0x200) + +/* Cortex-M0 TXEV event clear */ +#define CREG_M0TXEVENT MMIO32(CREG_BASE + 0x400) + +/* ARM Cortex-M0 memory mapping */ +#define CREG_M0APPMEMMAP MMIO32(CREG_BASE + 0x404) + +/* USB0 frame length adjust register */ +#define CREG_USB0FLADJ MMIO32(CREG_BASE + 0x500) + +/* USB1 frame length adjust register */ +#define CREG_USB1FLADJ MMIO32(CREG_BASE + 0x600) + +/* --- CREG_CREG0 values ---------------------------------------- */ + +/* EN1KHZ: Enable 1 kHz output */ +#define CREG_CREG0_EN1KHZ_SHIFT (0) +#define CREG_CREG0_EN1KHZ (1 << CREG_CREG0_EN1KHZ_SHIFT) + +/* EN32KHZ: Enable 32 kHz output */ +#define CREG_CREG0_EN32KHZ_SHIFT (1) +#define CREG_CREG0_EN32KHZ (1 << CREG_CREG0_EN32KHZ_SHIFT) + +/* RESET32KHZ: 32 kHz oscillator reset */ +#define CREG_CREG0_RESET32KHZ_SHIFT (2) +#define CREG_CREG0_RESET32KHZ (1 << CREG_CREG0_RESET32KHZ_SHIFT) + +/* PD32KHZ: 32 kHz power control */ +#define CREG_CREG0_PD32KHZ_SHIFT (3) +#define CREG_CREG0_PD32KHZ (1 << CREG_CREG0_PD32KHZ_SHIFT) + +/* USB0PHY: USB0 PHY power control */ +#define CREG_CREG0_USB0PHY_SHIFT (5) +#define CREG_CREG0_USB0PHY (1 << CREG_CREG0_USB0PHY_SHIFT) + +/* ALARMCTRL: RTC_ALARM pin output control */ +#define CREG_CREG0_ALARMCTRL_SHIFT (6) +#define CREG_CREG0_ALARMCTRL_MASK (0x3 << CREG_CREG0_ALARMCTRL_SHIFT) +#define CREG_CREG0_ALARMCTRL(x) ((x) << CREG_CREG0_ALARMCTRL_SHIFT) + +/* BODLVL1: BOD trip level to generate an interrupt */ +#define CREG_CREG0_BODLVL1_SHIFT (8) +#define CREG_CREG0_BODLVL1_MASK (0x3 << CREG_CREG0_BODLVL1_SHIFT) +#define CREG_CREG0_BODLVL1(x) ((x) << CREG_CREG0_BODLVL1_SHIFT) + +/* BODLVL2: BOD trip level to generate a reset */ +#define CREG_CREG0_BODLVL2_SHIFT (10) +#define CREG_CREG0_BODLVL2_MASK (0x3 << CREG_CREG0_BODLVL2_SHIFT) +#define CREG_CREG0_BODLVL2(x) ((x) << CREG_CREG0_BODLVL2_SHIFT) + +/* SAMPLECTRL: SAMPLE pin input/output control */ +#define CREG_CREG0_SAMPLECTRL_SHIFT (12) +#define CREG_CREG0_SAMPLECTRL_MASK (0x3 << CREG_CREG0_SAMPLECTRL_SHIFT) +#define CREG_CREG0_SAMPLECTRL(x) ((x) << CREG_CREG0_SAMPLECTRL_SHIFT) + +/* WAKEUP0CTRL: WAKEUP0 pin input/output control */ +#define CREG_CREG0_WAKEUP0CTRL_SHIFT (14) +#define CREG_CREG0_WAKEUP0CTRL_MASK (0x3 << CREG_CREG0_WAKEUP0CTRL_SHIFT) +#define CREG_CREG0_WAKEUP0CTRL(x) ((x) << CREG_CREG0_WAKEUP0CTRL_SHIFT) + +/* WAKEUP1CTRL: WAKEUP1 pin input/output control */ +#define CREG_CREG0_WAKEUP1CTRL_SHIFT (16) +#define CREG_CREG0_WAKEUP1CTRL_MASK (0x3 << CREG_CREG0_WAKEUP1CTRL_SHIFT) +#define CREG_CREG0_WAKEUP1CTRL(x) ((x) << CREG_CREG0_WAKEUP1CTRL_SHIFT) + +/* --- CREG_M4MEMMAP values ------------------------------------- */ + +/* M4MAP: Shadow address when accessing memory at address 0x00000000 */ +#define CREG_M4MEMMAP_M4MAP_SHIFT (12) +#define CREG_M4MEMMAP_M4MAP_MASK (0xfffff << CREG_M4MEMMAP_M4MAP_SHIFT) +#define CREG_M4MEMMAP_M4MAP(x) ((x) << CREG_M4MEMMAP_M4MAP_SHIFT) + +/* --- CREG_CREG5 values ---------------------------------------- */ + +/* M4TAPSEL: JTAG debug select for M4 core */ +#define CREG_CREG5_M4TAPSEL_SHIFT (6) +#define CREG_CREG5_M4TAPSEL (1 << CREG_CREG5_M4TAPSEL_SHIFT) + +/* M0APPTAPSEL: JTAG debug select for M0 co-processor */ +#define CREG_CREG5_M0APPTAPSEL_SHIFT (9) +#define CREG_CREG5_M0APPTAPSEL (1 << CREG_CREG5_M0APPTAPSEL_SHIFT) + +/* --- CREG_DMAMUX values --------------------------------------- */ + +/* DMAMUXPER0: Select DMA to peripheral connection for DMA peripheral 0 */ +#define CREG_DMAMUX_DMAMUXPER0_SHIFT (0) +#define CREG_DMAMUX_DMAMUXPER0_MASK (0x3 << CREG_DMAMUX_DMAMUXPER0_SHIFT) +#define CREG_DMAMUX_DMAMUXPER0(x) ((x) << CREG_DMAMUX_DMAMUXPER0_SHIFT) + +/* DMAMUXPER1: Select DMA to peripheral connection for DMA peripheral 1 */ +#define CREG_DMAMUX_DMAMUXPER1_SHIFT (2) +#define CREG_DMAMUX_DMAMUXPER1_MASK (0x3 << CREG_DMAMUX_DMAMUXPER1_SHIFT) +#define CREG_DMAMUX_DMAMUXPER1(x) ((x) << CREG_DMAMUX_DMAMUXPER1_SHIFT) + +/* DMAMUXPER2: Select DMA to peripheral connection for DMA peripheral 2 */ +#define CREG_DMAMUX_DMAMUXPER2_SHIFT (4) +#define CREG_DMAMUX_DMAMUXPER2_MASK (0x3 << CREG_DMAMUX_DMAMUXPER2_SHIFT) +#define CREG_DMAMUX_DMAMUXPER2(x) ((x) << CREG_DMAMUX_DMAMUXPER2_SHIFT) + +/* DMAMUXPER3: Select DMA to peripheral connection for DMA peripheral 3 */ +#define CREG_DMAMUX_DMAMUXPER3_SHIFT (6) +#define CREG_DMAMUX_DMAMUXPER3_MASK (0x3 << CREG_DMAMUX_DMAMUXPER3_SHIFT) +#define CREG_DMAMUX_DMAMUXPER3(x) ((x) << CREG_DMAMUX_DMAMUXPER3_SHIFT) + +/* DMAMUXPER4: Select DMA to peripheral connection for DMA peripheral 4 */ +#define CREG_DMAMUX_DMAMUXPER4_SHIFT (8) +#define CREG_DMAMUX_DMAMUXPER4_MASK (0x3 << CREG_DMAMUX_DMAMUXPER4_SHIFT) +#define CREG_DMAMUX_DMAMUXPER4(x) ((x) << CREG_DMAMUX_DMAMUXPER4_SHIFT) + +/* DMAMUXPER5: Select DMA to peripheral connection for DMA peripheral 5 */ +#define CREG_DMAMUX_DMAMUXPER5_SHIFT (10) +#define CREG_DMAMUX_DMAMUXPER5_MASK (0x3 << CREG_DMAMUX_DMAMUXPER5_SHIFT) +#define CREG_DMAMUX_DMAMUXPER5(x) ((x) << CREG_DMAMUX_DMAMUXPER5_SHIFT) + +/* DMAMUXPER6: Select DMA to peripheral connection for DMA peripheral 6 */ +#define CREG_DMAMUX_DMAMUXPER6_SHIFT (12) +#define CREG_DMAMUX_DMAMUXPER6_MASK (0x3 << CREG_DMAMUX_DMAMUXPER6_SHIFT) +#define CREG_DMAMUX_DMAMUXPER6(x) ((x) << CREG_DMAMUX_DMAMUXPER6_SHIFT) + +/* DMAMUXPER7: Select DMA to peripheral connection for DMA peripheral 7 */ +#define CREG_DMAMUX_DMAMUXPER7_SHIFT (14) +#define CREG_DMAMUX_DMAMUXPER7_MASK (0x3 << CREG_DMAMUX_DMAMUXPER7_SHIFT) +#define CREG_DMAMUX_DMAMUXPER7(x) ((x) << CREG_DMAMUX_DMAMUXPER7_SHIFT) + +/* DMAMUXPER8: Select DMA to peripheral connection for DMA peripheral 8 */ +#define CREG_DMAMUX_DMAMUXPER8_SHIFT (16) +#define CREG_DMAMUX_DMAMUXPER8_MASK (0x3 << CREG_DMAMUX_DMAMUXPER8_SHIFT) +#define CREG_DMAMUX_DMAMUXPER8(x) ((x) << CREG_DMAMUX_DMAMUXPER8_SHIFT) + +/* DMAMUXPER9: Select DMA to peripheral connection for DMA peripheral 9 */ +#define CREG_DMAMUX_DMAMUXPER9_SHIFT (18) +#define CREG_DMAMUX_DMAMUXPER9_MASK (0x3 << CREG_DMAMUX_DMAMUXPER9_SHIFT) +#define CREG_DMAMUX_DMAMUXPER9(x) ((x) << CREG_DMAMUX_DMAMUXPER9_SHIFT) + +/* DMAMUXPER10: Select DMA to peripheral connection for DMA peripheral 10 */ +#define CREG_DMAMUX_DMAMUXPER10_SHIFT (20) +#define CREG_DMAMUX_DMAMUXPER10_MASK (0x3 << CREG_DMAMUX_DMAMUXPER10_SHIFT) +#define CREG_DMAMUX_DMAMUXPER10(x) ((x) << CREG_DMAMUX_DMAMUXPER10_SHIFT) + +/* DMAMUXPER11: Select DMA to peripheral connection for DMA peripheral 11 */ +#define CREG_DMAMUX_DMAMUXPER11_SHIFT (22) +#define CREG_DMAMUX_DMAMUXPER11_MASK (0x3 << CREG_DMAMUX_DMAMUXPER11_SHIFT) +#define CREG_DMAMUX_DMAMUXPER11(x) ((x) << CREG_DMAMUX_DMAMUXPER11_SHIFT) + +/* DMAMUXPER12: Select DMA to peripheral connection for DMA peripheral 12 */ +#define CREG_DMAMUX_DMAMUXPER12_SHIFT (24) +#define CREG_DMAMUX_DMAMUXPER12_MASK (0x3 << CREG_DMAMUX_DMAMUXPER12_SHIFT) +#define CREG_DMAMUX_DMAMUXPER12(x) ((x) << CREG_DMAMUX_DMAMUXPER12_SHIFT) + +/* DMAMUXPER13: Select DMA to peripheral connection for DMA peripheral 13 */ +#define CREG_DMAMUX_DMAMUXPER13_SHIFT (26) +#define CREG_DMAMUX_DMAMUXPER13_MASK (0x3 << CREG_DMAMUX_DMAMUXPER13_SHIFT) +#define CREG_DMAMUX_DMAMUXPER13(x) ((x) << CREG_DMAMUX_DMAMUXPER13_SHIFT) + +/* DMAMUXPER14: Select DMA to peripheral connection for DMA peripheral 14 */ +#define CREG_DMAMUX_DMAMUXPER14_SHIFT (28) +#define CREG_DMAMUX_DMAMUXPER14_MASK (0x3 << CREG_DMAMUX_DMAMUXPER14_SHIFT) +#define CREG_DMAMUX_DMAMUXPER14(x) ((x) << CREG_DMAMUX_DMAMUXPER14_SHIFT) + +/* DMAMUXPER15: Select DMA to peripheral connection for DMA peripheral 15 */ +#define CREG_DMAMUX_DMAMUXPER15_SHIFT (30) +#define CREG_DMAMUX_DMAMUXPER15_MASK (0x3 << CREG_DMAMUX_DMAMUXPER15_SHIFT) +#define CREG_DMAMUX_DMAMUXPER15(x) ((x) << CREG_DMAMUX_DMAMUXPER15_SHIFT) + +/* --- CREG_FLASHCFGA values ------------------------------------ */ + +/* FLASHTIM: Flash access time. The value of this field plus 1 gives the number + * of BASE_M4_CLK clocks used for a flash access */ +#define CREG_FLASHCFGA_FLASHTIM_SHIFT (12) +#define CREG_FLASHCFGA_FLASHTIM_MASK (0xf << CREG_FLASHCFGA_FLASHTIM_SHIFT) +#define CREG_FLASHCFGA_FLASHTIM(x) ((x) << CREG_FLASHCFGA_FLASHTIM_SHIFT) + +/* POW: Flash bank A power control */ +#define CREG_FLASHCFGA_POW_SHIFT (31) +#define CREG_FLASHCFGA_POW (1 << CREG_FLASHCFGA_POW_SHIFT) + +/* --- CREG_FLASHCFGB values ------------------------------------ */ + +/* FLASHTIM: Flash access time. The value of this field plus 1 gives the number + * of BASE_M4_CLK clocks used for a flash access */ +#define CREG_FLASHCFGB_FLASHTIM_SHIFT (12) +#define CREG_FLASHCFGB_FLASHTIM_MASK (0xf << CREG_FLASHCFGB_FLASHTIM_SHIFT) +#define CREG_FLASHCFGB_FLASHTIM(x) ((x) << CREG_FLASHCFGB_FLASHTIM_SHIFT) + +/* POW: Flash bank B power control */ +#define CREG_FLASHCFGB_POW_SHIFT (31) +#define CREG_FLASHCFGB_POW (1 << CREG_FLASHCFGB_POW_SHIFT) + +/* --- CREG_ETBCFG values --------------------------------------- */ + +/* ETB: Select SRAM interface */ +#define CREG_ETBCFG_ETB_SHIFT (0) +#define CREG_ETBCFG_ETB (1 << CREG_ETBCFG_ETB_SHIFT) + +/* --- CREG_CREG6 values ---------------------------------------- */ + +/* ETHMODE: Selects the Ethernet mode. Reset the ethernet after changing the + * PHY interface */ +#define CREG_CREG6_ETHMODE_SHIFT (0) +#define CREG_CREG6_ETHMODE_MASK (0x7 << CREG_CREG6_ETHMODE_SHIFT) +#define CREG_CREG6_ETHMODE(x) ((x) << CREG_CREG6_ETHMODE_SHIFT) + +/* CTOUTCTRL: Selects the functionality of the SCT outputs */ +#define CREG_CREG6_CTOUTCTRL_SHIFT (4) +#define CREG_CREG6_CTOUTCTRL (1 << CREG_CREG6_CTOUTCTRL_SHIFT) + +/* I2S0_TX_SCK_IN_SEL: I2S0_TX_SCK input select */ +#define CREG_CREG6_I2S0_TX_SCK_IN_SEL_SHIFT (12) +#define CREG_CREG6_I2S0_TX_SCK_IN_SEL (1 << CREG_CREG6_I2S0_TX_SCK_IN_SEL_SHIFT) + +/* I2S0_RX_SCK_IN_SEL: I2S0_RX_SCK input select */ +#define CREG_CREG6_I2S0_RX_SCK_IN_SEL_SHIFT (13) +#define CREG_CREG6_I2S0_RX_SCK_IN_SEL (1 << CREG_CREG6_I2S0_RX_SCK_IN_SEL_SHIFT) + +/* I2S1_TX_SCK_IN_SEL: I2S1_TX_SCK input select */ +#define CREG_CREG6_I2S1_TX_SCK_IN_SEL_SHIFT (14) +#define CREG_CREG6_I2S1_TX_SCK_IN_SEL (1 << CREG_CREG6_I2S1_TX_SCK_IN_SEL_SHIFT) + +/* I2S1_RX_SCK_IN_SEL: I2S1_RX_SCK input select */ +#define CREG_CREG6_I2S1_RX_SCK_IN_SEL_SHIFT (15) +#define CREG_CREG6_I2S1_RX_SCK_IN_SEL (1 << CREG_CREG6_I2S1_RX_SCK_IN_SEL_SHIFT) + +/* EMC_CLK_SEL: EMC_CLK divided clock select */ +#define CREG_CREG6_EMC_CLK_SEL_SHIFT (16) +#define CREG_CREG6_EMC_CLK_SEL (1 << CREG_CREG6_EMC_CLK_SEL_SHIFT) + +/* --- CREG_M4TXEVENT values ------------------------------------ */ + +/* TXEVCLR: Cortex-M4 TXEV event */ +#define CREG_M4TXEVENT_TXEVCLR_SHIFT (0) +#define CREG_M4TXEVENT_TXEVCLR (1 << CREG_M4TXEVENT_TXEVCLR_SHIFT) + +/* --- CREG_M0TXEVENT values ------------------------------------ */ + +/* TXEVCLR: Cortex-M0 TXEV event */ +#define CREG_M0TXEVENT_TXEVCLR_SHIFT (0) +#define CREG_M0TXEVENT_TXEVCLR (1 << CREG_M0TXEVENT_TXEVCLR_SHIFT) + +/* --- CREG_M0APPMEMMAP values ---------------------------------- */ + +/* M0APPMAP: Shadow address when accessing memory at address 0x00000000 */ +#define CREG_M0APPMEMMAP_M0APPMAP_SHIFT (12) +#define CREG_M0APPMEMMAP_M0APPMAP_MASK \ + (0xfffff << CREG_M0APPMEMMAP_M0APPMAP_SHIFT) +#define CREG_M0APPMEMMAP_M0APPMAP(x) ((x) << CREG_M0APPMEMMAP_M0APPMAP_SHIFT) + +/* --- CREG_USB0FLADJ values ------------------------------------ */ + +/* FLTV: Frame length timing value */ +#define CREG_USB0FLADJ_FLTV_SHIFT (0) +#define CREG_USB0FLADJ_FLTV_MASK (0x3f << CREG_USB0FLADJ_FLTV_SHIFT) +#define CREG_USB0FLADJ_FLTV(x) ((x) << CREG_USB0FLADJ_FLTV_SHIFT) + +/* --- CREG_USB1FLADJ values ------------------------------------ */ + +/* FLTV: Frame length timing value */ +#define CREG_USB1FLADJ_FLTV_SHIFT (0) +#define CREG_USB1FLADJ_FLTV_MASK (0x3f << CREG_USB1FLADJ_FLTV_SHIFT) +#define CREG_USB1FLADJ_FLTV(x) ((x) << CREG_USB1FLADJ_FLTV_SHIFT) + +/**@}*/ + +#endif diff --git a/libopencm3/include/libopencm3/lpc43xx/doc-lpc43xx.h b/libopencm3/include/libopencm3/lpc43xx/doc-lpc43xx.h new file mode 100644 index 0000000..3c21aae --- /dev/null +++ b/libopencm3/include/libopencm3/lpc43xx/doc-lpc43xx.h @@ -0,0 +1,32 @@ +/** @mainpage libopencm3 LPC43xx + +@version 1.0.0 + +@date 14 September 2012 + +API documentation for NXP Semiconductors LPC43xx Cortex M3 series. + +LGPL License Terms @ref lgpl_license +*/ + +/** @defgroup LPC43xx LPC43xx +Libraries for NXP Semiconductors LPC43xx series. + +@version 1.0.0 + +@date 14 September 2012 + +LGPL License Terms @ref lgpl_license +*/ + +/** @defgroup LPC43xx_defines LPC43xx Defines + +@brief Defined Constants and Types for the LPC43xx series + +@version 1.0.0 + +@date 14 September 2012 + +LGPL License Terms @ref lgpl_license +*/ + diff --git a/libopencm3/include/libopencm3/lpc43xx/eventrouter.h b/libopencm3/include/libopencm3/lpc43xx/eventrouter.h new file mode 100644 index 0000000..d27c67c --- /dev/null +++ b/libopencm3/include/libopencm3/lpc43xx/eventrouter.h @@ -0,0 +1,70 @@ +/** @defgroup eventrouter_defines Event Router Defines + +@brief <b>Defined Constants and Types for the LPC43xx Event Router</b> + +@ingroup LPC43xx_defines + +@version 1.0.0 + +@author @htmlonly © @endhtmlonly 2012 Michael Ossmann <mike@ossmann.com> + +@date 10 March 2013 + +LGPL License Terms @ref lgpl_license + */ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2012 Michael Ossmann <mike@ossmann.com> + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see <http://www.gnu.org/licenses/>. + */ + +#ifndef LPC43XX_EVENTROUTER_H +#define LPC43XX_EVENTROUTER_H + +/**@{*/ + +#include <libopencm3/cm3/common.h> +#include <libopencm3/lpc43xx/memorymap.h> + +/* --- Event Router registers ---------------------------------------------- */ + +/* Level configuration register */ +#define EVENTROUTER_HILO MMIO32(EVENTROUTER_BASE + 0x000) + +/* Edge configuration */ +#define EVENTROUTER_EDGE MMIO32(EVENTROUTER_BASE + 0x004) + +/* Clear event enable register */ +#define EVENTROUTER_CLR_EN MMIO32(EVENTROUTER_BASE + 0xFD8) + +/* Set event enable register */ +#define EVENTROUTER_SET_EN MMIO32(EVENTROUTER_BASE + 0xFDC) + +/* Event Status register */ +#define EVENTROUTER_STATUS MMIO32(EVENTROUTER_BASE + 0xFE0) + +/* Event Enable register */ +#define EVENTROUTER_ENABLE MMIO32(EVENTROUTER_BASE + 0xFE4) + +/* Clear event status register */ +#define EVENTROUTER_CLR_STAT MMIO32(EVENTROUTER_BASE + 0xFE8) + +/* Set event status register */ +#define EVENTROUTER_SET_STAT MMIO32(EVENTROUTER_BASE + 0xFEC) + +/**@}*/ + +#endif diff --git a/libopencm3/include/libopencm3/lpc43xx/gima.h b/libopencm3/include/libopencm3/lpc43xx/gima.h new file mode 100644 index 0000000..6a36c76 --- /dev/null +++ b/libopencm3/include/libopencm3/lpc43xx/gima.h @@ -0,0 +1,137 @@ +/** @defgroup gima_defines Global Input Multiplexer Array Defines + +@brief <b>Defined Constants and Types for the LPC43xx Global Input Multiplexer +Array</b> + +@ingroup LPC43xx_defines + +@version 1.0.0 + +@author @htmlonly © @endhtmlonly 2012 Michael Ossmann <mike@ossmann.com> + +@date 10 March 2013 + +LGPL License Terms @ref lgpl_license + */ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2012 Michael Ossmann <mike@ossmann.com> + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see <http://www.gnu.org/licenses/>. + */ + +#ifndef LPC43XX_GIMA_H +#define LPC43XX_GIMA_H + +/**@{*/ + +#include <libopencm3/cm3/common.h> +#include <libopencm3/lpc43xx/memorymap.h> + +/* --- GIMA registers ----------------------------------------------------- */ + +/* Timer 0 CAP0_0 capture input multiplexer (GIMA output 0) */ +#define GIMA_CAP0_0_IN MMIO32(GIMA_BASE + 0x000) + +/* Timer 0 CAP0_1 capture input multiplexer (GIMA output 1) */ +#define GIMA_CAP0_1_IN MMIO32(GIMA_BASE + 0x004) + +/* Timer 0 CAP0_2 capture input multiplexer (GIMA output 2) */ +#define GIMA_CAP0_2_IN MMIO32(GIMA_BASE + 0x008) + +/* Timer 0 CAP0_3 capture input multiplexer (GIMA output 3) */ +#define GIMA_CAP0_3_IN MMIO32(GIMA_BASE + 0x00C) + +/* Timer 1 CAP1_0 capture input multiplexer (GIMA output 4) */ +#define GIMA_CAP1_0_IN MMIO32(GIMA_BASE + 0x010) + +/* Timer 1 CAP1_1 capture input multiplexer (GIMA output 5) */ +#define GIMA_CAP1_1_IN MMIO32(GIMA_BASE + 0x014) + +/* Timer 1 CAP1_2 capture input multiplexer (GIMA output 6) */ +#define GIMA_CAP1_2_IN MMIO32(GIMA_BASE + 0x018) + +/* Timer 1 CAP1_3 capture input multiplexer (GIMA output 7) */ +#define GIMA_CAP1_3_IN MMIO32(GIMA_BASE + 0x01C) + +/* Timer 2 CAP2_0 capture input multiplexer (GIMA output 8) */ +#define GIMA_CAP2_0_IN MMIO32(GIMA_BASE + 0x020) + +/* Timer 2 CAP2_1 capture input multiplexer (GIMA output 9) */ +#define GIMA_CAP2_1_IN MMIO32(GIMA_BASE + 0x024) + +/* Timer 2 CAP2_2 capture input multiplexer (GIMA output 10) */ +#define GIMA_CAP2_2_IN MMIO32(GIMA_BASE + 0x028) + +/* Timer 2 CAP2_3 capture input multiplexer (GIMA output 11) */ +#define GIMA_CAP2_3_IN MMIO32(GIMA_BASE + 0x02C) + +/* Timer 3 CAP3_0 capture input multiplexer (GIMA output 12) */ +#define GIMA_CAP3_0_IN MMIO32(GIMA_BASE + 0x030) + +/* Timer 3 CAP3_1 capture input multiplexer (GIMA output 13) */ +#define GIMA_CAP3_1_IN MMIO32(GIMA_BASE + 0x034) + +/* Timer 3 CAP3_2 capture input multiplexer (GIMA output 14) */ +#define GIMA_CAP3_2_IN MMIO32(GIMA_BASE + 0x038) + +/* Timer 3 CAP3_3 capture input multiplexer (GIMA output 15) */ +#define GIMA_CAP3_3_IN MMIO32(GIMA_BASE + 0x03C) + +/* SCT CTIN_0 capture input multiplexer (GIMA output 16) */ +#define GIMA_CTIN_0_IN MMIO32(GIMA_BASE + 0x040) + +/* SCT CTIN_1 capture input multiplexer (GIMA output 17) */ +#define GIMA_CTIN_1_IN MMIO32(GIMA_BASE + 0x044) + +/* SCT CTIN_2 capture input multiplexer (GIMA output 18) */ +#define GIMA_CTIN_2_IN MMIO32(GIMA_BASE + 0x048) + +/* SCT CTIN_3 capture input multiplexer (GIMA output 19) */ +#define GIMA_CTIN_3_IN MMIO32(GIMA_BASE + 0x04C) + +/* SCT CTIN_4 capture input multiplexer (GIMA output 20) */ +#define GIMA_CTIN_4_IN MMIO32(GIMA_BASE + 0x050) + +/* SCT CTIN_5 capture input multiplexer (GIMA output 21) */ +#define GIMA_CTIN_5_IN MMIO32(GIMA_BASE + 0x054) + +/* SCT CTIN_6 capture input multiplexer (GIMA output 22) */ +#define GIMA_CTIN_6_IN MMIO32(GIMA_BASE + 0x058) + +/* SCT CTIN_7 capture input multiplexer (GIMA output 23) */ +#define GIMA_CTIN_7_IN MMIO32(GIMA_BASE + 0x05C) + +/* VADC trigger input multiplexer (GIMA output 24) */ +#define GIMA_VADC_TRIGGER_IN MMIO32(GIMA_BASE + 0x060) + +/* Event router input 13 multiplexer (GIMA output 25) */ +#define GIMA_EVENTROUTER_13_IN MMIO32(GIMA_BASE + 0x064) + +/* Event router input 14 multiplexer (GIMA output 26) */ +#define GIMA_EVENTROUTER_14_IN MMIO32(GIMA_BASE + 0x068) + +/* Event router input 16 multiplexer (GIMA output 27) */ +#define GIMA_EVENTROUTER_16_IN MMIO32(GIMA_BASE + 0x06C) + +/* ADC start0 input multiplexer (GIMA output 28) */ +#define GIMA_ADCSTART0_IN MMIO32(GIMA_BASE + 0x070) + +/* ADC start1 input multiplexer (GIMA output 29) */ +#define GIMA_ADCSTART1_IN MMIO32(GIMA_BASE + 0x074) + +/**@}*/ + +#endif diff --git a/libopencm3/include/libopencm3/lpc43xx/gpdma.h b/libopencm3/include/libopencm3/lpc43xx/gpdma.h new file mode 100644 index 0000000..9df6698 --- /dev/null +++ b/libopencm3/include/libopencm3/lpc43xx/gpdma.h @@ -0,0 +1,552 @@ +/** @defgroup gpdma_defines General Purpose DMA Defines + * + * @brief <b>Defined Constants and Types for the LPC43xx General Purpose DMA</b> + * + * @ingroup LPC43xx_defines + * + * @version 1.0.0 + * + * @author @htmlonly © @endhtmlonly 2012 Michael Ossmann <mike@ossmann.com> + * + * @date 10 March 2013 + * + * LGPL License Terms @ref lgpl_license + */ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2012 Michael Ossmann <mike@ossmann.com> + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see <http://www.gnu.org/licenses/>. + */ + +#ifndef LPC43XX_GPDMA_H +#define LPC43XX_GPDMA_H + +/**@{*/ + +#include <libopencm3/cm3/common.h> +#include <libopencm3/lpc43xx/memorymap.h> + +/* --- GPDMA registers ----------------------------------------------------- */ + +/* General registers */ + +/* DMA Interrupt Status Register */ +#define GPDMA_INTSTAT MMIO32(GPDMA_BASE + 0x000) + +/* DMA Interrupt Terminal Count Request Status Register */ +#define GPDMA_INTTCSTAT MMIO32(GPDMA_BASE + 0x004) + +/* DMA Interrupt Terminal Count Request Clear Register */ +#define GPDMA_INTTCCLEAR MMIO32(GPDMA_BASE + 0x008) + +/* DMA Interrupt Error Status Register */ +#define GPDMA_INTERRSTAT MMIO32(GPDMA_BASE + 0x00C) + +/* DMA Interrupt Error Clear Register */ +#define GPDMA_INTERRCLR MMIO32(GPDMA_BASE + 0x010) + +/* DMA Raw Interrupt Terminal Count Status Register */ +#define GPDMA_RAWINTTCSTAT MMIO32(GPDMA_BASE + 0x014) + +/* DMA Raw Error Interrupt Status Register */ +#define GPDMA_RAWINTERRSTAT MMIO32(GPDMA_BASE + 0x018) + +/* DMA Enabled Channel Register */ +#define GPDMA_ENBLDCHNS MMIO32(GPDMA_BASE + 0x01C) + +/* DMA Software Burst Request Register */ +#define GPDMA_SOFTBREQ MMIO32(GPDMA_BASE + 0x020) + +/* DMA Software Single Request Register */ +#define GPDMA_SOFTSREQ MMIO32(GPDMA_BASE + 0x024) + +/* DMA Software Last Burst Request Register */ +#define GPDMA_SOFTLBREQ MMIO32(GPDMA_BASE + 0x028) + +/* DMA Software Last Single Request Register */ +#define GPDMA_SOFTLSREQ MMIO32(GPDMA_BASE + 0x02C) + +/* DMA Configuration Register */ +#define GPDMA_CONFIG MMIO32(GPDMA_BASE + 0x030) + +/* DMA Synchronization Register */ +#define GPDMA_SYNC MMIO32(GPDMA_BASE + 0x034) + + +/* Channel registers */ + +/* Source Address Register */ +#define GPDMA_CSRCADDR(channel) MMIO32(GPDMA_BASE + 0x100 + \ + (channel * 0x20)) +#define GPDMA_C0SRCADDR GPDMA_CSRCADDR(0) +#define GPDMA_C1SRCADDR GPDMA_CSRCADDR(1) +#define GPDMA_C2SRCADDR GPDMA_CSRCADDR(2) +#define GPDMA_C3SRCADDR GPDMA_CSRCADDR(3) +#define GPDMA_C4SRCADDR GPDMA_CSRCADDR(4) +#define GPDMA_C5SRCADDR GPDMA_CSRCADDR(5) +#define GPDMA_C6SRCADDR GPDMA_CSRCADDR(6) +#define GPDMA_C7SRCADDR GPDMA_CSRCADDR(7) + +/* Destination Address Register */ +#define GPDMA_CDESTADDR(channel) MMIO32(GPDMA_BASE + 0x104 + \ + (channel * 0x20)) +#define GPDMA_C0DESTADDR GPDMA_CDESTADDR(0) +#define GPDMA_C1DESTADDR GPDMA_CDESTADDR(1) +#define GPDMA_C2DESTADDR GPDMA_CDESTADDR(2) +#define GPDMA_C3DESTADDR GPDMA_CDESTADDR(3) +#define GPDMA_C4DESTADDR GPDMA_CDESTADDR(4) +#define GPDMA_C5DESTADDR GPDMA_CDESTADDR(5) +#define GPDMA_C6DESTADDR GPDMA_CDESTADDR(6) +#define GPDMA_C7DESTADDR GPDMA_CDESTADDR(7) + +/* Linked List Item Register */ +#define GPDMA_CLLI(channel) MMIO32(GPDMA_BASE + 0x108 + \ + (channel * 0x20)) +#define GPDMA_C0LLI GPDMA_CLLI(0) +#define GPDMA_C1LLI GPDMA_CLLI(1) +#define GPDMA_C2LLI GPDMA_CLLI(2) +#define GPDMA_C3LLI GPDMA_CLLI(3) +#define GPDMA_C4LLI GPDMA_CLLI(4) +#define GPDMA_C5LLI GPDMA_CLLI(5) +#define GPDMA_C6LLI GPDMA_CLLI(6) +#define GPDMA_C7LLI GPDMA_CLLI(7) + +/* Control Register */ +#define GPDMA_CCONTROL(channel) MMIO32(GPDMA_BASE + 0x10C + \ + (channel * 0x20)) +#define GPDMA_C0CONTROL GPDMA_CCONTROL(0) +#define GPDMA_C1CONTROL GPDMA_CCONTROL(1) +#define GPDMA_C2CONTROL GPDMA_CCONTROL(2) +#define GPDMA_C3CONTROL GPDMA_CCONTROL(3) +#define GPDMA_C4CONTROL GPDMA_CCONTROL(4) +#define GPDMA_C5CONTROL GPDMA_CCONTROL(5) +#define GPDMA_C6CONTROL GPDMA_CCONTROL(6) +#define GPDMA_C7CONTROL GPDMA_CCONTROL(7) + +/* Configuration Register */ +#define GPDMA_CCONFIG(channel) MMIO32(GPDMA_BASE + 0x110 + \ + (channel * 0x20)) +#define GPDMA_C0CONFIG GPDMA_CCONFIG(0) +#define GPDMA_C1CONFIG GPDMA_CCONFIG(1) +#define GPDMA_C2CONFIG GPDMA_CCONFIG(2) +#define GPDMA_C3CONFIG GPDMA_CCONFIG(3) +#define GPDMA_C4CONFIG GPDMA_CCONFIG(4) +#define GPDMA_C5CONFIG GPDMA_CCONFIG(5) +#define GPDMA_C6CONFIG GPDMA_CCONFIG(6) +#define GPDMA_C7CONFIG GPDMA_CCONFIG(7) + +/* --- Common fields -------------------------------------------- */ + +#define GPDMA_CSRCADDR_SRCADDR_SHIFT (0) +#define GPDMA_CSRCADDR_SRCADDR_MASK (0xffffffff << GPDMA_CSRCADDR_SRCADDR_SHIFT) +#define GPDMA_CSRCADDR_SRCADDR(x) ((x) << GPDMA_CSRCADDR_SRCADDR_SHIFT) + +#define GPDMA_CDESTADDR_DESTADDR_SHIFT (0) +#define GPDMA_CDESTADDR_DESTADDR_MASK \ + (0xffffffff << GPDMA_CDESTADDR_DESTADDR_SHIFT) +#define GPDMA_CDESTADDR_DESTADDR(x) ((x) << GPDMA_CDESTADDR_DESTADDR_SHIFT) + +#define GPDMA_CLLI_LM_SHIFT (0) +#define GPDMA_CLLI_LM_MASK (0x1 << GPDMA_CLLI_LM_SHIFT) +#define GPDMA_CLLI_LM(x) ((x) << GPDMA_CLLI_LM_SHIFT) + +#define GPDMA_CLLI_LLI_SHIFT (2) +#define GPDMA_CLLI_LLI_MASK (0x3fffffff << GPDMA_CLLI_LLI_SHIFT) +#define GPDMA_CLLI_LLI(x) ((x) << GPDMA_CLLI_LLI_SHIFT) + +#define GPDMA_CCONTROL_TRANSFERSIZE_SHIFT (0) +#define GPDMA_CCONTROL_TRANSFERSIZE_MASK \ + (0xfff << GPDMA_CCONTROL_TRANSFERSIZE_SHIFT) +#define GPDMA_CCONTROL_TRANSFERSIZE(x) \ + ((x) << GPDMA_CCONTROL_TRANSFERSIZE_SHIFT) + +#define GPDMA_CCONTROL_SBSIZE_SHIFT (12) +#define GPDMA_CCONTROL_SBSIZE_MASK (0x7 << GPDMA_CCONTROL_SBSIZE_SHIFT) +#define GPDMA_CCONTROL_SBSIZE(x) ((x) << GPDMA_CCONTROL_SBSIZE_SHIFT) + +#define GPDMA_CCONTROL_DBSIZE_SHIFT (15) +#define GPDMA_CCONTROL_DBSIZE_MASK (0x7 << GPDMA_CCONTROL_DBSIZE_SHIFT) +#define GPDMA_CCONTROL_DBSIZE(x) ((x) << GPDMA_CCONTROL_DBSIZE_SHIFT) + +#define GPDMA_CCONTROL_SWIDTH_SHIFT (18) +#define GPDMA_CCONTROL_SWIDTH_MASK (0x7 << GPDMA_CCONTROL_SWIDTH_SHIFT) +#define GPDMA_CCONTROL_SWIDTH(x) ((x) << GPDMA_CCONTROL_SWIDTH_SHIFT) + +#define GPDMA_CCONTROL_DWIDTH_SHIFT (21) +#define GPDMA_CCONTROL_DWIDTH_MASK (0x7 << GPDMA_CCONTROL_DWIDTH_SHIFT) +#define GPDMA_CCONTROL_DWIDTH(x) ((x) << GPDMA_CCONTROL_DWIDTH_SHIFT) + +#define GPDMA_CCONTROL_S_SHIFT (24) +#define GPDMA_CCONTROL_S_MASK (0x1 << GPDMA_CCONTROL_S_SHIFT) +#define GPDMA_CCONTROL_S(x) ((x) << GPDMA_CCONTROL_S_SHIFT) + +#define GPDMA_CCONTROL_D_SHIFT (25) +#define GPDMA_CCONTROL_D_MASK (0x1 << GPDMA_CCONTROL_D_SHIFT) +#define GPDMA_CCONTROL_D(x) ((x) << GPDMA_CCONTROL_D_SHIFT) + +#define GPDMA_CCONTROL_SI_SHIFT (26) +#define GPDMA_CCONTROL_SI_MASK (0x1 << GPDMA_CCONTROL_SI_SHIFT) +#define GPDMA_CCONTROL_SI(x) ((x) << GPDMA_CCONTROL_SI_SHIFT) + +#define GPDMA_CCONTROL_DI_SHIFT (27) +#define GPDMA_CCONTROL_DI_MASK (0x1 << GPDMA_CCONTROL_DI_SHIFT) +#define GPDMA_CCONTROL_DI(x) ((x) << GPDMA_CCONTROL_DI_SHIFT) + +#define GPDMA_CCONTROL_PROT1_SHIFT (28) +#define GPDMA_CCONTROL_PROT1_MASK (0x1 << GPDMA_CCONTROL_PROT1_SHIFT) +#define GPDMA_CCONTROL_PROT1(x) ((x) << GPDMA_CCONTROL_PROT1_SHIFT) + +#define GPDMA_CCONTROL_PROT2_SHIFT (29) +#define GPDMA_CCONTROL_PROT2_MASK (0x1 << GPDMA_CCONTROL_PROT2_SHIFT) +#define GPDMA_CCONTROL_PROT2(x) ((x) << GPDMA_CCONTROL_PROT2_SHIFT) + +#define GPDMA_CCONTROL_PROT3_SHIFT (30) +#define GPDMA_CCONTROL_PROT3_MASK (0x1 << GPDMA_CCONTROL_PROT3_SHIFT) +#define GPDMA_CCONTROL_PROT3(x) ((x) << GPDMA_CCONTROL_PROT3_SHIFT) + +#define GPDMA_CCONTROL_I_SHIFT (31) +#define GPDMA_CCONTROL_I_MASK (0x1 << GPDMA_CCONTROL_I_SHIFT) +#define GPDMA_CCONTROL_I(x) ((x) << GPDMA_CCONTROL_I_SHIFT) + +#define GPDMA_CCONFIG_E_SHIFT (0) +#define GPDMA_CCONFIG_E_MASK (0x1 << GPDMA_CCONFIG_E_SHIFT) +#define GPDMA_CCONFIG_E(x) ((x) << GPDMA_CCONFIG_E_SHIFT) + +#define GPDMA_CCONFIG_SRCPERIPHERAL_SHIFT (1) +#define GPDMA_CCONFIG_SRCPERIPHERAL_MASK \ + (0x1f << GPDMA_CCONFIG_SRCPERIPHERAL_SHIFT) +#define GPDMA_CCONFIG_SRCPERIPHERAL(x) \ + ((x) << GPDMA_CCONFIG_SRCPERIPHERAL_SHIFT) + +#define GPDMA_CCONFIG_DESTPERIPHERAL_SHIFT (6) +#define GPDMA_CCONFIG_DESTPERIPHERAL_MASK \ + (0x1f << GPDMA_CCONFIG_DESTPERIPHERAL_SHIFT) +#define GPDMA_CCONFIG_DESTPERIPHERAL(x) \ + ((x) << GPDMA_CCONFIG_DESTPERIPHERAL_SHIFT) + +#define GPDMA_CCONFIG_FLOWCNTRL_SHIFT (11) +#define GPDMA_CCONFIG_FLOWCNTRL_MASK (0x7 << GPDMA_CCONFIG_FLOWCNTRL_SHIFT) +#define GPDMA_CCONFIG_FLOWCNTRL(x) ((x) << GPDMA_CCONFIG_FLOWCNTRL_SHIFT) + +#define GPDMA_CCONFIG_IE_SHIFT (14) +#define GPDMA_CCONFIG_IE_MASK (0x1 << GPDMA_CCONFIG_IE_SHIFT) +#define GPDMA_CCONFIG_IE(x) ((x) << GPDMA_CCONFIG_IE_SHIFT) + +#define GPDMA_CCONFIG_ITC_SHIFT (15) +#define GPDMA_CCONFIG_ITC_MASK (0x1 << GPDMA_CCONFIG_ITC_SHIFT) +#define GPDMA_CCONFIG_ITC(x) ((x) << GPDMA_CCONFIG_ITC_SHIFT) + +#define GPDMA_CCONFIG_L_SHIFT (16) +#define GPDMA_CCONFIG_L_MASK (0x1 << GPDMA_CCONFIG_L_SHIFT) +#define GPDMA_CCONFIG_L(x) ((x) << GPDMA_CCONFIG_L_SHIFT) + +#define GPDMA_CCONFIG_A_SHIFT (17) +#define GPDMA_CCONFIG_A_MASK (0x1 << GPDMA_CCONFIG_A_SHIFT) +#define GPDMA_CCONFIG_A(x) ((x) << GPDMA_CCONFIG_A_SHIFT) + +#define GPDMA_CCONFIG_H_SHIFT (18) +#define GPDMA_CCONFIG_H_MASK (0x1 << GPDMA_CCONFIG_H_SHIFT) +#define GPDMA_CCONFIG_H(x) ((x) << GPDMA_CCONFIG_H_SHIFT) + +/* --- AUTO-GENERATED STUFF FOLLOWS ----------------------------- */ + +/* --- GPDMA_NTSTAT values -------------------------------------- */ + +/* INTSTAT: Status of DMA channel interrupts after masking */ +#define GPDMA_NTSTAT_INTSTAT_SHIFT (0) +#define GPDMA_NTSTAT_INTSTAT_MASK (0xff << GPDMA_NTSTAT_INTSTAT_SHIFT) +#define GPDMA_NTSTAT_INTSTAT(x) ((x) << GPDMA_NTSTAT_INTSTAT_SHIFT) + +/* --- GPDMA_INTTCSTAT values ----------------------------------- */ + +/* INTTCSTAT: Terminal count interrupt request status for DMA channels */ +#define GPDMA_INTTCSTAT_INTTCSTAT_SHIFT (0) +#define GPDMA_INTTCSTAT_INTTCSTAT_MASK (0xff << GPDMA_INTTCSTAT_INTTCSTAT_SHIFT) +#define GPDMA_INTTCSTAT_INTTCSTAT(x) ((x) << GPDMA_INTTCSTAT_INTTCSTAT_SHIFT) + +/* --- GPDMA_INTTCCLEAR values ---------------------------------- */ + +/* INTTCCLEAR: Allows clearing the Terminal count interrupt request (IntTCStat) + for DMA channels */ +#define GPDMA_INTTCCLEAR_INTTCCLEAR_SHIFT (0) +#define GPDMA_INTTCCLEAR_INTTCCLEAR_MASK \ + (0xff << GPDMA_INTTCCLEAR_INTTCCLEAR_SHIFT) +#define GPDMA_INTTCCLEAR_INTTCCLEAR(x) \ + ((x) << GPDMA_INTTCCLEAR_INTTCCLEAR_SHIFT) + +/* --- GPDMA_INTERRSTAT values ---------------------------------- */ + +/* INTERRSTAT: Interrupt error status for DMA channels */ +#define GPDMA_INTERRSTAT_INTERRSTAT_SHIFT (0) +#define GPDMA_INTERRSTAT_INTERRSTAT_MASK \ + (0xff << GPDMA_INTERRSTAT_INTERRSTAT_SHIFT) +#define GPDMA_INTERRSTAT_INTERRSTAT(x) \ + ((x) << GPDMA_INTERRSTAT_INTERRSTAT_SHIFT) + +/* --- GPDMA_INTERRCLR values ----------------------------------- */ + +/* INTERRCLR: Writing a 1 clears the error interrupt request (IntErrStat) + for DMA channels */ +#define GPDMA_INTERRCLR_INTERRCLR_SHIFT (0) +#define GPDMA_INTERRCLR_INTERRCLR_MASK \ + (0xff << GPDMA_INTERRCLR_INTERRCLR_SHIFT) +#define GPDMA_INTERRCLR_INTERRCLR(x) \ + ((x) << GPDMA_INTERRCLR_INTERRCLR_SHIFT) + +/* --- GPDMA_RAWINTTCSTAT values -------------------------------- */ + +/* RAWINTTCSTAT: Status of the terminal count interrupt for DMA channels + prior to masking */ +#define GPDMA_RAWINTTCSTAT_RAWINTTCSTAT_SHIFT (0) +#define GPDMA_RAWINTTCSTAT_RAWINTTCSTAT_MASK \ + (0xff << GPDMA_RAWINTTCSTAT_RAWINTTCSTAT_SHIFT) +#define GPDMA_RAWINTTCSTAT_RAWINTTCSTAT(x) \ + ((x) << GPDMA_RAWINTTCSTAT_RAWINTTCSTAT_SHIFT) + +/* --- GPDMA_RAWINTERRSTAT values ------------------------------- */ + +/* RAWINTERRSTAT: Status of the error interrupt for DMA channels prior to + masking */ +#define GPDMA_RAWINTERRSTAT_RAWINTERRSTAT_SHIFT (0) +#define GPDMA_RAWINTERRSTAT_RAWINTERRSTAT_MASK \ + (0xff << GPDMA_RAWINTERRSTAT_RAWINTERRSTAT_SHIFT) +#define GPDMA_RAWINTERRSTAT_RAWINTERRSTAT(x) \ + ((x) << GPDMA_RAWINTERRSTAT_RAWINTERRSTAT_SHIFT) + +/* --- GPDMA_ENBLDCHNS values ----------------------------------- */ + +/* ENABLEDCHANNELS: Enable status for DMA channels */ +#define GPDMA_ENBLDCHNS_ENABLEDCHANNELS_SHIFT (0) +#define GPDMA_ENBLDCHNS_ENABLEDCHANNELS_MASK \ + (0xff << GPDMA_ENBLDCHNS_ENABLEDCHANNELS_SHIFT) +#define GPDMA_ENBLDCHNS_ENABLEDCHANNELS(x) \ + ((x) << GPDMA_ENBLDCHNS_ENABLEDCHANNELS_SHIFT) + +/* --- GPDMA_SOFTBREQ values ------------------------------------ */ + +/* SOFTBREQ: Software burst request flags for each of 16 possible sources */ +#define GPDMA_SOFTBREQ_SOFTBREQ_SHIFT (0) +#define GPDMA_SOFTBREQ_SOFTBREQ_MASK (0xffff << GPDMA_SOFTBREQ_SOFTBREQ_SHIFT) +#define GPDMA_SOFTBREQ_SOFTBREQ(x) ((x) << GPDMA_SOFTBREQ_SOFTBREQ_SHIFT) + +/* --- GPDMA_SOFTSREQ values ------------------------------------ */ + +/* SOFTSREQ: Software single transfer request flags for each of 16 possible + sources */ +#define GPDMA_SOFTSREQ_SOFTSREQ_SHIFT (0) +#define GPDMA_SOFTSREQ_SOFTSREQ_MASK (0xffff << GPDMA_SOFTSREQ_SOFTSREQ_SHIFT) +#define GPDMA_SOFTSREQ_SOFTSREQ(x) ((x) << GPDMA_SOFTSREQ_SOFTSREQ_SHIFT) + +/* --- GPDMA_SOFTLBREQ values ----------------------------------- */ + +/* SOFTLBREQ: Software last burst request flags for each of 16 possible + sources */ +#define GPDMA_SOFTLBREQ_SOFTLBREQ_SHIFT (0) +#define GPDMA_SOFTLBREQ_SOFTLBREQ_MASK \ + (0xffff << GPDMA_SOFTLBREQ_SOFTLBREQ_SHIFT) +#define GPDMA_SOFTLBREQ_SOFTLBREQ(x) \ + ((x) << GPDMA_SOFTLBREQ_SOFTLBREQ_SHIFT) + +/* --- GPDMA_SOFTLSREQ values ----------------------------------- */ + +/* SOFTLSREQ: Software last single transfer request flags for each of 16 + possible sources */ +#define GPDMA_SOFTLSREQ_SOFTLSREQ_SHIFT (0) +#define GPDMA_SOFTLSREQ_SOFTLSREQ_MASK \ + (0xffff << GPDMA_SOFTLSREQ_SOFTLSREQ_SHIFT) +#define GPDMA_SOFTLSREQ_SOFTLSREQ(x) \ + ((x) << GPDMA_SOFTLSREQ_SOFTLSREQ_SHIFT) + +/* --- GPDMA_CONFIG values -------------------------------------- */ + +/* E: DMA Controller enable */ +#define GPDMA_CONFIG_E_SHIFT (0) +#define GPDMA_CONFIG_E_MASK (0x1 << GPDMA_CONFIG_E_SHIFT) +#define GPDMA_CONFIG_E(x) ((x) << GPDMA_CONFIG_E_SHIFT) + +/* M0: AHB Master 0 endianness configuration */ +#define GPDMA_CONFIG_M0_SHIFT (1) +#define GPDMA_CONFIG_M0_MASK (0x1 << GPDMA_CONFIG_M0_SHIFT) +#define GPDMA_CONFIG_M0(x) ((x) << GPDMA_CONFIG_M0_SHIFT) + +/* M1: AHB Master 1 endianness configuration */ +#define GPDMA_CONFIG_M1_SHIFT (2) +#define GPDMA_CONFIG_M1_MASK (0x1 << GPDMA_CONFIG_M1_SHIFT) +#define GPDMA_CONFIG_M1(x) ((x) << GPDMA_CONFIG_M1_SHIFT) + +/* --- GPDMA_SYNC values ---------------------------------------- */ + +/* DMACSYNC: Controls the synchronization logic for DMA request signals */ +#define GPDMA_SYNC_DMACSYNC_SHIFT (0) +#define GPDMA_SYNC_DMACSYNC_MASK (0xffff << GPDMA_SYNC_DMACSYNC_SHIFT) +#define GPDMA_SYNC_DMACSYNC(x) ((x) << GPDMA_SYNC_DMACSYNC_SHIFT) + +/* --- GPDMA_C[0..7]SRCADDR values ----------------------------------- */ + +/* SRCADDR: DMA source address */ +#define GPDMA_CxSRCADDR_SRCADDR_SHIFT (0) +#define GPDMA_CxSRCADDR_SRCADDR_MASK \ + (0xffffffff << GPDMA_CxSRCADDR_SRCADDR_SHIFT) +#define GPDMA_CxSRCADDR_SRCADDR(x) ((x) << GPDMA_CxSRCADDR_SRCADDR_SHIFT) + +/* --- GPDMA_C[0..7]DESTADDR values ---------------------------------- */ + +/* DESTADDR: DMA source address */ +#define GPDMA_CxDESTADDR_DESTADDR_SHIFT (0) +#define GPDMA_CxDESTADDR_DESTADDR_MASK \ + (0xffffffff << GPDMA_CxDESTADDR_DESTADDR_SHIFT) +#define GPDMA_CxDESTADDR_DESTADDR(x) ((x) << GPDMA_CxDESTADDR_DESTADDR_SHIFT) + +/* --- GPDMA_C[0..7]LLI values --------------------------------------- */ + +/* LM: AHB master select for loading the next LLI */ +#define GPDMA_CxLLI_LM_SHIFT (0) +#define GPDMA_CxLLI_LM_MASK (0x1 << GPDMA_CxLLI_LM_SHIFT) +#define GPDMA_CxLLI_LM(x) ((x) << GPDMA_CxLLI_LM_SHIFT) + +/* LLI: Linked list item */ +#define GPDMA_CxLLI_LLI_SHIFT (2) +#define GPDMA_CxLLI_LLI_MASK (0x3fffffff << GPDMA_CxLLI_LLI_SHIFT) +#define GPDMA_CxLLI_LLI(x) ((x) << GPDMA_CxLLI_LLI_SHIFT) + +/* --- GPDMA_C[0..7]CONTROL values ----------------------------------- */ + +/* TRANSFERSIZE: Transfer size in number of transfers */ +#define GPDMA_CxCONTROL_TRANSFERSIZE_SHIFT (0) +#define GPDMA_CxCONTROL_TRANSFERSIZE_MASK \ + (0xfff << GPDMA_CxCONTROL_TRANSFERSIZE_SHIFT) +#define GPDMA_CxCONTROL_TRANSFERSIZE(x) \ + ((x) << GPDMA_CxCONTROL_TRANSFERSIZE_SHIFT) + +/* SBSIZE: Source burst size */ +#define GPDMA_CxCONTROL_SBSIZE_SHIFT (12) +#define GPDMA_CxCONTROL_SBSIZE_MASK (0x7 << GPDMA_CxCONTROL_SBSIZE_SHIFT) +#define GPDMA_CxCONTROL_SBSIZE(x) ((x) << GPDMA_CxCONTROL_SBSIZE_SHIFT) + +/* DBSIZE: Destination burst size */ +#define GPDMA_CxCONTROL_DBSIZE_SHIFT (15) +#define GPDMA_CxCONTROL_DBSIZE_MASK (0x7 << GPDMA_CxCONTROL_DBSIZE_SHIFT) +#define GPDMA_CxCONTROL_DBSIZE(x) ((x) << GPDMA_CxCONTROL_DBSIZE_SHIFT) + +/* SWIDTH: Source transfer width */ +#define GPDMA_CxCONTROL_SWIDTH_SHIFT (18) +#define GPDMA_CxCONTROL_SWIDTH_MASK (0x7 << GPDMA_CxCONTROL_SWIDTH_SHIFT) +#define GPDMA_CxCONTROL_SWIDTH(x) ((x) << GPDMA_CxCONTROL_SWIDTH_SHIFT) + +/* DWIDTH: Destination transfer width */ +#define GPDMA_CxCONTROL_DWIDTH_SHIFT (21) +#define GPDMA_CxCONTROL_DWIDTH_MASK (0x7 << GPDMA_CxCONTROL_DWIDTH_SHIFT) +#define GPDMA_CxCONTROL_DWIDTH(x) ((x) << GPDMA_CxCONTROL_DWIDTH_SHIFT) + +/* S: Source AHB master select */ +#define GPDMA_CxCONTROL_S_SHIFT (24) +#define GPDMA_CxCONTROL_S_MASK (0x1 << GPDMA_CxCONTROL_S_SHIFT) +#define GPDMA_CxCONTROL_S(x) ((x) << GPDMA_CxCONTROL_S_SHIFT) + +/* D: Destination AHB master select */ +#define GPDMA_CxCONTROL_D_SHIFT (25) +#define GPDMA_CxCONTROL_D_MASK (0x1 << GPDMA_CxCONTROL_D_SHIFT) +#define GPDMA_CxCONTROL_D(x) ((x) << GPDMA_CxCONTROL_D_SHIFT) + +/* SI: Source increment */ +#define GPDMA_CxCONTROL_SI_SHIFT (26) +#define GPDMA_CxCONTROL_SI_MASK (0x1 << GPDMA_CxCONTROL_SI_SHIFT) +#define GPDMA_Cx0CONTROL_SI(x) ((x) << GPDMA_CxCONTROL_SI_SHIFT) + +/* DI: Destination increment */ +#define GPDMA_CxCONTROL_DI_SHIFT (27) +#define GPDMA_CxCONTROL_DI_MASK (0x1 << GPDMA_CxCONTROL_DI_SHIFT) +#define GPDMA_CxCONTROL_DI(x) ((x) << GPDMA_CxCONTROL_DI_SHIFT) + +/* PROT1: This information is provided to the peripheral during a DMA bus + access and indicates that the access is in user mode or privileged mode */ +#define GPDMA_CxCONTROL_PROT1_SHIFT (28) +#define GPDMA_CxCONTROL_PROT1_MASK (0x1 << GPDMA_CxCONTROL_PROT1_SHIFT) +#define GPDMA_CxCONTROL_PROT1(x) ((x) << GPDMA_CxCONTROL_PROT1_SHIFT) + +/* PROT2: This information is provided to the peripheral during a DMA bus + access and indicates to the peripheral that the access is bufferable or not + bufferable */ +#define GPDMA_CxCONTROL_PROT2_SHIFT (29) +#define GPDMA_CxCONTROL_PROT2_MASK (0x1 << GPDMA_CxCONTROL_PROT2_SHIFT) +#define GPDMA_CxCONTROL_PROT2(x) ((x) << GPDMA_CxCONTROL_PROT2_SHIFT) + +/* PROT3: This information is provided to the peripheral during a DMA bus + access and indicates to the peripheral that the access is cacheable or not + cacheable */ +#define GPDMA_CxCONTROL_PROT3_SHIFT (30) +#define GPDMA_CxCONTROL_PROT3_MASK (0x1 << GPDMA_CxCONTROL_PROT3_SHIFT) +#define GPDMA_CxCONTROL_PROT3(x) ((x) << GPDMA_CxCONTROL_PROT3_SHIFT) + +/* I: Terminal count interrupt enable bit */ +#define GPDMA_CxCONTROL_I_SHIFT (31) +#define GPDMA_CxCONTROL_I_MASK (0x1 << GPDMA_CxCONTROL_I_SHIFT) +#define GPDMA_CxCONTROL_I(x) ((x) << GPDMA_CxCONTROL_I_SHIFT) + +/* --- GPDMA_C[0..7]CONFIG values ------------------------------------ */ + +/* E: Channel enable */ +#define GPDMA_CxCONFIG_E_SHIFT (0) +#define GPDMA_CxCONFIG_E_MASK (0x1 << GPDMA_CxCONFIG_E_SHIFT) +#define GPDMA_CxCONFIG_E(x) ((x) << GPDMA_CxCONFIG_E_SHIFT) + +/* SRCPERIPHERAL: Source peripheral */ +#define GPDMA_CxCONFIG_SRCPERIPHERAL_SHIFT (1) +#define GPDMA_CxCONFIG_SRCPERIPHERAL_MASK \ + (0x1f << GPDMA_CxCONFIG_SRCPERIPHERAL_SHIFT) +#define GPDMA_CxCONFIG_SRCPERIPHERAL(x) \ + ((x) << GPDMA_CxCONFIG_SRCPERIPHERAL_SHIFT) + +/* DESTPERIPHERAL: Destination peripheral */ +#define GPDMA_CxCONFIG_DESTPERIPHERAL_SHIFT (6) +#define GPDMA_CxCONFIG_DESTPERIPHERAL_MASK \ + (0x1f << GPDMA_CxCONFIG_DESTPERIPHERAL_SHIFT) +#define GPDMA_CxCONFIG_DESTPERIPHERAL(x) \ + ((x) << GPDMA_CxCONFIG_DESTPERIPHERAL_SHIFT) + +/* FLOWCNTRL: Flow control and transfer type */ +#define GPDMA_CxCONFIG_FLOWCNTRL_SHIFT (11) +#define GPDMA_CxCONFIG_FLOWCNTRL_MASK (0x7 << GPDMA_CxCONFIG_FLOWCNTRL_SHIFT) +#define GPDMA_CxCONFIG_FLOWCNTRL(x) ((x) << GPDMA_CxCONFIG_FLOWCNTRL_SHIFT) + +/* IE: Interrupt error mask */ +#define GPDMA_CxCONFIG_IE_SHIFT (14) +#define GPDMA_CxCONFIG_IE_MASK (0x1 << GPDMA_CxCONFIG_IE_SHIFT) +#define GPDMA_CxCONFIG_IE(x) ((x) << GPDMA_CxCONFIG_IE_SHIFT) + +/* ITC: Terminal count interrupt mask */ +#define GPDMA_CxCONFIG_ITC_SHIFT (15) +#define GPDMA_CxCONFIG_ITC_MASK (0x1 << GPDMA_CxCONFIG_ITC_SHIFT) +#define GPDMA_CxCONFIG_ITC(x) ((x) << GPDMA_CxCONFIG_ITC_SHIFT) + +/* L: Lock */ +#define GPDMA_CxCONFIG_L_SHIFT (16) +#define GPDMA_CxCONFIG_L_MASK (0x1 << GPDMA_CxCONFIG_L_SHIFT) +#define GPDMA_CxCONFIG_L(x) ((x) << GPDMA_CxCONFIG_L_SHIFT) + +/* A: Active */ +#define GPDMA_CxCONFIG_A_SHIFT (17) +#define GPDMA_CxCONFIG_A_MASK (0x1 << GPDMA_CxCONFIG_A_SHIFT) +#define GPDMA_CxCONFIG_A(x) ((x) << GPDMA_CxCONFIG_A_SHIFT) + +/* H: Halt */ +#define GPDMA_CxCONFIG_H_SHIFT (18) +#define GPDMA_CxCONFIG_H_MASK (0x1 << GPDMA_CxCONFIG_H_SHIFT) +#define GPDMA_CxCONFIG_H(x) ((x) << GPDMA_CxCONFIG_H_SHIFT) + +/**@}*/ + +#endif diff --git a/libopencm3/include/libopencm3/lpc43xx/gpio.h b/libopencm3/include/libopencm3/lpc43xx/gpio.h new file mode 100644 index 0000000..6747470 --- /dev/null +++ b/libopencm3/include/libopencm3/lpc43xx/gpio.h @@ -0,0 +1,784 @@ +/** @defgroup gpio_defines General Purpose I/O Defines + +@brief <b>Defined Constants and Types for the LPC43xx General Purpose I/O</b> + +@ingroup LPC43xx_defines + +@version 1.0.0 + +@author @htmlonly © @endhtmlonly 2012 Michael Ossmann <mike@ossmann.com> + +@date 10 March 2013 + +LGPL License Terms @ref lgpl_license + */ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2010 Uwe Hermann <uwe@hermann-uwe.de> + * Copyright (C) 2012 Michael Ossmann <mike@ossmann.com> + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see <http://www.gnu.org/licenses/>. + */ + +#ifndef LPC43XX_GPIO_H +#define LPC43XX_GPIO_H + +/**@{*/ + +#include <libopencm3/cm3/common.h> +#include <libopencm3/lpc43xx/memorymap.h> + +/* --- Convenience macros -------------------------------------------------- */ + +/* GPIO port base addresses (for convenience) */ +#define GPIO0 (GPIO_PORT_BASE + 0x2000) +#define GPIO1 (GPIO_PORT_BASE + 0x2004) +#define GPIO2 (GPIO_PORT_BASE + 0x2008) +#define GPIO3 (GPIO_PORT_BASE + 0x200C) +#define GPIO4 (GPIO_PORT_BASE + 0x2010) +#define GPIO5 (GPIO_PORT_BASE + 0x2014) +#define GPIO6 (GPIO_PORT_BASE + 0x2018) +#define GPIO7 (GPIO_PORT_BASE + 0x201C) + +/* GPIO number definitions (for convenience) */ +#define GPIOPIN0 (1 << 0) +#define GPIOPIN1 (1 << 1) +#define GPIOPIN2 (1 << 2) +#define GPIOPIN3 (1 << 3) +#define GPIOPIN4 (1 << 4) +#define GPIOPIN5 (1 << 5) +#define GPIOPIN6 (1 << 6) +#define GPIOPIN7 (1 << 7) +#define GPIOPIN8 (1 << 8) +#define GPIOPIN9 (1 << 9) +#define GPIOPIN10 (1 << 10) +#define GPIOPIN11 (1 << 11) +#define GPIOPIN12 (1 << 12) +#define GPIOPIN13 (1 << 13) +#define GPIOPIN14 (1 << 14) +#define GPIOPIN15 (1 << 15) +#define GPIOPIN16 (1 << 16) +#define GPIOPIN17 (1 << 17) +#define GPIOPIN18 (1 << 18) +#define GPIOPIN19 (1 << 19) +#define GPIOPIN20 (1 << 20) +#define GPIOPIN21 (1 << 21) +#define GPIOPIN22 (1 << 22) +#define GPIOPIN23 (1 << 23) +#define GPIOPIN24 (1 << 24) +#define GPIOPIN25 (1 << 25) +#define GPIOPIN26 (1 << 26) +#define GPIOPIN27 (1 << 27) +#define GPIOPIN28 (1 << 28) +#define GPIOPIN29 (1 << 29) +#define GPIOPIN30 (1 << 30) +#define GPIOPIN31 (1 << 31) + +/* --- GPIO registers ------------------------------------------------------ */ + +/* GPIO pin interrupts */ + +/* Pin Interrupt Mode register */ +#define GPIO_PIN_INTERRUPT_ISEL MMIO32(GPIO_PIN_INTERRUPT_BASE + 0x000) + +/* Pin interrupt level (rising edge) interrupt enable register */ +#define GPIO_PIN_INTERRUPT_IENR MMIO32(GPIO_PIN_INTERRUPT_BASE + 0x004) + +/* Pin interrupt level (rising edge) interrupt set register */ +#define GPIO_PIN_INTERRUPT_SIENR MMIO32(GPIO_PIN_INTERRUPT_BASE + 0x008) + +/* Pin interrupt level (rising edge interrupt) clear register */ +#define GPIO_PIN_INTERRUPT_CIENR MMIO32(GPIO_PIN_INTERRUPT_BASE + 0x00C) + +/* Pin interrupt active level (falling edge) interrupt enable register */ +#define GPIO_PIN_INTERRUPT_IENF MMIO32(GPIO_PIN_INTERRUPT_BASE + 0x010) + +/* Pin interrupt active level (falling edge) interrupt set register */ +#define GPIO_PIN_INTERRUPT_SIENF MMIO32(GPIO_PIN_INTERRUPT_BASE + 0x014) + +/* Pin interrupt active level (falling edge) interrupt clear register */ +#define GPIO_PIN_INTERRUPT_CIENF MMIO32(GPIO_PIN_INTERRUPT_BASE + 0x018) + +/* Pin interrupt rising edge register */ +#define GPIO_PIN_INTERRUPT_RISE MMIO32(GPIO_PIN_INTERRUPT_BASE + 0x01C) + +/* Pin interrupt falling edge register */ +#define GPIO_PIN_INTERRUPT_FALL MMIO32(GPIO_PIN_INTERRUPT_BASE + 0x020) + +/* Pin interrupt status register */ +#define GPIO_PIN_INTERRUPT_IST MMIO32(GPIO_PIN_INTERRUPT_BASE + 0x024) + +/* GPIO GROUP0 interrupt */ + +/* GPIO grouped interrupt control register */ +#define GPIO_GROUP0_INTERRUPT_CTRL \ + MMIO32(GPIO_GROUP0_INTERRUPT_BASE + 0x000) + +/* GPIO grouped interrupt port [0..7] polarity register */ +#define GPIO_GROUP0_INTERRUPT_PORT_POL(x) \ + MMIO32(GPIO_GROUP0_INTERRUPT_BASE + 0x020 + ((x)*4)) + +/* GPIO grouped interrupt port [0..7] enable register */ +#define GPIO_GROUP0_INTERRUPT_PORT_ENA(x) \ + MMIO32(GPIO_GROUP0_INTERRUPT_BASE + 0x040 + ((x)*4)) + +/* GPIO GROUP1 interrupt */ + +/* GPIO grouped interrupt control register */ +#define GPIO_GROUP1_INTERRUPT_CTRL \ + MMIO32(GPIO_GROUP1_INTERRUPT_BASE + 0x000) + +/* GPIO grouped interrupt port [0..7] polarity register */ +#define GPIO_GROUP1_INTERRUPT_PORT_POL(x) \ + MMIO32(GPIO_GROUP1_INTERRUPT_BASE + 0x020 + ((x)*4)) + +/* GPIO grouped interrupt port [0..7] enable register */ +#define GPIO_GROUP1_INTERRUPT_PORT_ENA(x) \ + MMIO32(GPIO_GROUP1_INTERRUPT_BASE + 0x040 + ((x)*4)) + +/* Byte pin registers port 0; pins PIO0_0 to PIO0_31 (R/W) */ +#define GPIO_B0 (GPIO_PORT_BASE + 0x0000) +#define GPIO_B1 (GPIO_PORT_BASE + 0x0001) +#define GPIO_B2 (GPIO_PORT_BASE + 0x0002) +#define GPIO_B3 (GPIO_PORT_BASE + 0x0003) +#define GPIO_B4 (GPIO_PORT_BASE + 0x0004) +#define GPIO_B5 (GPIO_PORT_BASE + 0x0005) +#define GPIO_B6 (GPIO_PORT_BASE + 0x0006) +#define GPIO_B7 (GPIO_PORT_BASE + 0x0007) +#define GPIO_B8 (GPIO_PORT_BASE + 0x0008) +#define GPIO_B9 (GPIO_PORT_BASE + 0x0009) +#define GPIO_B10 (GPIO_PORT_BASE + 0x000A) +#define GPIO_B11 (GPIO_PORT_BASE + 0x000B) +#define GPIO_B12 (GPIO_PORT_BASE + 0x000C) +#define GPIO_B13 (GPIO_PORT_BASE + 0x000D) +#define GPIO_B14 (GPIO_PORT_BASE + 0x000E) +#define GPIO_B15 (GPIO_PORT_BASE + 0x000F) +#define GPIO_B16 (GPIO_PORT_BASE + 0x0010) +#define GPIO_B17 (GPIO_PORT_BASE + 0x0011) +#define GPIO_B18 (GPIO_PORT_BASE + 0x0012) +#define GPIO_B19 (GPIO_PORT_BASE + 0x0013) +#define GPIO_B20 (GPIO_PORT_BASE + 0x0014) +#define GPIO_B21 (GPIO_PORT_BASE + 0x0015) +#define GPIO_B22 (GPIO_PORT_BASE + 0x0016) +#define GPIO_B23 (GPIO_PORT_BASE + 0x0017) +#define GPIO_B24 (GPIO_PORT_BASE + 0x0018) +#define GPIO_B25 (GPIO_PORT_BASE + 0x0019) +#define GPIO_B26 (GPIO_PORT_BASE + 0x001A) +#define GPIO_B27 (GPIO_PORT_BASE + 0x001B) +#define GPIO_B28 (GPIO_PORT_BASE + 0x001C) +#define GPIO_B29 (GPIO_PORT_BASE + 0x001D) +#define GPIO_B30 (GPIO_PORT_BASE + 0x001E) +#define GPIO_B31 (GPIO_PORT_BASE + 0x001F) + +/* Byte pin registers port 1 (R/W) */ +#define GPIO_B32 (GPIO_PORT_BASE + 0x0020) +#define GPIO_B33 (GPIO_PORT_BASE + 0x0021) +#define GPIO_B34 (GPIO_PORT_BASE + 0x0022) +#define GPIO_B35 (GPIO_PORT_BASE + 0x0023) +#define GPIO_B36 (GPIO_PORT_BASE + 0x0024) +#define GPIO_B37 (GPIO_PORT_BASE + 0x0025) +#define GPIO_B38 (GPIO_PORT_BASE + 0x0026) +#define GPIO_B39 (GPIO_PORT_BASE + 0x0027) +#define GPIO_B40 (GPIO_PORT_BASE + 0x0028) +#define GPIO_B41 (GPIO_PORT_BASE + 0x0029) +#define GPIO_B42 (GPIO_PORT_BASE + 0x002A) +#define GPIO_B43 (GPIO_PORT_BASE + 0x002B) +#define GPIO_B44 (GPIO_PORT_BASE + 0x002C) +#define GPIO_B45 (GPIO_PORT_BASE + 0x002D) +#define GPIO_B46 (GPIO_PORT_BASE + 0x002E) +#define GPIO_B47 (GPIO_PORT_BASE + 0x002F) +#define GPIO_B48 (GPIO_PORT_BASE + 0x0030) +#define GPIO_B49 (GPIO_PORT_BASE + 0x0031) +#define GPIO_B50 (GPIO_PORT_BASE + 0x0032) +#define GPIO_B51 (GPIO_PORT_BASE + 0x0033) +#define GPIO_B52 (GPIO_PORT_BASE + 0x0034) +#define GPIO_B53 (GPIO_PORT_BASE + 0x0035) +#define GPIO_B54 (GPIO_PORT_BASE + 0x0036) +#define GPIO_B55 (GPIO_PORT_BASE + 0x0037) +#define GPIO_B56 (GPIO_PORT_BASE + 0x0038) +#define GPIO_B57 (GPIO_PORT_BASE + 0x0039) +#define GPIO_B58 (GPIO_PORT_BASE + 0x003A) +#define GPIO_B59 (GPIO_PORT_BASE + 0x003B) +#define GPIO_B60 (GPIO_PORT_BASE + 0x003C) +#define GPIO_B61 (GPIO_PORT_BASE + 0x003D) +#define GPIO_B62 (GPIO_PORT_BASE + 0x003E) +#define GPIO_B63 (GPIO_PORT_BASE + 0x003F) + +/* Byte pin registers port 2 (R/W) */ +#define GPIO_B64 (GPIO_PORT_BASE + 0x0040) +#define GPIO_B65 (GPIO_PORT_BASE + 0x0041) +#define GPIO_B66 (GPIO_PORT_BASE + 0x0042) +#define GPIO_B67 (GPIO_PORT_BASE + 0x0043) +#define GPIO_B68 (GPIO_PORT_BASE + 0x0044) +#define GPIO_B69 (GPIO_PORT_BASE + 0x0045) +#define GPIO_B70 (GPIO_PORT_BASE + 0x0046) +#define GPIO_B71 (GPIO_PORT_BASE + 0x0047) +#define GPIO_B72 (GPIO_PORT_BASE + 0x0048) +#define GPIO_B73 (GPIO_PORT_BASE + 0x0049) +#define GPIO_B74 (GPIO_PORT_BASE + 0x004A) +#define GPIO_B75 (GPIO_PORT_BASE + 0x004B) +#define GPIO_B76 (GPIO_PORT_BASE + 0x004C) +#define GPIO_B77 (GPIO_PORT_BASE + 0x004D) +#define GPIO_B78 (GPIO_PORT_BASE + 0x004E) +#define GPIO_B79 (GPIO_PORT_BASE + 0x004F) +#define GPIO_B80 (GPIO_PORT_BASE + 0x0050) +#define GPIO_B81 (GPIO_PORT_BASE + 0x0051) +#define GPIO_B82 (GPIO_PORT_BASE + 0x0052) +#define GPIO_B83 (GPIO_PORT_BASE + 0x0053) +#define GPIO_B84 (GPIO_PORT_BASE + 0x0054) +#define GPIO_B85 (GPIO_PORT_BASE + 0x0055) +#define GPIO_B86 (GPIO_PORT_BASE + 0x0056) +#define GPIO_B87 (GPIO_PORT_BASE + 0x0057) +#define GPIO_B88 (GPIO_PORT_BASE + 0x0058) +#define GPIO_B89 (GPIO_PORT_BASE + 0x0059) +#define GPIO_B90 (GPIO_PORT_BASE + 0x005A) +#define GPIO_B91 (GPIO_PORT_BASE + 0x005B) +#define GPIO_B92 (GPIO_PORT_BASE + 0x005C) +#define GPIO_B93 (GPIO_PORT_BASE + 0x005D) +#define GPIO_B94 (GPIO_PORT_BASE + 0x005E) +#define GPIO_B95 (GPIO_PORT_BASE + 0x005F) + +/* Byte pin registers port 3 (R/W) */ +#define GPIO_B96 (GPIO_PORT_BASE + 0x0060) +#define GPIO_B97 (GPIO_PORT_BASE + 0x0061) +#define GPIO_B98 (GPIO_PORT_BASE + 0x0062) +#define GPIO_B99 (GPIO_PORT_BASE + 0x0063) +#define GPIO_B100 (GPIO_PORT_BASE + 0x0064) +#define GPIO_B101 (GPIO_PORT_BASE + 0x0065) +#define GPIO_B102 (GPIO_PORT_BASE + 0x0066) +#define GPIO_B103 (GPIO_PORT_BASE + 0x0067) +#define GPIO_B104 (GPIO_PORT_BASE + 0x0068) +#define GPIO_B105 (GPIO_PORT_BASE + 0x0069) +#define GPIO_B106 (GPIO_PORT_BASE + 0x006A) +#define GPIO_B107 (GPIO_PORT_BASE + 0x006B) +#define GPIO_B108 (GPIO_PORT_BASE + 0x006C) +#define GPIO_B109 (GPIO_PORT_BASE + 0x006D) +#define GPIO_B110 (GPIO_PORT_BASE + 0x006E) +#define GPIO_B111 (GPIO_PORT_BASE + 0x006F) +#define GPIO_B112 (GPIO_PORT_BASE + 0x0070) +#define GPIO_B113 (GPIO_PORT_BASE + 0x0071) +#define GPIO_B114 (GPIO_PORT_BASE + 0x0072) +#define GPIO_B115 (GPIO_PORT_BASE + 0x0073) +#define GPIO_B116 (GPIO_PORT_BASE + 0x0074) +#define GPIO_B117 (GPIO_PORT_BASE + 0x0075) +#define GPIO_B118 (GPIO_PORT_BASE + 0x0076) +#define GPIO_B119 (GPIO_PORT_BASE + 0x0077) +#define GPIO_B120 (GPIO_PORT_BASE + 0x0078) +#define GPIO_B121 (GPIO_PORT_BASE + 0x0079) +#define GPIO_B122 (GPIO_PORT_BASE + 0x007A) +#define GPIO_B123 (GPIO_PORT_BASE + 0x007B) +#define GPIO_B124 (GPIO_PORT_BASE + 0x007C) +#define GPIO_B125 (GPIO_PORT_BASE + 0x007D) +#define GPIO_B126 (GPIO_PORT_BASE + 0x007E) +#define GPIO_B127 (GPIO_PORT_BASE + 0x007F) + +/* Byte pin registers port 4 (R/W) */ +#define GPIO_B128 (GPIO_PORT_BASE + 0x0080) +#define GPIO_B129 (GPIO_PORT_BASE + 0x0081) +#define GPIO_B130 (GPIO_PORT_BASE + 0x0082) +#define GPIO_B131 (GPIO_PORT_BASE + 0x0083) +#define GPIO_B132 (GPIO_PORT_BASE + 0x0084) +#define GPIO_B133 (GPIO_PORT_BASE + 0x0085) +#define GPIO_B134 (GPIO_PORT_BASE + 0x0086) +#define GPIO_B135 (GPIO_PORT_BASE + 0x0087) +#define GPIO_B136 (GPIO_PORT_BASE + 0x0088) +#define GPIO_B137 (GPIO_PORT_BASE + 0x0089) +#define GPIO_B138 (GPIO_PORT_BASE + 0x008A) +#define GPIO_B139 (GPIO_PORT_BASE + 0x008B) +#define GPIO_B140 (GPIO_PORT_BASE + 0x008C) +#define GPIO_B141 (GPIO_PORT_BASE + 0x008D) +#define GPIO_B142 (GPIO_PORT_BASE + 0x008E) +#define GPIO_B143 (GPIO_PORT_BASE + 0x008F) +#define GPIO_B144 (GPIO_PORT_BASE + 0x0090) +#define GPIO_B145 (GPIO_PORT_BASE + 0x0091) +#define GPIO_B146 (GPIO_PORT_BASE + 0x0092) +#define GPIO_B147 (GPIO_PORT_BASE + 0x0093) +#define GPIO_B148 (GPIO_PORT_BASE + 0x0094) +#define GPIO_B149 (GPIO_PORT_BASE + 0x0095) +#define GPIO_B150 (GPIO_PORT_BASE + 0x0096) +#define GPIO_B151 (GPIO_PORT_BASE + 0x0097) +#define GPIO_B152 (GPIO_PORT_BASE + 0x0098) +#define GPIO_B153 (GPIO_PORT_BASE + 0x0099) +#define GPIO_B154 (GPIO_PORT_BASE + 0x009A) +#define GPIO_B155 (GPIO_PORT_BASE + 0x009B) +#define GPIO_B156 (GPIO_PORT_BASE + 0x009C) +#define GPIO_B157 (GPIO_PORT_BASE + 0x009D) +#define GPIO_B158 (GPIO_PORT_BASE + 0x009E) +#define GPIO_B159 (GPIO_PORT_BASE + 0x009F) + +/* Byte pin registers port 5 (R/W) */ +#define GPIO_B160 (GPIO_PORT_BASE + 0x00A0) +#define GPIO_B161 (GPIO_PORT_BASE + 0x00A1) +#define GPIO_B162 (GPIO_PORT_BASE + 0x00A2) +#define GPIO_B163 (GPIO_PORT_BASE + 0x00A3) +#define GPIO_B164 (GPIO_PORT_BASE + 0x00A4) +#define GPIO_B165 (GPIO_PORT_BASE + 0x00A5) +#define GPIO_B166 (GPIO_PORT_BASE + 0x00A6) +#define GPIO_B167 (GPIO_PORT_BASE + 0x00A7) +#define GPIO_B168 (GPIO_PORT_BASE + 0x00A8) +#define GPIO_B169 (GPIO_PORT_BASE + 0x00A9) +#define GPIO_B170 (GPIO_PORT_BASE + 0x00AA) +#define GPIO_B171 (GPIO_PORT_BASE + 0x00AB) +#define GPIO_B172 (GPIO_PORT_BASE + 0x00AC) +#define GPIO_B173 (GPIO_PORT_BASE + 0x00AD) +#define GPIO_B174 (GPIO_PORT_BASE + 0x00AE) +#define GPIO_B175 (GPIO_PORT_BASE + 0x00AF) +#define GPIO_B176 (GPIO_PORT_BASE + 0x00B0) +#define GPIO_B177 (GPIO_PORT_BASE + 0x00B1) +#define GPIO_B178 (GPIO_PORT_BASE + 0x00B2) +#define GPIO_B179 (GPIO_PORT_BASE + 0x00B3) +#define GPIO_B180 (GPIO_PORT_BASE + 0x00B4) +#define GPIO_B181 (GPIO_PORT_BASE + 0x00B5) +#define GPIO_B182 (GPIO_PORT_BASE + 0x00B6) +#define GPIO_B183 (GPIO_PORT_BASE + 0x00B7) +#define GPIO_B184 (GPIO_PORT_BASE + 0x00B8) +#define GPIO_B185 (GPIO_PORT_BASE + 0x00B9) +#define GPIO_B186 (GPIO_PORT_BASE + 0x00BA) +#define GPIO_B187 (GPIO_PORT_BASE + 0x00BB) +#define GPIO_B188 (GPIO_PORT_BASE + 0x00BC) +#define GPIO_B189 (GPIO_PORT_BASE + 0x00BD) +#define GPIO_B190 (GPIO_PORT_BASE + 0x00BE) +#define GPIO_B191 (GPIO_PORT_BASE + 0x00BF) + +/* Byte pin registers port 6 (R/W) */ +#define GPIO_B192 (GPIO_PORT_BASE + 0x00C0) +#define GPIO_B193 (GPIO_PORT_BASE + 0x00C1) +#define GPIO_B194 (GPIO_PORT_BASE + 0x00C2) +#define GPIO_B195 (GPIO_PORT_BASE + 0x00C3) +#define GPIO_B196 (GPIO_PORT_BASE + 0x00C4) +#define GPIO_B197 (GPIO_PORT_BASE + 0x00C5) +#define GPIO_B198 (GPIO_PORT_BASE + 0x00C6) +#define GPIO_B199 (GPIO_PORT_BASE + 0x00C7) +#define GPIO_B200 (GPIO_PORT_BASE + 0x00C8) +#define GPIO_B201 (GPIO_PORT_BASE + 0x00C9) +#define GPIO_B202 (GPIO_PORT_BASE + 0x00CA) +#define GPIO_B203 (GPIO_PORT_BASE + 0x00CB) +#define GPIO_B204 (GPIO_PORT_BASE + 0x00CC) +#define GPIO_B205 (GPIO_PORT_BASE + 0x00CD) +#define GPIO_B206 (GPIO_PORT_BASE + 0x00CE) +#define GPIO_B207 (GPIO_PORT_BASE + 0x00CF) +#define GPIO_B208 (GPIO_PORT_BASE + 0x00D0) +#define GPIO_B209 (GPIO_PORT_BASE + 0x00D1) +#define GPIO_B210 (GPIO_PORT_BASE + 0x00D2) +#define GPIO_B211 (GPIO_PORT_BASE + 0x00D3) +#define GPIO_B212 (GPIO_PORT_BASE + 0x00D4) +#define GPIO_B213 (GPIO_PORT_BASE + 0x00D5) +#define GPIO_B214 (GPIO_PORT_BASE + 0x00D6) +#define GPIO_B215 (GPIO_PORT_BASE + 0x00D7) +#define GPIO_B216 (GPIO_PORT_BASE + 0x00D8) +#define GPIO_B217 (GPIO_PORT_BASE + 0x00D9) +#define GPIO_B218 (GPIO_PORT_BASE + 0x00DA) +#define GPIO_B219 (GPIO_PORT_BASE + 0x00DB) +#define GPIO_B220 (GPIO_PORT_BASE + 0x00DC) +#define GPIO_B221 (GPIO_PORT_BASE + 0x00DD) +#define GPIO_B222 (GPIO_PORT_BASE + 0x00DE) +#define GPIO_B223 (GPIO_PORT_BASE + 0x00DF) + +/* Byte pin registers port 7 (R/W) */ +#define GPIO_B224 (GPIO_PORT_BASE + 0x00E0) +#define GPIO_B225 (GPIO_PORT_BASE + 0x00E1) +#define GPIO_B226 (GPIO_PORT_BASE + 0x00E2) +#define GPIO_B227 (GPIO_PORT_BASE + 0x00E3) +#define GPIO_B228 (GPIO_PORT_BASE + 0x00E4) +#define GPIO_B229 (GPIO_PORT_BASE + 0x00E5) +#define GPIO_B230 (GPIO_PORT_BASE + 0x00E6) +#define GPIO_B231 (GPIO_PORT_BASE + 0x00E7) +#define GPIO_B232 (GPIO_PORT_BASE + 0x00E8) +#define GPIO_B233 (GPIO_PORT_BASE + 0x00E9) +#define GPIO_B234 (GPIO_PORT_BASE + 0x00EA) +#define GPIO_B235 (GPIO_PORT_BASE + 0x00EB) +#define GPIO_B236 (GPIO_PORT_BASE + 0x00EC) +#define GPIO_B237 (GPIO_PORT_BASE + 0x00ED) +#define GPIO_B238 (GPIO_PORT_BASE + 0x00EE) +#define GPIO_B239 (GPIO_PORT_BASE + 0x00EF) +#define GPIO_B240 (GPIO_PORT_BASE + 0x00F0) +#define GPIO_B241 (GPIO_PORT_BASE + 0x00F1) +#define GPIO_B242 (GPIO_PORT_BASE + 0x00F2) +#define GPIO_B243 (GPIO_PORT_BASE + 0x00F3) +#define GPIO_B244 (GPIO_PORT_BASE + 0x00F4) +#define GPIO_B245 (GPIO_PORT_BASE + 0x00F5) +#define GPIO_B246 (GPIO_PORT_BASE + 0x00F6) +#define GPIO_B247 (GPIO_PORT_BASE + 0x00F7) +#define GPIO_B248 (GPIO_PORT_BASE + 0x00F8) +#define GPIO_B249 (GPIO_PORT_BASE + 0x00F9) +#define GPIO_B250 (GPIO_PORT_BASE + 0x00FA) +#define GPIO_B251 (GPIO_PORT_BASE + 0x00FB) +#define GPIO_B252 (GPIO_PORT_BASE + 0x00FC) +#define GPIO_B253 (GPIO_PORT_BASE + 0x00FD) +#define GPIO_B254 (GPIO_PORT_BASE + 0x00FE) +#define GPIO_B255 (GPIO_PORT_BASE + 0x00FF) + +/* Word pin registers port 0 (R/W) */ +#define GPIO_W0 (GPIO_PORT_BASE + 0x1000) +#define GPIO_W1 (GPIO_PORT_BASE + 0x1004) +#define GPIO_W2 (GPIO_PORT_BASE + 0x1008) +#define GPIO_W3 (GPIO_PORT_BASE + 0x100C) +#define GPIO_W4 (GPIO_PORT_BASE + 0x1010) +#define GPIO_W5 (GPIO_PORT_BASE + 0x1014) +#define GPIO_W6 (GPIO_PORT_BASE + 0x1018) +#define GPIO_W7 (GPIO_PORT_BASE + 0x101C) +#define GPIO_W8 (GPIO_PORT_BASE + 0x1020) +#define GPIO_W9 (GPIO_PORT_BASE + 0x1024) +#define GPIO_W10 (GPIO_PORT_BASE + 0x1028) +#define GPIO_W11 (GPIO_PORT_BASE + 0x102C) +#define GPIO_W12 (GPIO_PORT_BASE + 0x1030) +#define GPIO_W13 (GPIO_PORT_BASE + 0x1034) +#define GPIO_W14 (GPIO_PORT_BASE + 0x1038) +#define GPIO_W15 (GPIO_PORT_BASE + 0x103C) +#define GPIO_W16 (GPIO_PORT_BASE + 0x1040) +#define GPIO_W17 (GPIO_PORT_BASE + 0x1044) +#define GPIO_W18 (GPIO_PORT_BASE + 0x1048) +#define GPIO_W19 (GPIO_PORT_BASE + 0x104C) +#define GPIO_W20 (GPIO_PORT_BASE + 0x1050) +#define GPIO_W21 (GPIO_PORT_BASE + 0x1054) +#define GPIO_W22 (GPIO_PORT_BASE + 0x1058) +#define GPIO_W23 (GPIO_PORT_BASE + 0x105C) +#define GPIO_W24 (GPIO_PORT_BASE + 0x1060) +#define GPIO_W25 (GPIO_PORT_BASE + 0x1064) +#define GPIO_W26 (GPIO_PORT_BASE + 0x1068) +#define GPIO_W27 (GPIO_PORT_BASE + 0x106C) +#define GPIO_W28 (GPIO_PORT_BASE + 0x1070) +#define GPIO_W29 (GPIO_PORT_BASE + 0x1074) +#define GPIO_W30 (GPIO_PORT_BASE + 0x1078) +#define GPIO_W31 (GPIO_PORT_BASE + 0x107C) + +/* Word pin registers port 1 (R/W) */ +#define GPIO_W32 (GPIO_PORT_BASE + 0x1080) +#define GPIO_W33 (GPIO_PORT_BASE + 0x1084) +#define GPIO_W34 (GPIO_PORT_BASE + 0x1088) +#define GPIO_W35 (GPIO_PORT_BASE + 0x108C) +#define GPIO_W36 (GPIO_PORT_BASE + 0x1090) +#define GPIO_W37 (GPIO_PORT_BASE + 0x1094) +#define GPIO_W38 (GPIO_PORT_BASE + 0x1098) +#define GPIO_W39 (GPIO_PORT_BASE + 0x109C) +#define GPIO_W40 (GPIO_PORT_BASE + 0x10A0) +#define GPIO_W41 (GPIO_PORT_BASE + 0x10A4) +#define GPIO_W42 (GPIO_PORT_BASE + 0x10A8) +#define GPIO_W43 (GPIO_PORT_BASE + 0x10AC) +#define GPIO_W44 (GPIO_PORT_BASE + 0x10B0) +#define GPIO_W45 (GPIO_PORT_BASE + 0x10B4) +#define GPIO_W46 (GPIO_PORT_BASE + 0x10B8) +#define GPIO_W47 (GPIO_PORT_BASE + 0x10BC) +#define GPIO_W48 (GPIO_PORT_BASE + 0x10C0) +#define GPIO_W49 (GPIO_PORT_BASE + 0x10C4) +#define GPIO_W50 (GPIO_PORT_BASE + 0x10C8) +#define GPIO_W51 (GPIO_PORT_BASE + 0x10CC) +#define GPIO_W52 (GPIO_PORT_BASE + 0x10D0) +#define GPIO_W53 (GPIO_PORT_BASE + 0x10D4) +#define GPIO_W54 (GPIO_PORT_BASE + 0x10D8) +#define GPIO_W55 (GPIO_PORT_BASE + 0x10DC) +#define GPIO_W56 (GPIO_PORT_BASE + 0x10E0) +#define GPIO_W57 (GPIO_PORT_BASE + 0x10E4) +#define GPIO_W58 (GPIO_PORT_BASE + 0x10E8) +#define GPIO_W59 (GPIO_PORT_BASE + 0x10EC) +#define GPIO_W60 (GPIO_PORT_BASE + 0x10F0) +#define GPIO_W61 (GPIO_PORT_BASE + 0x10F4) +#define GPIO_W62 (GPIO_PORT_BASE + 0x10F8) +#define GPIO_W63 (GPIO_PORT_BASE + 0x10FC) + +/* Word pin registers port 2 (R/W) */ +#define GPIO_W64 (GPIO_PORT_BASE + 0x1100) +#define GPIO_W65 (GPIO_PORT_BASE + 0x1104) +#define GPIO_W66 (GPIO_PORT_BASE + 0x1108) +#define GPIO_W67 (GPIO_PORT_BASE + 0x110C) +#define GPIO_W68 (GPIO_PORT_BASE + 0x1110) +#define GPIO_W69 (GPIO_PORT_BASE + 0x1114) +#define GPIO_W70 (GPIO_PORT_BASE + 0x1118) +#define GPIO_W71 (GPIO_PORT_BASE + 0x111C) +#define GPIO_W72 (GPIO_PORT_BASE + 0x1120) +#define GPIO_W73 (GPIO_PORT_BASE + 0x1124) +#define GPIO_W74 (GPIO_PORT_BASE + 0x1128) +#define GPIO_W75 (GPIO_PORT_BASE + 0x112C) +#define GPIO_W76 (GPIO_PORT_BASE + 0x1130) +#define GPIO_W77 (GPIO_PORT_BASE + 0x1134) +#define GPIO_W78 (GPIO_PORT_BASE + 0x1138) +#define GPIO_W79 (GPIO_PORT_BASE + 0x113C) +#define GPIO_W80 (GPIO_PORT_BASE + 0x1140) +#define GPIO_W81 (GPIO_PORT_BASE + 0x1144) +#define GPIO_W82 (GPIO_PORT_BASE + 0x1148) +#define GPIO_W83 (GPIO_PORT_BASE + 0x114C) +#define GPIO_W84 (GPIO_PORT_BASE + 0x1150) +#define GPIO_W85 (GPIO_PORT_BASE + 0x1154) +#define GPIO_W86 (GPIO_PORT_BASE + 0x1158) +#define GPIO_W87 (GPIO_PORT_BASE + 0x115C) +#define GPIO_W88 (GPIO_PORT_BASE + 0x1160) +#define GPIO_W89 (GPIO_PORT_BASE + 0x1164) +#define GPIO_W90 (GPIO_PORT_BASE + 0x1168) +#define GPIO_W91 (GPIO_PORT_BASE + 0x116C) +#define GPIO_W92 (GPIO_PORT_BASE + 0x1170) +#define GPIO_W93 (GPIO_PORT_BASE + 0x1174) +#define GPIO_W94 (GPIO_PORT_BASE + 0x1178) +#define GPIO_W95 (GPIO_PORT_BASE + 0x117C) + +/* Word pin registers port 3 (R/W) */ +#define GPIO_W96 (GPIO_PORT_BASE + 0x1180) +#define GPIO_W97 (GPIO_PORT_BASE + 0x1184) +#define GPIO_W98 (GPIO_PORT_BASE + 0x1188) +#define GPIO_W99 (GPIO_PORT_BASE + 0x118C) +#define GPIO_W100 (GPIO_PORT_BASE + 0x1190) +#define GPIO_W101 (GPIO_PORT_BASE + 0x1194) +#define GPIO_W102 (GPIO_PORT_BASE + 0x1198) +#define GPIO_W103 (GPIO_PORT_BASE + 0x119C) +#define GPIO_W104 (GPIO_PORT_BASE + 0x11A0) +#define GPIO_W105 (GPIO_PORT_BASE + 0x11A4) +#define GPIO_W106 (GPIO_PORT_BASE + 0x11A8) +#define GPIO_W107 (GPIO_PORT_BASE + 0x11AC) +#define GPIO_W108 (GPIO_PORT_BASE + 0x11B0) +#define GPIO_W109 (GPIO_PORT_BASE + 0x11B4) +#define GPIO_W110 (GPIO_PORT_BASE + 0x11B8) +#define GPIO_W111 (GPIO_PORT_BASE + 0x11BC) +#define GPIO_W112 (GPIO_PORT_BASE + 0x11C0) +#define GPIO_W113 (GPIO_PORT_BASE + 0x11C4) +#define GPIO_W114 (GPIO_PORT_BASE + 0x11C8) +#define GPIO_W115 (GPIO_PORT_BASE + 0x11CC) +#define GPIO_W116 (GPIO_PORT_BASE + 0x11D0) +#define GPIO_W117 (GPIO_PORT_BASE + 0x11D4) +#define GPIO_W118 (GPIO_PORT_BASE + 0x11D8) +#define GPIO_W119 (GPIO_PORT_BASE + 0x11DC) +#define GPIO_W120 (GPIO_PORT_BASE + 0x11E0) +#define GPIO_W121 (GPIO_PORT_BASE + 0x11E4) +#define GPIO_W122 (GPIO_PORT_BASE + 0x11E8) +#define GPIO_W123 (GPIO_PORT_BASE + 0x11EC) +#define GPIO_W124 (GPIO_PORT_BASE + 0x11F0) +#define GPIO_W125 (GPIO_PORT_BASE + 0x11F4) +#define GPIO_W126 (GPIO_PORT_BASE + 0x11F8) +#define GPIO_W127 (GPIO_PORT_BASE + 0x11FC) + +/* Word pin registers port 4 (R/W) */ +#define GPIO_W128 (GPIO_PORT_BASE + 0x1200) +#define GPIO_W129 (GPIO_PORT_BASE + 0x1204) +#define GPIO_W130 (GPIO_PORT_BASE + 0x1208) +#define GPIO_W131 (GPIO_PORT_BASE + 0x120C) +#define GPIO_W132 (GPIO_PORT_BASE + 0x1210) +#define GPIO_W133 (GPIO_PORT_BASE + 0x1214) +#define GPIO_W134 (GPIO_PORT_BASE + 0x1218) +#define GPIO_W135 (GPIO_PORT_BASE + 0x121C) +#define GPIO_W136 (GPIO_PORT_BASE + 0x1220) +#define GPIO_W137 (GPIO_PORT_BASE + 0x1224) +#define GPIO_W138 (GPIO_PORT_BASE + 0x1228) +#define GPIO_W139 (GPIO_PORT_BASE + 0x122C) +#define GPIO_W140 (GPIO_PORT_BASE + 0x1230) +#define GPIO_W141 (GPIO_PORT_BASE + 0x1234) +#define GPIO_W142 (GPIO_PORT_BASE + 0x1238) +#define GPIO_W143 (GPIO_PORT_BASE + 0x123C) +#define GPIO_W144 (GPIO_PORT_BASE + 0x1240) +#define GPIO_W145 (GPIO_PORT_BASE + 0x1244) +#define GPIO_W146 (GPIO_PORT_BASE + 0x1248) +#define GPIO_W147 (GPIO_PORT_BASE + 0x124C) +#define GPIO_W148 (GPIO_PORT_BASE + 0x1250) +#define GPIO_W149 (GPIO_PORT_BASE + 0x1254) +#define GPIO_W150 (GPIO_PORT_BASE + 0x1258) +#define GPIO_W151 (GPIO_PORT_BASE + 0x125C) +#define GPIO_W152 (GPIO_PORT_BASE + 0x1260) +#define GPIO_W153 (GPIO_PORT_BASE + 0x1264) +#define GPIO_W154 (GPIO_PORT_BASE + 0x1268) +#define GPIO_W155 (GPIO_PORT_BASE + 0x126C) +#define GPIO_W156 (GPIO_PORT_BASE + 0x1270) +#define GPIO_W157 (GPIO_PORT_BASE + 0x1274) +#define GPIO_W158 (GPIO_PORT_BASE + 0x1278) +#define GPIO_W159 (GPIO_PORT_BASE + 0x127C) + +/* Word pin registers port 5 (R/W) */ +#define GPIO_W160 (GPIO_PORT_BASE + 0x1280) +#define GPIO_W161 (GPIO_PORT_BASE + 0x1284) +#define GPIO_W162 (GPIO_PORT_BASE + 0x1288) +#define GPIO_W163 (GPIO_PORT_BASE + 0x128C) +#define GPIO_W164 (GPIO_PORT_BASE + 0x1290) +#define GPIO_W165 (GPIO_PORT_BASE + 0x1294) +#define GPIO_W166 (GPIO_PORT_BASE + 0x1298) +#define GPIO_W167 (GPIO_PORT_BASE + 0x129C) +#define GPIO_W168 (GPIO_PORT_BASE + 0x12A0) +#define GPIO_W169 (GPIO_PORT_BASE + 0x12A4) +#define GPIO_W170 (GPIO_PORT_BASE + 0x12A8) +#define GPIO_W171 (GPIO_PORT_BASE + 0x12AC) +#define GPIO_W172 (GPIO_PORT_BASE + 0x12B0) +#define GPIO_W173 (GPIO_PORT_BASE + 0x12B4) +#define GPIO_W174 (GPIO_PORT_BASE + 0x12B8) +#define GPIO_W175 (GPIO_PORT_BASE + 0x12BC) +#define GPIO_W176 (GPIO_PORT_BASE + 0x12C0) +#define GPIO_W177 (GPIO_PORT_BASE + 0x12C4) +#define GPIO_W178 (GPIO_PORT_BASE + 0x12C8) +#define GPIO_W179 (GPIO_PORT_BASE + 0x12CC) +#define GPIO_W180 (GPIO_PORT_BASE + 0x12D0) +#define GPIO_W181 (GPIO_PORT_BASE + 0x12D4) +#define GPIO_W182 (GPIO_PORT_BASE + 0x12D8) +#define GPIO_W183 (GPIO_PORT_BASE + 0x12DC) +#define GPIO_W184 (GPIO_PORT_BASE + 0x12E0) +#define GPIO_W185 (GPIO_PORT_BASE + 0x12E4) +#define GPIO_W186 (GPIO_PORT_BASE + 0x12E8) +#define GPIO_W187 (GPIO_PORT_BASE + 0x12EC) +#define GPIO_W188 (GPIO_PORT_BASE + 0x12F0) +#define GPIO_W189 (GPIO_PORT_BASE + 0x12F4) +#define GPIO_W190 (GPIO_PORT_BASE + 0x12F8) +#define GPIO_W191 (GPIO_PORT_BASE + 0x12FC) + +/* Word pin registers port 6 (R/W) */ +#define GPIO_W192 (GPIO_PORT_BASE + 0x1300) +#define GPIO_W193 (GPIO_PORT_BASE + 0x1304) +#define GPIO_W194 (GPIO_PORT_BASE + 0x1308) +#define GPIO_W195 (GPIO_PORT_BASE + 0x130C) +#define GPIO_W196 (GPIO_PORT_BASE + 0x1310) +#define GPIO_W197 (GPIO_PORT_BASE + 0x1314) +#define GPIO_W198 (GPIO_PORT_BASE + 0x1318) +#define GPIO_W199 (GPIO_PORT_BASE + 0x131C) +#define GPIO_W200 (GPIO_PORT_BASE + 0x1320) +#define GPIO_W201 (GPIO_PORT_BASE + 0x1324) +#define GPIO_W202 (GPIO_PORT_BASE + 0x1328) +#define GPIO_W203 (GPIO_PORT_BASE + 0x132C) +#define GPIO_W204 (GPIO_PORT_BASE + 0x1330) +#define GPIO_W205 (GPIO_PORT_BASE + 0x1334) +#define GPIO_W206 (GPIO_PORT_BASE + 0x1338) +#define GPIO_W207 (GPIO_PORT_BASE + 0x133C) +#define GPIO_W208 (GPIO_PORT_BASE + 0x1340) +#define GPIO_W209 (GPIO_PORT_BASE + 0x1344) +#define GPIO_W210 (GPIO_PORT_BASE + 0x1348) +#define GPIO_W211 (GPIO_PORT_BASE + 0x134C) +#define GPIO_W212 (GPIO_PORT_BASE + 0x1350) +#define GPIO_W213 (GPIO_PORT_BASE + 0x1354) +#define GPIO_W214 (GPIO_PORT_BASE + 0x1358) +#define GPIO_W215 (GPIO_PORT_BASE + 0x135C) +#define GPIO_W216 (GPIO_PORT_BASE + 0x1360) +#define GPIO_W217 (GPIO_PORT_BASE + 0x1364) +#define GPIO_W218 (GPIO_PORT_BASE + 0x1368) +#define GPIO_W219 (GPIO_PORT_BASE + 0x136C) +#define GPIO_W220 (GPIO_PORT_BASE + 0x1370) +#define GPIO_W221 (GPIO_PORT_BASE + 0x1374) +#define GPIO_W222 (GPIO_PORT_BASE + 0x1378) +#define GPIO_W223 (GPIO_PORT_BASE + 0x137C) + +/* Word pin registers port 7 (R/W) */ +#define GPIO_W224 (GPIO_PORT_BASE + 0x1380) +#define GPIO_W225 (GPIO_PORT_BASE + 0x1384) +#define GPIO_W226 (GPIO_PORT_BASE + 0x1388) +#define GPIO_W227 (GPIO_PORT_BASE + 0x138C) +#define GPIO_W228 (GPIO_PORT_BASE + 0x1390) +#define GPIO_W229 (GPIO_PORT_BASE + 0x1394) +#define GPIO_W230 (GPIO_PORT_BASE + 0x1398) +#define GPIO_W231 (GPIO_PORT_BASE + 0x139C) +#define GPIO_W232 (GPIO_PORT_BASE + 0x13A0) +#define GPIO_W233 (GPIO_PORT_BASE + 0x13A4) +#define GPIO_W234 (GPIO_PORT_BASE + 0x13A8) +#define GPIO_W235 (GPIO_PORT_BASE + 0x13AC) +#define GPIO_W236 (GPIO_PORT_BASE + 0x13B0) +#define GPIO_W237 (GPIO_PORT_BASE + 0x13B4) +#define GPIO_W238 (GPIO_PORT_BASE + 0x13B8) +#define GPIO_W239 (GPIO_PORT_BASE + 0x13BC) +#define GPIO_W240 (GPIO_PORT_BASE + 0x13C0) +#define GPIO_W241 (GPIO_PORT_BASE + 0x13C4) +#define GPIO_W242 (GPIO_PORT_BASE + 0x13C8) +#define GPIO_W243 (GPIO_PORT_BASE + 0x13CC) +#define GPIO_W244 (GPIO_PORT_BASE + 0x13D0) +#define GPIO_W245 (GPIO_PORT_BASE + 0x13D4) +#define GPIO_W246 (GPIO_PORT_BASE + 0x13D8) +#define GPIO_W247 (GPIO_PORT_BASE + 0x13DC) +#define GPIO_W248 (GPIO_PORT_BASE + 0x13E0) +#define GPIO_W249 (GPIO_PORT_BASE + 0x13E4) +#define GPIO_W250 (GPIO_PORT_BASE + 0x13E8) +#define GPIO_W251 (GPIO_PORT_BASE + 0x13EC) +#define GPIO_W252 (GPIO_PORT_BASE + 0x13F0) +#define GPIO_W253 (GPIO_PORT_BASE + 0x13F4) +#define GPIO_W254 (GPIO_PORT_BASE + 0x13F8) +#define GPIO_W255 (GPIO_PORT_BASE + 0x13FC) + +/* GPIO data direction register (GPIOn_DIR) */ +#define GPIO_DIR(port) MMIO32(port + 0x00) +#define GPIO0_DIR GPIO_DIR(GPIO0) +#define GPIO1_DIR GPIO_DIR(GPIO1) +#define GPIO2_DIR GPIO_DIR(GPIO2) +#define GPIO3_DIR GPIO_DIR(GPIO3) +#define GPIO4_DIR GPIO_DIR(GPIO4) +#define GPIO5_DIR GPIO_DIR(GPIO5) +#define GPIO6_DIR GPIO_DIR(GPIO6) +#define GPIO7_DIR GPIO_DIR(GPIO7) + +/* GPIO fast mask register (GPIOn_MASK) */ +#define GPIO_MASK(port) MMIO32(port + 0x80) +#define GPIO0_MASK GPIO_MASK(GPIO0) +#define GPIO1_MASK GPIO_MASK(GPIO1) +#define GPIO2_MASK GPIO_MASK(GPIO2) +#define GPIO3_MASK GPIO_MASK(GPIO3) +#define GPIO4_MASK GPIO_MASK(GPIO4) +#define GPIO5_MASK GPIO_MASK(GPIO5) +#define GPIO6_MASK GPIO_MASK(GPIO6) +#define GPIO7_MASK GPIO_MASK(GPIO7) + +/* GPIO port pin value register (GPIOn_PIN) */ +#define GPIO_PIN(port) MMIO32(port + 0x100) +#define GPIO0_PIN GPIO_PIN(GPIO0) +#define GPIO1_PIN GPIO_PIN(GPIO1) +#define GPIO2_PIN GPIO_PIN(GPIO2) +#define GPIO3_PIN GPIO_PIN(GPIO3) +#define GPIO4_PIN GPIO_PIN(GPIO4) +#define GPIO5_PIN GPIO_PIN(GPIO5) +#define GPIO6_PIN GPIO_PIN(GPIO6) +#define GPIO7_PIN GPIO_PIN(GPIO7) + +/* GPIO port masked pin value register (GPIOn_MPIN) */ +#define GPIO_MPIN(port) MMIO32(port + 0x180) +#define GPIO0_MPIN GPIO_MPIN(GPIO0) +#define GPIO1_MPIN GPIO_MPIN(GPIO1) +#define GPIO2_MPIN GPIO_MPIN(GPIO2) +#define GPIO3_MPIN GPIO_MPIN(GPIO3) +#define GPIO4_MPIN GPIO_MPIN(GPIO4) +#define GPIO5_MPIN GPIO_MPIN(GPIO5) +#define GPIO6_MPIN GPIO_MPIN(GPIO6) +#define GPIO7_MPIN GPIO_MPIN(GPIO7) + +/* GPIO port output set register (GPIOn_SET) */ +#define GPIO_SET(port) MMIO32(port + 0x200) +#define GPIO0_SET GPIO_SET(GPIO0) +#define GPIO1_SET GPIO_SET(GPIO1) +#define GPIO2_SET GPIO_SET(GPIO2) +#define GPIO3_SET GPIO_SET(GPIO3) +#define GPIO4_SET GPIO_SET(GPIO4) +#define GPIO5_SET GPIO_SET(GPIO5) +#define GPIO6_SET GPIO_SET(GPIO6) +#define GPIO7_SET GPIO_SET(GPIO7) + +/* GPIO port output clear register (GPIOn_CLR) */ +#define GPIO_CLR(port) MMIO32(port + 0x280) +#define GPIO0_CLR GPIO_CLR(GPIO0) +#define GPIO1_CLR GPIO_CLR(GPIO1) +#define GPIO2_CLR GPIO_CLR(GPIO2) +#define GPIO3_CLR GPIO_CLR(GPIO3) +#define GPIO4_CLR GPIO_CLR(GPIO4) +#define GPIO5_CLR GPIO_CLR(GPIO5) +#define GPIO6_CLR GPIO_CLR(GPIO6) +#define GPIO7_CLR GPIO_CLR(GPIO7) + +/* GPIO port toggle register (GPIOn_NOT) */ +#define GPIO_NOT(port) MMIO32(port + 0x300) +#define GPIO0_NOT GPIO_NOT(GPIO0) +#define GPIO1_NOT GPIO_NOT(GPIO1) +#define GPIO2_NOT GPIO_NOT(GPIO2) +#define GPIO3_NOT GPIO_NOT(GPIO3) +#define GPIO4_NOT GPIO_NOT(GPIO4) +#define GPIO5_NOT GPIO_NOT(GPIO5) +#define GPIO6_NOT GPIO_NOT(GPIO6) +#define GPIO7_NOT GPIO_NOT(GPIO7) + +/* TODO interrupts */ + +BEGIN_DECLS + +void gpio_set(uint32_t gpioport, uint32_t gpios); +void gpio_clear(uint32_t gpioport, uint32_t gpios); +void gpio_toggle(uint32_t gpioport, uint32_t gpios); + +END_DECLS + +/**@}*/ + +#endif diff --git a/libopencm3/include/libopencm3/lpc43xx/i2c.h b/libopencm3/include/libopencm3/lpc43xx/i2c.h new file mode 100644 index 0000000..2bab0b0 --- /dev/null +++ b/libopencm3/include/libopencm3/lpc43xx/i2c.h @@ -0,0 +1,164 @@ +/** @defgroup i2c_defines I2C Defines + +@brief <b>Defined Constants and Types for the LPC43xx I2C</b> + +@ingroup LPC43xx_defines + +@version 1.0.0 + +@author @htmlonly © @endhtmlonly 2012 Michael Ossmann <mike@ossmann.com> + +@date 10 March 2013 + +LGPL License Terms @ref lgpl_license + */ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2012 Michael Ossmann <mike@ossmann.com> + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see <http://www.gnu.org/licenses/>. + */ + +#ifndef LPC43XX_I2C_H +#define LPC43XX_I2C_H + +/**@{*/ + +#include <libopencm3/cm3/common.h> +#include <libopencm3/lpc43xx/memorymap.h> + +/* --- Convenience macros -------------------------------------------------- */ + +/* I2C port base addresses (for convenience) */ +#define I2C0 I2C0_BASE +#define I2C1 I2C1_BASE + +/* --- I2C registers ------------------------------------------------------- */ + +/* I2C Control Set Register */ +#define I2C_CONSET(port) MMIO32(port + 0x000) +#define I2C0_CONSET I2C_CONSET(I2C0) +#define I2C1_CONSET I2C_CONSET(I2C1) + +/* I2C Status Register */ +#define I2C_STAT(port) MMIO32(port + 0x004) +#define I2C0_STAT I2C_STAT(I2C0) +#define I2C1_STAT I2C_STAT(I2C1) + +/* I2C Data Register */ +#define I2C_DAT(port) MMIO32(port + 0x008) +#define I2C0_DAT I2C_DAT(I2C0) +#define I2C1_DAT I2C_DAT(I2C1) + +/* I2C Slave Address Register 0 */ +#define I2C_ADR0(port) MMIO32(port + 0x00C) +#define I2C0_ADR0 I2C_ADR0(I2C0) +#define I2C1_ADR0 I2C_ADR0(I2C1) + +/* SCH Duty Cycle Register High Half Word */ +#define I2C_SCLH(port) MMIO32(port + 0x010) +#define I2C0_SCLH I2C_SCLH(I2C0) +#define I2C1_SCLH I2C_SCLH(I2C1) + +/* SCL Duty Cycle Register Low Half Word */ +#define I2C_SCLL(port) MMIO32(port + 0x014) +#define I2C0_SCLL I2C_SCLL(I2C0) +#define I2C1_SCLL I2C_SCLL(I2C1) + +/* I2C Control Clear Register */ +#define I2C_CONCLR(port) MMIO32(port + 0x018) +#define I2C0_CONCLR I2C_CONCLR(I2C0) +#define I2C1_CONCLR I2C_CONCLR(I2C1) + +/* Monitor mode control register */ +#define I2C_MMCTRL(port) MMIO32(port + 0x01C) +#define I2C0_MMCTRL I2C_MMCTRL(I2C0) +#define I2C1_MMCTRL I2C_MMCTRL(I2C1) + +/* I2C Slave Address Register 1 */ +#define I2C_ADR1(port) MMIO32(port + 0x020) +#define I2C0_ADR1 I2C_ADR1(I2C0) +#define I2C1_ADR1 I2C_ADR1(I2C1) + +/* I2C Slave Address Register 2 */ +#define I2C_ADR2(port) MMIO32(port + 0x024) +#define I2C0_ADR2 I2C_ADR2(I2C0) +#define I2C1_ADR2 I2C_ADR2(I2C1) + +/* I2C Slave Address Register 3 */ +#define I2C_ADR3(port) MMIO32(port + 0x028) +#define I2C0_ADR3 I2C_ADR3(I2C0) +#define I2C1_ADR3 I2C_ADR3(I2C1) + +/* Data buffer register */ +#define I2C_DATA_BUFFER(port) MMIO32(port + 0x02C) +#define I2C0_DATA_BUFFER I2C_DATA_BUFFER(I2C0) +#define I2C1_DATA_BUFFER I2C_DATA_BUFFER(I2C1) + +/* I2C Slave address mask register 0 */ +#define I2C_MASK0(port) MMIO32(port + 0x030) +#define I2C0_MASK0 I2C_MASK0(I2C0) +#define I2C1_MASK0 I2C_MASK0(I2C1) + +/* I2C Slave address mask register 1 */ +#define I2C_MASK1(port) MMIO32(port + 0x034) +#define I2C0_MASK1 I2C_MASK1(I2C0) +#define I2C1_MASK1 I2C_MASK1(I2C1) + +/* I2C Slave address mask register 2 */ +#define I2C_MASK2(port) MMIO32(port + 0x038) +#define I2C0_MASK2 I2C_MASK2(I2C0) +#define I2C1_MASK2 I2C_MASK2(I2C1) + +/* I2C Slave address mask register 3 */ +#define I2C_MASK3(port) MMIO32(port + 0x03C) +#define I2C0_MASK3 I2C_MASK3(I2C0) +#define I2C1_MASK3 I2C_MASK3(I2C1) + +/* --- I2Cx_CONCLR values -------------------------------------------------- */ + +#define I2C_CONCLR_AAC (1 << 2) /* Assert acknowledge Clear */ +#define I2C_CONCLR_SIC (1 << 3) /* I2C interrupt Clear */ +#define I2C_CONCLR_STAC (1 << 5) /* START flag Clear */ +#define I2C_CONCLR_I2ENC (1 << 6) /* I2C interface Disable bit */ + +/* --- I2Cx_CONSET values -------------------------------------------------- */ + +#define I2C_CONSET_AA (1 << 2) /* Assert acknowledge flag */ +#define I2C_CONSET_SI (1 << 3) /* I2C interrupt flag */ +#define I2C_CONSET_STO (1 << 4) /* STOP flag */ +#define I2C_CONSET_STA (1 << 5) /* START flag */ +#define I2C_CONSET_I2EN (1 << 6) /* I2C interface enable */ + +/* --- I2C const definitions ----------------------------------------------- */ + +#define I2C_WRITE 0 +#define I2C_READ 1 + +/* --- I2C function prototypes --------------------------------------------- */ + +BEGIN_DECLS + +void i2c0_init(const uint16_t duty_cycle_count); +void i2c0_tx_start(void); +void i2c0_tx_byte(uint8_t byte); +uint8_t i2c0_rx_byte(void); +void i2c0_stop(void); + +END_DECLS + +/**@}*/ + +#endif diff --git a/libopencm3/include/libopencm3/lpc43xx/i2s.h b/libopencm3/include/libopencm3/lpc43xx/i2s.h new file mode 100644 index 0000000..63f7afb --- /dev/null +++ b/libopencm3/include/libopencm3/lpc43xx/i2s.h @@ -0,0 +1,122 @@ +/** @defgroup i2s_defines I2S Defines + +@brief <b>Defined Constants and Types for the LPC43xx I2S</b> + +@ingroup LPC43xx_defines + +@version 1.0.0 + +@author @htmlonly © @endhtmlonly 2012 Michael Ossmann <mike@ossmann.com> + +@date 10 March 2013 + +LGPL License Terms @ref lgpl_license + */ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2012 Michael Ossmann <mike@ossmann.com> + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see <http://www.gnu.org/licenses/>. + */ + +#ifndef LPC43XX_I2S_H +#define LPC43XX_I2S_H + +/**@{*/ + +#include <libopencm3/cm3/common.h> +#include <libopencm3/lpc43xx/memorymap.h> + +/* --- Convenience macros -------------------------------------------------- */ + +/* I2S port base addresses (for convenience) */ +#define I2S0 I2S0_BASE +#define I2S1 I2S1_BASE + +/* --- I2S registers ------------------------------------------------------- */ + +/* I2S Digital Audio Output Register */ +#define I2S_DAO(port) MMIO32(port + 0x000) +#define I2S0_DAO I2S_DAO(I2S0) +#define I2S1_DAO I2S_DAO(I2S1) + +/* I2S Digital Audio Input Register */ +#define I2S_DAI(port) MMIO32(port + 0x004) +#define I2S0_DAI I2S_DAI(I2S0) +#define I2S1_DAI I2S_DAI(I2S1) + +/* I2S Transmit FIFO */ +#define I2S_TXFIFO(port) MMIO32(port + 0x008) +#define I2S0_TXFIFO I2S_TXFIFO(I2S0) +#define I2S1_TXFIFO I2S_TXFIFO(I2S1) + +/* I2S Receive FIFO */ +#define I2S_RXFIFO(port) MMIO32(port + 0x00C) +#define I2S0_RXFIFO I2S_RXFIFO(I2S0) +#define I2S1_RXFIFO I2S_RXFIFO(I2S1) + +/* I2S Status Feedback Register */ +#define I2S_STATE(port) MMIO32(port + 0x010) +#define I2S0_STATE I2S_STATE(I2S0) +#define I2S1_STATE I2S_STATE(I2S1) + +/* I2S DMA Configuration Register 1 */ +#define I2S_DMA1(port) MMIO32(port + 0x014) +#define I2S0_DMA1 I2S_DMA1(I2S0) +#define I2S1_DMA1 I2S_DMA1(I2S1) + +/* I2S DMA Configuration Register 2 */ +#define I2S_DMA2(port) MMIO32(port + 0x018) +#define I2S0_DMA2 I2S_DMA2(I2S0) +#define I2S1_DMA2 I2S_DMA2(I2S1) + +/* I2S Interrupt Request Control Register */ +#define I2S_IRQ(port) MMIO32(port + 0x01C) +#define I2S0_IRQ I2S_IRQ(I2S0) +#define I2S1_IRQ I2S_IRQ(I2S1) + +/* I2S Transmit MCLK divider */ +#define I2S_TXRATE(port) MMIO32(port + 0x020) +#define I2S0_TXRATE I2S_TXRATE(I2S0) +#define I2S1_TXRATE I2S_TXRATE(I2S1) + +/* I2S Receive MCLK divider */ +#define I2S_RXRATE(port) MMIO32(port + 0x024) +#define I2S0_RXRATE I2S_RXRATE(I2S0) +#define I2S1_RXRATE I2S_RXRATE(I2S1) + +/* I2S Transmit bit rate divider */ +#define I2S_TXBITRATE(port) MMIO32(port + 0x028) +#define I2S0_TXBITRATE I2S_TXBITRATE(I2S0) +#define I2S1_TXBITRATE I2S_TXBITRATE(I2S1) + +/* I2S Receive bit rate divider */ +#define I2S_RXBITRATE(port) MMIO32(port + 0x02C) +#define I2S0_RXBITRATE I2S_RXBITRATE(I2S0) +#define I2S1_RXBITRATE I2S_RXBITRATE(I2S1) + +/* I2S Transmit mode control */ +#define I2S_TXMODE(port) MMIO32(port + 0x030) +#define I2S0_TXMODE I2S_TXMODE(I2S0) +#define I2S1_TXMODE I2S_TXMODE(I2S1) + +/* I2S Receive mode control */ +#define I2S_RXMODE(port) MMIO32(port + 0x034) +#define I2S0_RXMODE I2S_RXMODE(I2S0) +#define I2S1_RXMODE I2S_RXMODE(I2S1) + +/**@}*/ + +#endif diff --git a/libopencm3/include/libopencm3/lpc43xx/ipc.h b/libopencm3/include/libopencm3/lpc43xx/ipc.h new file mode 100644 index 0000000..ddd81b8 --- /dev/null +++ b/libopencm3/include/libopencm3/lpc43xx/ipc.h @@ -0,0 +1,30 @@ +/* +* This file is part of the libopencm3 project. +* +* Copyright (C) 2012 Benjamin Vernoux <titanmkd@gmail.com> +* +* This library is free software: you can redistribute it and/or modify +* it under the terms of the GNU Lesser General Public License as published by +* the Free Software Foundation, either version 3 of the License, or +* (at your option) any later version. +* +* This library is distributed in the hope that it will be useful, +* but WITHOUT ANY WARRANTY; without even the implied warranty of +* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +* GNU Lesser General Public License for more details. +* +* You should have received a copy of the GNU Lesser General Public License +* along with this library. If not, see <http://www.gnu.org/licenses/>. +*/ + +#ifndef LPC43XX_IPC_H +#define LPC43XX_IPC_H + +#include <libopencm3/cm3/common.h> +#include <libopencm3/lpc43xx/memorymap.h> + +void ipc_halt_m0(void); + +void ipc_start_m0(uint32_t cm0_baseaddr); + +#endif diff --git a/libopencm3/include/libopencm3/lpc43xx/m0/irq.json b/libopencm3/include/libopencm3/lpc43xx/m0/irq.json new file mode 100644 index 0000000..828c1dd --- /dev/null +++ b/libopencm3/include/libopencm3/lpc43xx/m0/irq.json @@ -0,0 +1,36 @@ +{ + "irqs": { + "0": "rtc", + "1": "m4core", + "2": "dma", + "4": "flasheepromat", + "5": "ethernet", + "6": "sdio", + "7": "lcd", + "8": "usb0", + "9": "usb1", + "10": "sct", + "11": "ritimer_or_wwdt", + "12": "timer0", + "13": "gint1", + "14": "pin_int4", + "15": "timer3", + "16": "mcpwm", + "17": "adc0", + "18": "i2c0_or_irc1", + "19": "sgpio", + "20": "spi_or_dac", + "21": "adc1", + "22": "ssp0_or_ssp1", + "23": "eventrouter", + "24": "usart0", + "25": "uart1", + "26": "usart2_or_c_can1", + "27": "usart3", + "28": "i2s0_or_i2s1", + "29": "c_can0" + }, + "partname_humanreadable": "LPC 43xx series M0 core", + "partname_doxygen": "LPC43xx (M0)", + "includeguard": "LIBOPENCM3_LPC43xx_M0_NVIC_H" +}
\ No newline at end of file diff --git a/libopencm3/include/libopencm3/lpc43xx/m4/irq.json b/libopencm3/include/libopencm3/lpc43xx/m4/irq.json new file mode 100644 index 0000000..376fab1 --- /dev/null +++ b/libopencm3/include/libopencm3/lpc43xx/m4/irq.json @@ -0,0 +1,54 @@ +{ + "irqs": { + "0": "dac", + "1": "m0core", + "2": "dma", + "5": "ethernet", + "6": "sdio", + "7": "lcd", + "8": "usb0", + "9": "usb1", + "10": "sct", + "11": "ritimer", + "12": "timer0", + "13": "timer1", + "14": "timer2", + "15": "timer3", + "16": "mcpwm", + "17": "adc0", + "18": "i2c0", + "19": "i2c1", + "20": "spi", + "21": "adc1", + "22": "ssp0", + "23": "ssp1", + "24": "usart0", + "25": "uart1", + "26": "usart2", + "27": "usart3", + "28": "i2s0", + "29": "i2s1", + "30": "spifi", + "31": "sgpio", + "32": "pin_int0", + "33": "pin_int1", + "34": "pin_int2", + "35": "pin_int3", + "36": "pin_int4", + "37": "pin_int5", + "38": "pin_int6", + "39": "pin_int7", + "40": "gint0", + "41": "gint1", + "42": "eventrouter", + "43": "c_can1", + "46": "atimer", + "47": "rtc", + "49": "wwdt", + "51": "c_can0", + "52": "qei" + }, + "partname_humanreadable": "LPC 43xx series M4 core", + "partname_doxygen": "LPC43xx (M4)", + "includeguard": "LIBOPENCM3_LPC43xx_M4_NVIC_H" +}
\ No newline at end of file diff --git a/libopencm3/include/libopencm3/lpc43xx/memorymap.h b/libopencm3/include/libopencm3/lpc43xx/memorymap.h new file mode 100644 index 0000000..5d2bdc4 --- /dev/null +++ b/libopencm3/include/libopencm3/lpc43xx/memorymap.h @@ -0,0 +1,138 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2010 Uwe Hermann <uwe@hermann-uwe.de> + * Copyright (C) 2012 Michael Ossmann <mike@ossmann.com> + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see <http://www.gnu.org/licenses/>. + */ + +#ifndef LPC43XX_MEMORYMAP_H +#define LPC43XX_MEMORYMAP_H + +#include <libopencm3/cm3/common.h> + +/* --- LPC43XX specific peripheral definitions ----------------------------- */ + +/* Memory map for all busses */ +#define PERIPH_BASE_AHB (0x40000000U) +#define PERIPH_BASE_APB0 (0x40080000U) +#define PERIPH_BASE_APB1 (0x400A0000U) +#define PERIPH_BASE_APB2 (0x400C0000U) +#define PERIPH_BASE_APB3 (0x400E0000U) + +/* Register boundary addresses */ + +/* AHB (0x4000 0000 - 0x4001 2000) */ +#define SCT_BASE (PERIPH_BASE_AHB + 0x00000) +/* PERIPH_BASE_AHB + 0x01000 (0x4000 1000 - 0x4000 1FFF): Reserved */ +#define GPDMA_BASE (PERIPH_BASE_AHB + 0x02000) +#define SPIFI_BASE (PERIPH_BASE_AHB + 0x03000) +#define SDIO_BASE (PERIPH_BASE_AHB + 0x04000) +#define EMC_BASE (PERIPH_BASE_AHB + 0x05000) +#define USB0_BASE (PERIPH_BASE_AHB + 0x06000) +#define USB1_BASE (PERIPH_BASE_AHB + 0x07000) +#define LCD_BASE (PERIPH_BASE_AHB + 0x08000) +/* PERIPH_BASE_AHB + 0x09000 (0x4000 9000 - 0x4000 FFFF): Reserved */ +#define ETHERNET_BASE (PERIPH_BASE_AHB + 0x10000) + +/* 0x4001 2000 - 0x4003 FFFF Reserved */ + +/* RTC domain peripherals */ +#define ATIMER_BASE (0x40040000U) +#define BACKUP_REG_BASE (0x40041000U) +#define PMC_BASE (0x40042000U) +#define CREG_BASE (0x40043000U) +#define EVENTROUTER_BASE (0x40044000U) +#define OTP_BASE (0x40045000U) +#define RTC_BASE (0x40046000U) +/* 0x4004 7000 - 0x4004 FFFF Reserved */ + +/* clocking/reset control peripherals */ +#define CGU_BASE (0x40050000U) +#define CCU1_BASE (0x40051000U) +#define CCU2_BASE (0x40052000U) +#define RGU_BASE (0x40053000U) +/* 0x4005 4000 - 0x4005 FFFF Reserved */ + +/* 0x4006 0000 - 0x4007 FFFF Reserved */ + +/* APB0 ( 0x4008 0000 - 0x4008 FFFF) */ +#define WWDT_BASE (PERIPH_BASE_APB0 + 0x00000) +#define USART0_BASE (PERIPH_BASE_APB0 + 0x01000) +#define UART1_BASE (PERIPH_BASE_APB0 + 0x02000) +#define SSP0_BASE (PERIPH_BASE_APB0 + 0x03000) +#define TIMER0_BASE (PERIPH_BASE_APB0 + 0x04000) +#define TIMER1_BASE (PERIPH_BASE_APB0 + 0x05000) +#define SCU_BASE (PERIPH_BASE_APB0 + 0x06000) +#define GPIO_PIN_INTERRUPT_BASE (PERIPH_BASE_APB0 + 0x07000) +#define GPIO_GROUP0_INTERRUPT_BASE (PERIPH_BASE_APB0 + 0x08000) +#define GPIO_GROUP1_INTERRUPT_BASE (PERIPH_BASE_APB0 + 0x09000) +/* 0x4008 A000 - 0x4008 FFFF Reserved */ + +/* 0x4009 0000 - 0x4009 FFFF Reserved */ + +/* APB1 (0x400A 0000 - 0x400A FFFF) */ +#define MCPWM_BASE (PERIPH_BASE_APB1 + 0x00000) +#define I2C0_BASE (PERIPH_BASE_APB1 + 0x01000) +#define I2S0_BASE (PERIPH_BASE_APB1 + 0x02000) +#define I2S1_BASE (PERIPH_BASE_APB1 + 0x03000) +#define C_CCAN1_BASE (PERIPH_BASE_APB1 + 0x04000) +/* 0x400A 5000 - 0x400A FFFF Reserved */ + +/* 0x400B 0000 - 0x400B FFFF Reserved */ + +/* APB2 (0x400C 0000 - 0x400C FFFF) */ +#define RITIMER_BASE (PERIPH_BASE_APB2 + 0x00000) +#define USART2_BASE (PERIPH_BASE_APB2 + 0x01000) +#define USART3_BASE (PERIPH_BASE_APB2 + 0x02000) +#define TIMER2_BASE (PERIPH_BASE_APB2 + 0x03000) +#define TIMER3_BASE (PERIPH_BASE_APB2 + 0x04000) +#define SSP1_BASE (PERIPH_BASE_APB2 + 0x05000) +#define QEI_BASE (PERIPH_BASE_APB2 + 0x06000) +#define GIMA_BASE (PERIPH_BASE_APB2 + 0x07000) +/* 0x400C 8000 - 0x400C FFFF Reserved */ + +/* 0x400D 0000 - 0x400D FFFF Reserved */ + +/* APB3 (0x400E 0000 - 0x400E FFFF) */ +#define I2C1_BASE (PERIPH_BASE_APB3 + 0x00000) +#define DAC_BASE (PERIPH_BASE_APB3 + 0x01000) +#define C_CAN0_BASE (PERIPH_BASE_APB3 + 0x02000) +#define ADC0_BASE (PERIPH_BASE_APB3 + 0x03000) +#define ADC1_BASE (PERIPH_BASE_APB3 + 0x04000) +/* 0x400E 5000 - 0x400E FFFF Reserved */ + +/* 0x400F 0000 - 0x400F 0FFF Reserved */ + +#define AES_BASE (0x400F1000U) + +/* 0x400F 2000 - 0x400F 3FFF Reserved */ + +#define GPIO_PORT_BASE (0x400F4000U) + +/* 0x400F 8000 - 0x400F FFFF Reserved */ + +#define SPI_PORT_BASE (0x40100000U) +#define SGPIO_PORT_BASE (0x40101000U) + +/* 0x4010 2000 - 0x41FF FFFF Reserved */ + +/* 0x4200 0000 - 0x43FF FFFF peripheral bit band alias region */ + +/* 0x4400 0000 - 0x5FFF FFFF Reserved */ + +/* 0x6000 0000 - 0xFFFF FFFF external memories and ARM private bus */ + +#endif diff --git a/libopencm3/include/libopencm3/lpc43xx/rgu.h b/libopencm3/include/libopencm3/lpc43xx/rgu.h new file mode 100644 index 0000000..0ec0146 --- /dev/null +++ b/libopencm3/include/libopencm3/lpc43xx/rgu.h @@ -0,0 +1,1206 @@ +/** @defgroup rgu_defines Reset Generation Unit Defines + +@brief <b>Defined Constants and Types for the LPC43xx Reset Generation Unit</b> + +@ingroup LPC43xx_defines + +@version 1.0.0 + +@author @htmlonly © @endhtmlonly 2012 Michael Ossmann <mike@ossmann.com> + +@date 10 March 2013 + +LGPL License Terms @ref lgpl_license + */ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2012 Michael Ossmann <mike@ossmann.com> + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see <http://www.gnu.org/licenses/>. + */ + +#ifndef LPC43XX_RGU_H +#define LPC43XX_RGU_H + +/**@{*/ + +#include <libopencm3/cm3/common.h> +#include <libopencm3/lpc43xx/memorymap.h> + +/* --- RGU registers ------------------------------------------------------- */ + +/* Reset control register 0 */ +#define RESET_CTRL0 MMIO32(RGU_BASE + 0x100) + +/* Reset control register 1 */ +#define RESET_CTRL1 MMIO32(RGU_BASE + 0x104) + +/* Reset status register 0 */ +#define RESET_STATUS0 MMIO32(RGU_BASE + 0x110) + +/* Reset status register 1 */ +#define RESET_STATUS1 MMIO32(RGU_BASE + 0x114) + +/* Reset status register 2 */ +#define RESET_STATUS2 MMIO32(RGU_BASE + 0x118) + +/* Reset status register 3 */ +#define RESET_STATUS3 MMIO32(RGU_BASE + 0x11C) + +/* Reset active status register 0 */ +#define RESET_ACTIVE_STATUS0 MMIO32(RGU_BASE + 0x150) + +/* Reset active status register 1 */ +#define RESET_ACTIVE_STATUS1 MMIO32(RGU_BASE + 0x154) + +/* Reset external status register 0 for CORE_RST */ +#define RESET_EXT_STAT0 MMIO32(RGU_BASE + 0x400) + +/* Reset external status register 1 for PERIPH_RST */ +#define RESET_EXT_STAT1 MMIO32(RGU_BASE + 0x404) + +/* Reset external status register 2 for MASTER_RST */ +#define RESET_EXT_STAT2 MMIO32(RGU_BASE + 0x408) + +/* Reserved */ +#define RESET_EXT_STAT3 MMIO32(RGU_BASE + 0x40C) + +/* Reset external status register 4 for WWDT_RST */ +#define RESET_EXT_STAT4 MMIO32(RGU_BASE + 0x410) + +/* Reset external status register 5 for CREG_RST */ +#define RESET_EXT_STAT5 MMIO32(RGU_BASE + 0x414) + +/* Reserved */ +#define RESET_EXT_STAT6 MMIO32(RGU_BASE + 0x418) + +/* Reserved */ +#define RESET_EXT_STAT7 MMIO32(RGU_BASE + 0x41C) + +/* Reset external status register 8 for BUS_RST */ +#define RESET_EXT_STAT8 MMIO32(RGU_BASE + 0x420) + +/* Reset external status register 9 for SCU_RST */ +#define RESET_EXT_STAT9 MMIO32(RGU_BASE + 0x424) + +/* Reserved */ +#define RESET_EXT_STAT10 MMIO32(RGU_BASE + 0x428) + +/* Reserved */ +#define RESET_EXT_STAT11 MMIO32(RGU_BASE + 0x42C) + +/* Reserved */ +#define RESET_EXT_STAT12 MMIO32(RGU_BASE + 0x430) + +/* Reset external status register 13 for M4_RST */ +#define RESET_EXT_STAT13 MMIO32(RGU_BASE + 0x434) + +/* Reserved */ +#define RESET_EXT_STAT14 MMIO32(RGU_BASE + 0x438) + +/* Reserved */ +#define RESET_EXT_STAT15 MMIO32(RGU_BASE + 0x43C) + +/* Reset external status register 16 for LCD_RST */ +#define RESET_EXT_STAT16 MMIO32(RGU_BASE + 0x440) + +/* Reset external status register 17 for USB0_RST */ +#define RESET_EXT_STAT17 MMIO32(RGU_BASE + 0x444) + +/* Reset external status register 18 for USB1_RST */ +#define RESET_EXT_STAT18 MMIO32(RGU_BASE + 0x448) + +/* Reset external status register 19 for DMA_RST */ +#define RESET_EXT_STAT19 MMIO32(RGU_BASE + 0x44C) + +/* Reset external status register 20 for SDIO_RST */ +#define RESET_EXT_STAT20 MMIO32(RGU_BASE + 0x450) + +/* Reset external status register 21 for EMC_RST */ +#define RESET_EXT_STAT21 MMIO32(RGU_BASE + 0x454) + +/* Reset external status register 22 for ETHERNET_RST */ +#define RESET_EXT_STAT22 MMIO32(RGU_BASE + 0x458) + +/* Reserved */ +#define RESET_EXT_STAT23 MMIO32(RGU_BASE + 0x45C) + +/* Reserved */ +#define RESET_EXT_STAT24 MMIO32(RGU_BASE + 0x460) + +/* Reserved */ +#define RESET_EXT_STAT25 MMIO32(RGU_BASE + 0x464) + +/* Reserved */ +#define RESET_EXT_STAT26 MMIO32(RGU_BASE + 0x468) + +/* Reserved */ +#define RESET_EXT_STAT27 MMIO32(RGU_BASE + 0x46C) + +/* Reset external status register 28 for GPIO_RST */ +#define RESET_EXT_STAT28 MMIO32(RGU_BASE + 0x470) + +/* Reserved */ +#define RESET_EXT_STAT29 MMIO32(RGU_BASE + 0x474) + +/* Reserved */ +#define RESET_EXT_STAT30 MMIO32(RGU_BASE + 0x478) + +/* Reserved */ +#define RESET_EXT_STAT31 MMIO32(RGU_BASE + 0x47C) + +/* Reset external status register 32 for TIMER0_RST */ +#define RESET_EXT_STAT32 MMIO32(RGU_BASE + 0x480) + +/* Reset external status register 33 for TIMER1_RST */ +#define RESET_EXT_STAT33 MMIO32(RGU_BASE + 0x484) + +/* Reset external status register 34 for TIMER2_RST */ +#define RESET_EXT_STAT34 MMIO32(RGU_BASE + 0x488) + +/* Reset external status register 35 for TIMER3_RST */ +#define RESET_EXT_STAT35 MMIO32(RGU_BASE + 0x48C) + +/* Reset external status register 36 for RITIMER_RST */ +#define RESET_EXT_STAT36 MMIO32(RGU_BASE + 0x490) + +/* Reset external status register 37 for SCT_RST */ +#define RESET_EXT_STAT37 MMIO32(RGU_BASE + 0x494) + +/* Reset external status register 38 for MOTOCONPWM_RST */ +#define RESET_EXT_STAT38 MMIO32(RGU_BASE + 0x498) + +/* Reset external status register 39 for QEI_RST */ +#define RESET_EXT_STAT39 MMIO32(RGU_BASE + 0x49C) + +/* Reset external status register 40 for ADC0_RST */ +#define RESET_EXT_STAT40 MMIO32(RGU_BASE + 0x4A0) + +/* Reset external status register 41 for ADC1_RST */ +#define RESET_EXT_STAT41 MMIO32(RGU_BASE + 0x4A4) + +/* Reset external status register 42 for DAC_RST */ +#define RESET_EXT_STAT42 MMIO32(RGU_BASE + 0x4A8) + +/* Reserved */ +#define RESET_EXT_STAT43 MMIO32(RGU_BASE + 0x4AC) + +/* Reset external status register 44 for UART0_RST */ +#define RESET_EXT_STAT44 MMIO32(RGU_BASE + 0x4B0) + +/* Reset external status register 45 for UART1_RST */ +#define RESET_EXT_STAT45 MMIO32(RGU_BASE + 0x4B4) + +/* Reset external status register 46 for UART2_RST */ +#define RESET_EXT_STAT46 MMIO32(RGU_BASE + 0x4B8) + +/* Reset external status register 47 for UART3_RST */ +#define RESET_EXT_STAT47 MMIO32(RGU_BASE + 0x4BC) + +/* Reset external status register 48 for I2C0_RST */ +#define RESET_EXT_STAT48 MMIO32(RGU_BASE + 0x4C0) + +/* Reset external status register 49 for I2C1_RST */ +#define RESET_EXT_STAT49 MMIO32(RGU_BASE + 0x4C4) + +/* Reset external status register 50 for SSP0_RST */ +#define RESET_EXT_STAT50 MMIO32(RGU_BASE + 0x4C8) + +/* Reset external status register 51 for SSP1_RST */ +#define RESET_EXT_STAT51 MMIO32(RGU_BASE + 0x4CC) + +/* Reset external status register 52 for I2S_RST */ +#define RESET_EXT_STAT52 MMIO32(RGU_BASE + 0x4D0) + +/* Reset external status register 53 for SPIFI_RST */ +#define RESET_EXT_STAT53 MMIO32(RGU_BASE + 0x4D4) + +/* Reset external status register 54 for CAN1_RST */ +#define RESET_EXT_STAT54 MMIO32(RGU_BASE + 0x4D8) + +/* Reset external status register 55 for CAN0_RST */ +#define RESET_EXT_STAT55 MMIO32(RGU_BASE + 0x4DC) + +/* Reset external status register 56 for M0APP_RST */ +#define RESET_EXT_STAT56 MMIO32(RGU_BASE + 0x4E0) + +/* Reset external status register 57 for SGPIO_RST */ +#define RESET_EXT_STAT57 MMIO32(RGU_BASE + 0x4E4) + +/* Reset external status register 58 for SPI_RST */ +#define RESET_EXT_STAT58 MMIO32(RGU_BASE + 0x4E8) + +/* Reserved */ +#define RESET_EXT_STAT59 MMIO32(RGU_BASE + 0x4EC) + +/* Reserved */ +#define RESET_EXT_STAT60 MMIO32(RGU_BASE + 0x4F0) + +/* Reserved */ +#define RESET_EXT_STAT61 MMIO32(RGU_BASE + 0x4F4) + +/* Reserved */ +#define RESET_EXT_STAT62 MMIO32(RGU_BASE + 0x4F8) + +/* Reserved */ +#define RESET_EXT_STAT63 MMIO32(RGU_BASE + 0x4FC) + +/* --- RESET_CTRL0 values --------------------------------------- */ + +/* CORE_RST: Writing a one activates the reset */ +#define RESET_CTRL0_CORE_RST_SHIFT (0) +#define RESET_CTRL0_CORE_RST (1 << RESET_CTRL0_CORE_RST_SHIFT) + +/* PERIPH_RST: Writing a one activates the reset */ +#define RESET_CTRL0_PERIPH_RST_SHIFT (1) +#define RESET_CTRL0_PERIPH_RST (1 << RESET_CTRL0_PERIPH_RST_SHIFT) + +/* MASTER_RST: Writing a one activates the reset */ +#define RESET_CTRL0_MASTER_RST_SHIFT (2) +#define RESET_CTRL0_MASTER_RST (1 << RESET_CTRL0_MASTER_RST_SHIFT) + +/* WWDT_RST: Writing a one to this bit has no effect */ +#define RESET_CTRL0_WWDT_RST_SHIFT (4) +#define RESET_CTRL0_WWDT_RST (1 << RESET_CTRL0_WWDT_RST_SHIFT) + +/* CREG_RST: Writing a one to this bit has no effect */ +#define RESET_CTRL0_CREG_RST_SHIFT (5) +#define RESET_CTRL0_CREG_RST (1 << RESET_CTRL0_CREG_RST_SHIFT) + +/* BUS_RST: Writing a one activates the reset */ +#define RESET_CTRL0_BUS_RST_SHIFT (8) +#define RESET_CTRL0_BUS_RST (1 << RESET_CTRL0_BUS_RST_SHIFT) + +/* SCU_RST: Writing a one activates the reset */ +#define RESET_CTRL0_SCU_RST_SHIFT (9) +#define RESET_CTRL0_SCU_RST (1 << RESET_CTRL0_SCU_RST_SHIFT) + +/* M4_RST: Writing a one activates the reset */ +#define RESET_CTRL0_M4_RST_SHIFT (13) +#define RESET_CTRL0_M4_RST (1 << RESET_CTRL0_M4_RST_SHIFT) + +/* LCD_RST: Writing a one activates the reset */ +#define RESET_CTRL0_LCD_RST_SHIFT (16) +#define RESET_CTRL0_LCD_RST (1 << RESET_CTRL0_LCD_RST_SHIFT) + +/* USB0_RST: Writing a one activates the reset */ +#define RESET_CTRL0_USB0_RST_SHIFT (17) +#define RESET_CTRL0_USB0_RST (1 << RESET_CTRL0_USB0_RST_SHIFT) + +/* USB1_RST: Writing a one activates the reset */ +#define RESET_CTRL0_USB1_RST_SHIFT (18) +#define RESET_CTRL0_USB1_RST (1 << RESET_CTRL0_USB1_RST_SHIFT) + +/* DMA_RST: Writing a one activates the reset */ +#define RESET_CTRL0_DMA_RST_SHIFT (19) +#define RESET_CTRL0_DMA_RST (1 << RESET_CTRL0_DMA_RST_SHIFT) + +/* SDIO_RST: Writing a one activates the reset */ +#define RESET_CTRL0_SDIO_RST_SHIFT (20) +#define RESET_CTRL0_SDIO_RST (1 << RESET_CTRL0_SDIO_RST_SHIFT) + +/* EMC_RST: Writing a one activates the reset */ +#define RESET_CTRL0_EMC_RST_SHIFT (21) +#define RESET_CTRL0_EMC_RST (1 << RESET_CTRL0_EMC_RST_SHIFT) + +/* ETHERNET_RST: Writing a one activates the reset */ +#define RESET_CTRL0_ETHERNET_RST_SHIFT (22) +#define RESET_CTRL0_ETHERNET_RST (1 << RESET_CTRL0_ETHERNET_RST_SHIFT) + +/* FLASHA_RST: Writing a one activates the reset */ +#define RESET_CTRL0_FLASHA_RST_SHIFT (25) +#define RESET_CTRL0_FLASHA_RST (1 << RESET_CTRL0_FLASHA_RST_SHIFT) + +/* EEPROM_RST: Writing a one activates the reset */ +#define RESET_CTRL0_EEPROM_RST_SHIFT (27) +#define RESET_CTRL0_EEPROM_RST (1 << RESET_CTRL0_EEPROM_RST_SHIFT) + +/* GPIO_RST: Writing a one activates the reset */ +#define RESET_CTRL0_GPIO_RST_SHIFT (28) +#define RESET_CTRL0_GPIO_RST (1 << RESET_CTRL0_GPIO_RST_SHIFT) + +/* FLASHB_RST: Writing a one activates the reset */ +#define RESET_CTRL0_FLASHB_RST_SHIFT (29) +#define RESET_CTRL0_FLASHB_RST (1 << RESET_CTRL0_FLASHB_RST_SHIFT) + +/* --- RESET_CTRL1 values --------------------------------------- */ + +/* TIMER0_RST: Writing a one activates the reset */ +#define RESET_CTRL1_TIMER0_RST_SHIFT (0) +#define RESET_CTRL1_TIMER0_RST (1 << RESET_CTRL1_TIMER0_RST_SHIFT) + +/* TIMER1_RST: Writing a one activates the reset */ +#define RESET_CTRL1_TIMER1_RST_SHIFT (1) +#define RESET_CTRL1_TIMER1_RST (1 << RESET_CTRL1_TIMER1_RST_SHIFT) + +/* TIMER2_RST: Writing a one activates the reset */ +#define RESET_CTRL1_TIMER2_RST_SHIFT (2) +#define RESET_CTRL1_TIMER2_RST (1 << RESET_CTRL1_TIMER2_RST_SHIFT) + +/* TIMER3_RST: Writing a one activates the reset */ +#define RESET_CTRL1_TIMER3_RST_SHIFT (3) +#define RESET_CTRL1_TIMER3_RST (1 << RESET_CTRL1_TIMER3_RST_SHIFT) + +/* RTIMER_RST: Writing a one activates the reset */ +#define RESET_CTRL1_RTIMER_RST_SHIFT (4) +#define RESET_CTRL1_RTIMER_RST (1 << RESET_CTRL1_RTIMER_RST_SHIFT) + +/* SCT_RST: Writing a one activates the reset */ +#define RESET_CTRL1_SCT_RST_SHIFT (5) +#define RESET_CTRL1_SCT_RST (1 << RESET_CTRL1_SCT_RST_SHIFT) + +/* MOTOCONPWM_RST: Writing a one activates the reset */ +#define RESET_CTRL1_MOTOCONPWM_RST_SHIFT (6) +#define RESET_CTRL1_MOTOCONPWM_RST (1 << RESET_CTRL1_MOTOCONPWM_RST_SHIFT) + +/* QEI_RST: Writing a one activates the reset */ +#define RESET_CTRL1_QEI_RST_SHIFT (7) +#define RESET_CTRL1_QEI_RST (1 << RESET_CTRL1_QEI_RST_SHIFT) + +/* ADC0_RST: Writing a one activates the reset */ +#define RESET_CTRL1_ADC0_RST_SHIFT (8) +#define RESET_CTRL1_ADC0_RST (1 << RESET_CTRL1_ADC0_RST_SHIFT) + +/* ADC1_RST: Writing a one activates the reset */ +#define RESET_CTRL1_ADC1_RST_SHIFT (9) +#define RESET_CTRL1_ADC1_RST (1 << RESET_CTRL1_ADC1_RST_SHIFT) + +/* DAC_RST: Writing a one activates the reset */ +#define RESET_CTRL1_DAC_RST_SHIFT (10) +#define RESET_CTRL1_DAC_RST (1 << RESET_CTRL1_DAC_RST_SHIFT) + +/* UART0_RST: Writing a one activates the reset */ +#define RESET_CTRL1_UART0_RST_SHIFT (12) +#define RESET_CTRL1_UART0_RST (1 << RESET_CTRL1_UART0_RST_SHIFT) + +/* UART1_RST: Writing a one activates the reset */ +#define RESET_CTRL1_UART1_RST_SHIFT (13) +#define RESET_CTRL1_UART1_RST (1 << RESET_CTRL1_UART1_RST_SHIFT) + +/* UART2_RST: Writing a one activates the reset */ +#define RESET_CTRL1_UART2_RST_SHIFT (14) +#define RESET_CTRL1_UART2_RST (1 << RESET_CTRL1_UART2_RST_SHIFT) + +/* UART3_RST: Writing a one activates the reset */ +#define RESET_CTRL1_UART3_RST_SHIFT (15) +#define RESET_CTRL1_UART3_RST (1 << RESET_CTRL1_UART3_RST_SHIFT) + +/* I2C0_RST: Writing a one activates the reset */ +#define RESET_CTRL1_I2C0_RST_SHIFT (16) +#define RESET_CTRL1_I2C0_RST (1 << RESET_CTRL1_I2C0_RST_SHIFT) + +/* I2C1_RST: Writing a one activates the reset */ +#define RESET_CTRL1_I2C1_RST_SHIFT (17) +#define RESET_CTRL1_I2C1_RST (1 << RESET_CTRL1_I2C1_RST_SHIFT) + +/* SSP0_RST: Writing a one activates the reset */ +#define RESET_CTRL1_SSP0_RST_SHIFT (18) +#define RESET_CTRL1_SSP0_RST (1 << RESET_CTRL1_SSP0_RST_SHIFT) + +/* SSP1_RST: Writing a one activates the reset */ +#define RESET_CTRL1_SSP1_RST_SHIFT (19) +#define RESET_CTRL1_SSP1_RST (1 << RESET_CTRL1_SSP1_RST_SHIFT) + +/* I2S_RST: Writing a one activates the reset */ +#define RESET_CTRL1_I2S_RST_SHIFT (20) +#define RESET_CTRL1_I2S_RST (1 << RESET_CTRL1_I2S_RST_SHIFT) + +/* SPIFI_RST: Writing a one activates the reset */ +#define RESET_CTRL1_SPIFI_RST_SHIFT (21) +#define RESET_CTRL1_SPIFI_RST (1 << RESET_CTRL1_SPIFI_RST_SHIFT) + +/* CAN1_RST: Writing a one activates the reset */ +#define RESET_CTRL1_CAN1_RST_SHIFT (22) +#define RESET_CTRL1_CAN1_RST (1 << RESET_CTRL1_CAN1_RST_SHIFT) + +/* CAN0_RST: Writing a one activates the reset */ +#define RESET_CTRL1_CAN0_RST_SHIFT (23) +#define RESET_CTRL1_CAN0_RST (1 << RESET_CTRL1_CAN0_RST_SHIFT) + +/* M0APP_RST: Writing a one activates the reset */ +#define RESET_CTRL1_M0APP_RST_SHIFT (24) +#define RESET_CTRL1_M0APP_RST (1 << RESET_CTRL1_M0APP_RST_SHIFT) + +/* SGPIO_RST: Writing a one activates the reset */ +#define RESET_CTRL1_SGPIO_RST_SHIFT (25) +#define RESET_CTRL1_SGPIO_RST (1 << RESET_CTRL1_SGPIO_RST_SHIFT) + +/* SPI_RST: Writing a one activates the reset */ +#define RESET_CTRL1_SPI_RST_SHIFT (26) +#define RESET_CTRL1_SPI_RST (1 << RESET_CTRL1_SPI_RST_SHIFT) + +/* --- RESET_STATUS0 values ------------------------------------- */ + +/* CORE_RST: Status of the CORE_RST reset generator output */ +#define RESET_STATUS0_CORE_RST_SHIFT (0) +#define RESET_STATUS0_CORE_RST_MASK (0x3 << RESET_STATUS0_CORE_RST_SHIFT) +#define RESET_STATUS0_CORE_RST(x) ((x) << RESET_STATUS0_CORE_RST_SHIFT) + +/* PERIPH_RST: Status of the PERIPH_RST reset generator output */ +#define RESET_STATUS0_PERIPH_RST_SHIFT (2) +#define RESET_STATUS0_PERIPH_RST_MASK (0x3 << RESET_STATUS0_PERIPH_RST_SHIFT) +#define RESET_STATUS0_PERIPH_RST(x) ((x) << RESET_STATUS0_PERIPH_RST_SHIFT) + +/* MASTER_RST: Status of the MASTER_RST reset generator output */ +#define RESET_STATUS0_MASTER_RST_SHIFT (4) +#define RESET_STATUS0_MASTER_RST_MASK (0x3 << RESET_STATUS0_MASTER_RST_SHIFT) +#define RESET_STATUS0_MASTER_RST(x) ((x) << RESET_STATUS0_MASTER_RST_SHIFT) + +/* WWDT_RST: Status of the WWDT_RST reset generator output */ +#define RESET_STATUS0_WWDT_RST_SHIFT (8) +#define RESET_STATUS0_WWDT_RST_MASK (0x3 << RESET_STATUS0_WWDT_RST_SHIFT) +#define RESET_STATUS0_WWDT_RST(x) ((x) << RESET_STATUS0_WWDT_RST_SHIFT) + +/* CREG_RST: Status of the CREG_RST reset generator output */ +#define RESET_STATUS0_CREG_RST_SHIFT (10) +#define RESET_STATUS0_CREG_RST_MASK (0x3 << RESET_STATUS0_CREG_RST_SHIFT) +#define RESET_STATUS0_CREG_RST(x) ((x) << RESET_STATUS0_CREG_RST_SHIFT) + +/* BUS_RST: Status of the BUS_RST reset generator output */ +#define RESET_STATUS0_BUS_RST_SHIFT (16) +#define RESET_STATUS0_BUS_RST_MASK (0x3 << RESET_STATUS0_BUS_RST_SHIFT) +#define RESET_STATUS0_BUS_RST(x) ((x) << RESET_STATUS0_BUS_RST_SHIFT) + +/* SCU_RST: Status of the SCU_RST reset generator output */ +#define RESET_STATUS0_SCU_RST_SHIFT (18) +#define RESET_STATUS0_SCU_RST_MASK (0x3 << RESET_STATUS0_SCU_RST_SHIFT) +#define RESET_STATUS0_SCU_RST(x) ((x) << RESET_STATUS0_SCU_RST_SHIFT) + +/* M4_RST: Status of the M4_RST reset generator output */ +#define RESET_STATUS0_M4_RST_SHIFT (26) +#define RESET_STATUS0_M4_RST_MASK (0x3 << RESET_STATUS0_M4_RST_SHIFT) +#define RESET_STATUS0_M4_RST(x) ((x) << RESET_STATUS0_M4_RST_SHIFT) + +/* --- RESET_STATUS1 values ------------------------------------- */ + +/* LCD_RST: Status of the LCD_RST reset generator output */ +#define RESET_STATUS1_LCD_RST_SHIFT (0) +#define RESET_STATUS1_LCD_RST_MASK (0x3 << RESET_STATUS1_LCD_RST_SHIFT) +#define RESET_STATUS1_LCD_RST(x) ((x) << RESET_STATUS1_LCD_RST_SHIFT) + +/* USB0_RST: Status of the USB0_RST reset generator output */ +#define RESET_STATUS1_USB0_RST_SHIFT (2) +#define RESET_STATUS1_USB0_RST_MASK (0x3 << RESET_STATUS1_USB0_RST_SHIFT) +#define RESET_STATUS1_USB0_RST(x) ((x) << RESET_STATUS1_USB0_RST_SHIFT) + +/* USB1_RST: Status of the USB1_RST reset generator output */ +#define RESET_STATUS1_USB1_RST_SHIFT (4) +#define RESET_STATUS1_USB1_RST_MASK (0x3 << RESET_STATUS1_USB1_RST_SHIFT) +#define RESET_STATUS1_USB1_RST(x) ((x) << RESET_STATUS1_USB1_RST_SHIFT) + +/* DMA_RST: Status of the DMA_RST reset generator output */ +#define RESET_STATUS1_DMA_RST_SHIFT (6) +#define RESET_STATUS1_DMA_RST_MASK (0x3 << RESET_STATUS1_DMA_RST_SHIFT) +#define RESET_STATUS1_DMA_RST(x) ((x) << RESET_STATUS1_DMA_RST_SHIFT) + +/* SDIO_RST: Status of the SDIO_RST reset generator output */ +#define RESET_STATUS1_SDIO_RST_SHIFT (8) +#define RESET_STATUS1_SDIO_RST_MASK (0x3 << RESET_STATUS1_SDIO_RST_SHIFT) +#define RESET_STATUS1_SDIO_RST(x) ((x) << RESET_STATUS1_SDIO_RST_SHIFT) + +/* EMC_RST: Status of the EMC_RST reset generator output */ +#define RESET_STATUS1_EMC_RST_SHIFT (10) +#define RESET_STATUS1_EMC_RST_MASK (0x3 << RESET_STATUS1_EMC_RST_SHIFT) +#define RESET_STATUS1_EMC_RST(x) ((x) << RESET_STATUS1_EMC_RST_SHIFT) + +/* ETHERNET_RST: Status of the ETHERNET_RST reset generator output */ +#define RESET_STATUS1_ETHERNET_RST_SHIFT (12) +#define RESET_STATUS1_ETHERNET_RST_MASK \ + (0x3 << RESET_STATUS1_ETHERNET_RST_SHIFT) +#define RESET_STATUS1_ETHERNET_RST(x) ((x) << RESET_STATUS1_ETHERNET_RST_SHIFT) + +/* FLASHA_RST: Status of the FLASHA_RST reset generator output */ +#define RESET_STATUS1_FLASHA_RST_SHIFT (18) +#define RESET_STATUS1_FLASHA_RST_MASK (0x3 << RESET_STATUS1_FLASHA_RST_SHIFT) +#define RESET_STATUS1_FLASHA_RST(x) ((x) << RESET_STATUS1_FLASHA_RST_SHIFT) + +/* EEPROM_RST: Status of the EEPROM_RST reset generator output */ +#define RESET_STATUS1_EEPROM_RST_SHIFT (22) +#define RESET_STATUS1_EEPROM_RST_MASK (0x3 << RESET_STATUS1_EEPROM_RST_SHIFT) +#define RESET_STATUS1_EEPROM_RST(x) ((x) << RESET_STATUS1_EEPROM_RST_SHIFT) + +/* GPIO_RST: Status of the GPIO_RST reset generator output */ +#define RESET_STATUS1_GPIO_RST_SHIFT (24) +#define RESET_STATUS1_GPIO_RST_MASK (0x3 << RESET_STATUS1_GPIO_RST_SHIFT) +#define RESET_STATUS1_GPIO_RST(x) ((x) << RESET_STATUS1_GPIO_RST_SHIFT) + +/* FLASHB_RST: Status of the FLASHB_RST reset generator output */ +#define RESET_STATUS1_FLASHB_RST_SHIFT (26) +#define RESET_STATUS1_FLASHB_RST_MASK (0x3 << RESET_STATUS1_FLASHB_RST_SHIFT) +#define RESET_STATUS1_FLASHB_RST(x) ((x) << RESET_STATUS1_FLASHB_RST_SHIFT) + +/* --- RESET_STATUS2 values ------------------------------------- */ + +/* TIMER0_RST: Status of the TIMER0_RST reset generator output */ +#define RESET_STATUS2_TIMER0_RST_SHIFT (0) +#define RESET_STATUS2_TIMER0_RST_MASK (0x3 << RESET_STATUS2_TIMER0_RST_SHIFT) +#define RESET_STATUS2_TIMER0_RST(x) ((x) << RESET_STATUS2_TIMER0_RST_SHIFT) + +/* TIMER1_RST: Status of the TIMER1_RST reset generator output */ +#define RESET_STATUS2_TIMER1_RST_SHIFT (2) +#define RESET_STATUS2_TIMER1_RST_MASK (0x3 << RESET_STATUS2_TIMER1_RST_SHIFT) +#define RESET_STATUS2_TIMER1_RST(x) ((x) << RESET_STATUS2_TIMER1_RST_SHIFT) + +/* TIMER2_RST: Status of the TIMER2_RST reset generator output */ +#define RESET_STATUS2_TIMER2_RST_SHIFT (4) +#define RESET_STATUS2_TIMER2_RST_MASK (0x3 << RESET_STATUS2_TIMER2_RST_SHIFT) +#define RESET_STATUS2_TIMER2_RST(x) ((x) << RESET_STATUS2_TIMER2_RST_SHIFT) + +/* TIMER3_RST: Status of the TIMER3_RST reset generator output */ +#define RESET_STATUS2_TIMER3_RST_SHIFT (6) +#define RESET_STATUS2_TIMER3_RST_MASK (0x3 << RESET_STATUS2_TIMER3_RST_SHIFT) +#define RESET_STATUS2_TIMER3_RST(x) ((x) << RESET_STATUS2_TIMER3_RST_SHIFT) + +/* RITIMER_RST: Status of the RITIMER_RST reset generator output */ +#define RESET_STATUS2_RITIMER_RST_SHIFT (8) +#define RESET_STATUS2_RITIMER_RST_MASK (0x3 << RESET_STATUS2_RITIMER_RST_SHIFT) +#define RESET_STATUS2_RITIMER_RST(x) ((x) << RESET_STATUS2_RITIMER_RST_SHIFT) + +/* SCT_RST: Status of the SCT_RST reset generator output */ +#define RESET_STATUS2_SCT_RST_SHIFT (10) +#define RESET_STATUS2_SCT_RST_MASK (0x3 << RESET_STATUS2_SCT_RST_SHIFT) +#define RESET_STATUS2_SCT_RST(x) ((x) << RESET_STATUS2_SCT_RST_SHIFT) + +/* MOTOCONPWM_RST: Status of the MOTOCONPWM_RST reset generator output */ +#define RESET_STATUS2_MOTOCONPWM_RST_SHIFT (12) +#define RESET_STATUS2_MOTOCONPWM_RST_MASK \ + (0x3 << RESET_STATUS2_MOTOCONPWM_RST_SHIFT) +#define RESET_STATUS2_MOTOCONPWM_RST(x) \ + ((x) << RESET_STATUS2_MOTOCONPWM_RST_SHIFT) + +/* QEI_RST: Status of the QEI_RST reset generator output */ +#define RESET_STATUS2_QEI_RST_SHIFT (14) +#define RESET_STATUS2_QEI_RST_MASK (0x3 << RESET_STATUS2_QEI_RST_SHIFT) +#define RESET_STATUS2_QEI_RST(x) ((x) << RESET_STATUS2_QEI_RST_SHIFT) + +/* ADC0_RST: Status of the ADC0_RST reset generator output */ +#define RESET_STATUS2_ADC0_RST_SHIFT (16) +#define RESET_STATUS2_ADC0_RST_MASK (0x3 << RESET_STATUS2_ADC0_RST_SHIFT) +#define RESET_STATUS2_ADC0_RST(x) ((x) << RESET_STATUS2_ADC0_RST_SHIFT) + +/* ADC1_RST: Status of the ADC1_RST reset generator output */ +#define RESET_STATUS2_ADC1_RST_SHIFT (18) +#define RESET_STATUS2_ADC1_RST_MASK (0x3 << RESET_STATUS2_ADC1_RST_SHIFT) +#define RESET_STATUS2_ADC1_RST(x) ((x) << RESET_STATUS2_ADC1_RST_SHIFT) + +/* DAC_RST: Status of the DAC_RST reset generator output */ +#define RESET_STATUS2_DAC_RST_SHIFT (20) +#define RESET_STATUS2_DAC_RST_MASK (0x3 << RESET_STATUS2_DAC_RST_SHIFT) +#define RESET_STATUS2_DAC_RST(x) ((x) << RESET_STATUS2_DAC_RST_SHIFT) + +/* UART0_RST: Status of the UART0_RST reset generator output */ +#define RESET_STATUS2_UART0_RST_SHIFT (24) +#define RESET_STATUS2_UART0_RST_MASK (0x3 << RESET_STATUS2_UART0_RST_SHIFT) +#define RESET_STATUS2_UART0_RST(x) ((x) << RESET_STATUS2_UART0_RST_SHIFT) + +/* UART1_RST: Status of the UART1_RST reset generator output */ +#define RESET_STATUS2_UART1_RST_SHIFT (26) +#define RESET_STATUS2_UART1_RST_MASK (0x3 << RESET_STATUS2_UART1_RST_SHIFT) +#define RESET_STATUS2_UART1_RST(x) ((x) << RESET_STATUS2_UART1_RST_SHIFT) + +/* UART2_RST: Status of the UART2_RST reset generator output */ +#define RESET_STATUS2_UART2_RST_SHIFT (28) +#define RESET_STATUS2_UART2_RST_MASK (0x3 << RESET_STATUS2_UART2_RST_SHIFT) +#define RESET_STATUS2_UART2_RST(x) ((x) << RESET_STATUS2_UART2_RST_SHIFT) + +/* UART3_RST: Status of the UART3_RST reset generator output */ +#define RESET_STATUS2_UART3_RST_SHIFT (30) +#define RESET_STATUS2_UART3_RST_MASK (0x3 << RESET_STATUS2_UART3_RST_SHIFT) +#define RESET_STATUS2_UART3_RST(x) ((x) << RESET_STATUS2_UART3_RST_SHIFT) + +/* --- RESET_STATUS3 values ------------------------------------- */ + +/* I2C0_RST: Status of the I2C0_RST reset generator output */ +#define RESET_STATUS3_I2C0_RST_SHIFT (0) +#define RESET_STATUS3_I2C0_RST_MASK (0x3 << RESET_STATUS3_I2C0_RST_SHIFT) +#define RESET_STATUS3_I2C0_RST(x) ((x) << RESET_STATUS3_I2C0_RST_SHIFT) + +/* I2C1_RST: Status of the I2C1_RST reset generator output */ +#define RESET_STATUS3_I2C1_RST_SHIFT (2) +#define RESET_STATUS3_I2C1_RST_MASK (0x3 << RESET_STATUS3_I2C1_RST_SHIFT) +#define RESET_STATUS3_I2C1_RST(x) ((x) << RESET_STATUS3_I2C1_RST_SHIFT) + +/* SSP0_RST: Status of the SSP0_RST reset generator output */ +#define RESET_STATUS3_SSP0_RST_SHIFT (4) +#define RESET_STATUS3_SSP0_RST_MASK (0x3 << RESET_STATUS3_SSP0_RST_SHIFT) +#define RESET_STATUS3_SSP0_RST(x) ((x) << RESET_STATUS3_SSP0_RST_SHIFT) + +/* SSP1_RST: Status of the SSP1_RST reset generator output */ +#define RESET_STATUS3_SSP1_RST_SHIFT (6) +#define RESET_STATUS3_SSP1_RST_MASK (0x3 << RESET_STATUS3_SSP1_RST_SHIFT) +#define RESET_STATUS3_SSP1_RST(x) ((x) << RESET_STATUS3_SSP1_RST_SHIFT) + +/* I2S_RST: Status of the I2S_RST reset generator output */ +#define RESET_STATUS3_I2S_RST_SHIFT (8) +#define RESET_STATUS3_I2S_RST_MASK (0x3 << RESET_STATUS3_I2S_RST_SHIFT) +#define RESET_STATUS3_I2S_RST(x) ((x) << RESET_STATUS3_I2S_RST_SHIFT) + +/* SPIFI_RST: Status of the SPIFI_RST reset generator output */ +#define RESET_STATUS3_SPIFI_RST_SHIFT (10) +#define RESET_STATUS3_SPIFI_RST_MASK (0x3 << RESET_STATUS3_SPIFI_RST_SHIFT) +#define RESET_STATUS3_SPIFI_RST(x) ((x) << RESET_STATUS3_SPIFI_RST_SHIFT) + +/* CAN1_RST: Status of the CAN1_RST reset generator output */ +#define RESET_STATUS3_CAN1_RST_SHIFT (12) +#define RESET_STATUS3_CAN1_RST_MASK (0x3 << RESET_STATUS3_CAN1_RST_SHIFT) +#define RESET_STATUS3_CAN1_RST(x) ((x) << RESET_STATUS3_CAN1_RST_SHIFT) + +/* CAN0_RST: Status of the CAN0_RST reset generator output */ +#define RESET_STATUS3_CAN0_RST_SHIFT (14) +#define RESET_STATUS3_CAN0_RST_MASK (0x3 << RESET_STATUS3_CAN0_RST_SHIFT) +#define RESET_STATUS3_CAN0_RST(x) ((x) << RESET_STATUS3_CAN0_RST_SHIFT) + +/* M0APP_RST: Status of the M0APP_RST reset generator output */ +#define RESET_STATUS3_M0APP_RST_SHIFT (16) +#define RESET_STATUS3_M0APP_RST_MASK (0x3 << RESET_STATUS3_M0APP_RST_SHIFT) +#define RESET_STATUS3_M0APP_RST(x) ((x) << RESET_STATUS3_M0APP_RST_SHIFT) + +/* SGPIO_RST: Status of the SGPIO_RST reset generator output */ +#define RESET_STATUS3_SGPIO_RST_SHIFT (18) +#define RESET_STATUS3_SGPIO_RST_MASK (0x3 << RESET_STATUS3_SGPIO_RST_SHIFT) +#define RESET_STATUS3_SGPIO_RST(x) ((x) << RESET_STATUS3_SGPIO_RST_SHIFT) + +/* SPI_RST: Status of the SPI_RST reset generator output */ +#define RESET_STATUS3_SPI_RST_SHIFT (20) +#define RESET_STATUS3_SPI_RST_MASK (0x3 << RESET_STATUS3_SPI_RST_SHIFT) +#define RESET_STATUS3_SPI_RST(x) ((x) << RESET_STATUS3_SPI_RST_SHIFT) + +/* --- RESET_ACTIVE_STATUS0 values ------------------------------ */ + +/* CORE_RST: Current status of the CORE_RST */ +#define RESET_ACTIVE_STATUS0_CORE_RST_SHIFT (0) +#define RESET_ACTIVE_STATUS0_CORE_RST (1 << RESET_ACTIVE_STATUS0_CORE_RST_SHIFT) + +/* PERIPH_RST: Current status of the PERIPH_RST */ +#define RESET_ACTIVE_STATUS0_PERIPH_RST_SHIFT (1) +#define RESET_ACTIVE_STATUS0_PERIPH_RST \ + (1 << RESET_ACTIVE_STATUS0_PERIPH_RST_SHIFT) + +/* MASTER_RST: Current status of the MASTER_RST */ +#define RESET_ACTIVE_STATUS0_MASTER_RST_SHIFT (2) +#define RESET_ACTIVE_STATUS0_MASTER_RST \ + (1 << RESET_ACTIVE_STATUS0_MASTER_RST_SHIFT) + +/* WWDT_RST: Current status of the WWDT_RST */ +#define RESET_ACTIVE_STATUS0_WWDT_RST_SHIFT (4) +#define RESET_ACTIVE_STATUS0_WWDT_RST (1 << RESET_ACTIVE_STATUS0_WWDT_RST_SHIFT) + +/* CREG_RST: Current status of the CREG_RST */ +#define RESET_ACTIVE_STATUS0_CREG_RST_SHIFT (5) +#define RESET_ACTIVE_STATUS0_CREG_RST (1 << RESET_ACTIVE_STATUS0_CREG_RST_SHIFT) + +/* BUS_RST: Current status of the BUS_RST */ +#define RESET_ACTIVE_STATUS0_BUS_RST_SHIFT (8) +#define RESET_ACTIVE_STATUS0_BUS_RST (1 << RESET_ACTIVE_STATUS0_BUS_RST_SHIFT) + +/* SCU_RST: Current status of the SCU_RST */ +#define RESET_ACTIVE_STATUS0_SCU_RST_SHIFT (9) +#define RESET_ACTIVE_STATUS0_SCU_RST (1 << RESET_ACTIVE_STATUS0_SCU_RST_SHIFT) + +/* M4_RST: Current status of the M4_RST */ +#define RESET_ACTIVE_STATUS0_M4_RST_SHIFT (13) +#define RESET_ACTIVE_STATUS0_M4_RST (1 << RESET_ACTIVE_STATUS0_M4_RST_SHIFT) + +/* LCD_RST: Current status of the LCD_RST */ +#define RESET_ACTIVE_STATUS0_LCD_RST_SHIFT (16) +#define RESET_ACTIVE_STATUS0_LCD_RST (1 << RESET_ACTIVE_STATUS0_LCD_RST_SHIFT) + +/* USB0_RST: Current status of the USB0_RST */ +#define RESET_ACTIVE_STATUS0_USB0_RST_SHIFT (17) +#define RESET_ACTIVE_STATUS0_USB0_RST (1 << RESET_ACTIVE_STATUS0_USB0_RST_SHIFT) + +/* USB1_RST: Current status of the USB1_RST */ +#define RESET_ACTIVE_STATUS0_USB1_RST_SHIFT (18) +#define RESET_ACTIVE_STATUS0_USB1_RST (1 << RESET_ACTIVE_STATUS0_USB1_RST_SHIFT) + +/* DMA_RST: Current status of the DMA_RST */ +#define RESET_ACTIVE_STATUS0_DMA_RST_SHIFT (19) +#define RESET_ACTIVE_STATUS0_DMA_RST (1 << RESET_ACTIVE_STATUS0_DMA_RST_SHIFT) + +/* SDIO_RST: Current status of the SDIO_RST */ +#define RESET_ACTIVE_STATUS0_SDIO_RST_SHIFT (20) +#define RESET_ACTIVE_STATUS0_SDIO_RST (1 << RESET_ACTIVE_STATUS0_SDIO_RST_SHIFT) + +/* EMC_RST: Current status of the EMC_RST */ +#define RESET_ACTIVE_STATUS0_EMC_RST_SHIFT (21) +#define RESET_ACTIVE_STATUS0_EMC_RST (1 << RESET_ACTIVE_STATUS0_EMC_RST_SHIFT) + +/* ETHERNET_RST: Current status of the ETHERNET_RST */ +#define RESET_ACTIVE_STATUS0_ETHERNET_RST_SHIFT (22) +#define RESET_ACTIVE_STATUS0_ETHERNET_RST \ + (1 << RESET_ACTIVE_STATUS0_ETHERNET_RST_SHIFT) + +/* FLASHA_RST: Current status of the FLASHA_RST */ +#define RESET_ACTIVE_STATUS0_FLASHA_RST_SHIFT (25) +#define RESET_ACTIVE_STATUS0_FLASHA_RST \ + (1 << RESET_ACTIVE_STATUS0_FLASHA_RST_SHIFT) + +/* EEPROM_RST: Current status of the EEPROM_RST */ +#define RESET_ACTIVE_STATUS0_EEPROM_RST_SHIFT (27) +#define RESET_ACTIVE_STATUS0_EEPROM_RST \ + (1 << RESET_ACTIVE_STATUS0_EEPROM_RST_SHIFT) + +/* GPIO_RST: Current status of the GPIO_RST */ +#define RESET_ACTIVE_STATUS0_GPIO_RST_SHIFT (28) +#define RESET_ACTIVE_STATUS0_GPIO_RST (1 << RESET_ACTIVE_STATUS0_GPIO_RST_SHIFT) + +/* FLASHB_RST: Current status of the FLASHB_RST */ +#define RESET_ACTIVE_STATUS0_FLASHB_RST_SHIFT (29) +#define RESET_ACTIVE_STATUS0_FLASHB_RST \ + (1 << RESET_ACTIVE_STATUS0_FLASHB_RST_SHIFT) + +/* --- RESET_ACTIVE_STATUS1 values ------------------------------ */ + +/* TIMER0_RST: Current status of the TIMER0_RST */ +#define RESET_ACTIVE_STATUS1_TIMER0_RST_SHIFT (0) +#define RESET_ACTIVE_STATUS1_TIMER0_RST \ + (1 << RESET_ACTIVE_STATUS1_TIMER0_RST_SHIFT) + +/* TIMER1_RST: Current status of the TIMER1_RST */ +#define RESET_ACTIVE_STATUS1_TIMER1_RST_SHIFT (1) +#define RESET_ACTIVE_STATUS1_TIMER1_RST \ + (1 << RESET_ACTIVE_STATUS1_TIMER1_RST_SHIFT) + +/* TIMER2_RST: Current status of the TIMER2_RST */ +#define RESET_ACTIVE_STATUS1_TIMER2_RST_SHIFT (2) +#define RESET_ACTIVE_STATUS1_TIMER2_RST \ + (1 << RESET_ACTIVE_STATUS1_TIMER2_RST_SHIFT) + +/* TIMER3_RST: Current status of the TIMER3_RST */ +#define RESET_ACTIVE_STATUS1_TIMER3_RST_SHIFT (3) +#define RESET_ACTIVE_STATUS1_TIMER3_RST \ + (1 << RESET_ACTIVE_STATUS1_TIMER3_RST_SHIFT) + +/* RITIMER_RST: Current status of the RITIMER_RST */ +#define RESET_ACTIVE_STATUS1_RITIMER_RST_SHIFT (4) +#define RESET_ACTIVE_STATUS1_RITIMER_RST \ + (1 << RESET_ACTIVE_STATUS1_RITIMER_RST_SHIFT) + +/* SCT_RST: Current status of the SCT_RST */ +#define RESET_ACTIVE_STATUS1_SCT_RST_SHIFT (5) +#define RESET_ACTIVE_STATUS1_SCT_RST \ + (1 << RESET_ACTIVE_STATUS1_SCT_RST_SHIFT) + +/* MOTOCONPWM_RST: Current status of the MOTOCONPWM_RST */ +#define RESET_ACTIVE_STATUS1_MOTOCONPWM_RST_SHIFT (6) +#define RESET_ACTIVE_STATUS1_MOTOCONPWM_RST \ + (1 << RESET_ACTIVE_STATUS1_MOTOCONPWM_RST_SHIFT) + +/* QEI_RST: Current status of the QEI_RST */ +#define RESET_ACTIVE_STATUS1_QEI_RST_SHIFT (7) +#define RESET_ACTIVE_STATUS1_QEI_RST \ + (1 << RESET_ACTIVE_STATUS1_QEI_RST_SHIFT) + +/* ADC0_RST: Current status of the ADC0_RST */ +#define RESET_ACTIVE_STATUS1_ADC0_RST_SHIFT (8) +#define RESET_ACTIVE_STATUS1_ADC0_RST \ + (1 << RESET_ACTIVE_STATUS1_ADC0_RST_SHIFT) + +/* ADC1_RST: Current status of the ADC1_RST */ +#define RESET_ACTIVE_STATUS1_ADC1_RST_SHIFT (9) +#define RESET_ACTIVE_STATUS1_ADC1_RST \ + (1 << RESET_ACTIVE_STATUS1_ADC1_RST_SHIFT) + +/* DAC_RST: Current status of the DAC_RST */ +#define RESET_ACTIVE_STATUS1_DAC_RST_SHIFT (10) +#define RESET_ACTIVE_STATUS1_DAC_RST (1 << RESET_ACTIVE_STATUS1_DAC_RST_SHIFT) + +/* UART0_RST: Current status of the UART0_RST */ +#define RESET_ACTIVE_STATUS1_UART0_RST_SHIFT (12) +#define RESET_ACTIVE_STATUS1_UART0_RST \ + (1 << RESET_ACTIVE_STATUS1_UART0_RST_SHIFT) + +/* UART1_RST: Current status of the UART1_RST */ +#define RESET_ACTIVE_STATUS1_UART1_RST_SHIFT (13) +#define RESET_ACTIVE_STATUS1_UART1_RST \ + (1 << RESET_ACTIVE_STATUS1_UART1_RST_SHIFT) + +/* UART2_RST: Current status of the UART2_RST */ +#define RESET_ACTIVE_STATUS1_UART2_RST_SHIFT (14) +#define RESET_ACTIVE_STATUS1_UART2_RST \ + (1 << RESET_ACTIVE_STATUS1_UART2_RST_SHIFT) + +/* UART3_RST: Current status of the UART3_RST */ +#define RESET_ACTIVE_STATUS1_UART3_RST_SHIFT (15) +#define RESET_ACTIVE_STATUS1_UART3_RST \ + (1 << RESET_ACTIVE_STATUS1_UART3_RST_SHIFT) + +/* I2C0_RST: Current status of the I2C0_RST */ +#define RESET_ACTIVE_STATUS1_I2C0_RST_SHIFT (16) +#define RESET_ACTIVE_STATUS1_I2C0_RST \ + (1 << RESET_ACTIVE_STATUS1_I2C0_RST_SHIFT) + +/* I2C1_RST: Current status of the I2C1_RST */ +#define RESET_ACTIVE_STATUS1_I2C1_RST_SHIFT (17) +#define RESET_ACTIVE_STATUS1_I2C1_RST \ + (1 << RESET_ACTIVE_STATUS1_I2C1_RST_SHIFT) + +/* SSP0_RST: Current status of the SSP0_RST */ +#define RESET_ACTIVE_STATUS1_SSP0_RST_SHIFT (18) +#define RESET_ACTIVE_STATUS1_SSP0_RST \ + (1 << RESET_ACTIVE_STATUS1_SSP0_RST_SHIFT) + +/* SSP1_RST: Current status of the SSP1_RST */ +#define RESET_ACTIVE_STATUS1_SSP1_RST_SHIFT (19) +#define RESET_ACTIVE_STATUS1_SSP1_RST \ + (1 << RESET_ACTIVE_STATUS1_SSP1_RST_SHIFT) + +/* I2S_RST: Current status of the I2S_RST */ +#define RESET_ACTIVE_STATUS1_I2S_RST_SHIFT (20) +#define RESET_ACTIVE_STATUS1_I2S_RST (1 << RESET_ACTIVE_STATUS1_I2S_RST_SHIFT) + +/* SPIFI_RST: Current status of the SPIFI_RST */ +#define RESET_ACTIVE_STATUS1_SPIFI_RST_SHIFT (21) +#define RESET_ACTIVE_STATUS1_SPIFI_RST \ + (1 << RESET_ACTIVE_STATUS1_SPIFI_RST_SHIFT) + +/* CAN1_RST: Current status of the CAN1_RST */ +#define RESET_ACTIVE_STATUS1_CAN1_RST_SHIFT (22) +#define RESET_ACTIVE_STATUS1_CAN1_RST \ + (1 << RESET_ACTIVE_STATUS1_CAN1_RST_SHIFT) + +/* CAN0_RST: Current status of the CAN0_RST */ +#define RESET_ACTIVE_STATUS1_CAN0_RST_SHIFT (23) +#define RESET_ACTIVE_STATUS1_CAN0_RST \ + (1 << RESET_ACTIVE_STATUS1_CAN0_RST_SHIFT) + +/* M0APP_RST: Current status of the M0APP_RST */ +#define RESET_ACTIVE_STATUS1_M0APP_RST_SHIFT (24) +#define RESET_ACTIVE_STATUS1_M0APP_RST \ + (1 << RESET_ACTIVE_STATUS1_M0APP_RST_SHIFT) + +/* SGPIO_RST: Current status of the SGPIO_RST */ +#define RESET_ACTIVE_STATUS1_SGPIO_RST_SHIFT (25) +#define RESET_ACTIVE_STATUS1_SGPIO_RST \ + (1 << RESET_ACTIVE_STATUS1_SGPIO_RST_SHIFT) + +/* SPI_RST: Current status of the SPI_RST */ +#define RESET_ACTIVE_STATUS1_SPI_RST_SHIFT (26) +#define RESET_ACTIVE_STATUS1_SPI_RST (1 << RESET_ACTIVE_STATUS1_SPI_RST_SHIFT) + +/* --- RESET_EXT_STAT0 values ----------------------------------- */ + +/* EXT_RESET: Reset activated by external reset from reset pin */ +#define RESET_EXT_STAT0_EXT_RESET_SHIFT (0) +#define RESET_EXT_STAT0_EXT_RESET (1 << RESET_EXT_STAT0_EXT_RESET_SHIFT) + +/* BOD_RESET: Reset activated by BOD reset */ +#define RESET_EXT_STAT0_BOD_RESET_SHIFT (4) +#define RESET_EXT_STAT0_BOD_RESET (1 << RESET_EXT_STAT0_BOD_RESET_SHIFT) + +/* WWDT_RESET: Reset activated by WWDT time-out */ +#define RESET_EXT_STAT0_WWDT_RESET_SHIFT (5) +#define RESET_EXT_STAT0_WWDT_RESET (1 << RESET_EXT_STAT0_WWDT_RESET_SHIFT) + +/* --- RESET_EXT_STAT1 values ----------------------------------- */ + +/* CORE_RESET: Reset activated by CORE_RST output */ +#define RESET_EXT_STAT1_CORE_RESET_SHIFT (1) +#define RESET_EXT_STAT1_CORE_RESET (1 << RESET_EXT_STAT1_CORE_RESET_SHIFT) + +/* --- RESET_EXT_STAT2 values ----------------------------------- */ + +/* PERIPHERAL_RESET: Reset activated by PERIPHERAL_RST output */ +#define RESET_EXT_STAT2_PERIPHERAL_RESET_SHIFT (2) +#define RESET_EXT_STAT2_PERIPHERAL_RESET \ + (1 << RESET_EXT_STAT2_PERIPHERAL_RESET_SHIFT) + +/* --- RESET_EXT_STAT4 values ----------------------------------- */ + +/* CORE_RESET: Reset activated by CORE_RST output */ +#define RESET_EXT_STAT4_CORE_RESET_SHIFT (1) +#define RESET_EXT_STAT4_CORE_RESET (1 << RESET_EXT_STAT4_CORE_RESET_SHIFT) + +/* --- RESET_EXT_STAT5 values ----------------------------------- */ + +/* CORE_RESET: Reset activated by CORE_RST output */ +#define RESET_EXT_STAT5_CORE_RESET_SHIFT (1) +#define RESET_EXT_STAT5_CORE_RESET (1 << RESET_EXT_STAT5_CORE_RESET_SHIFT) + +/* --- RESET_EXT_STAT8 values ----------------------------------- */ + +/* PERIPHERAL_RESET: Reset activated by PERIPHERAL_RST output */ +#define RESET_EXT_STAT8_PERIPHERAL_RESET_SHIFT (2) +#define RESET_EXT_STAT8_PERIPHERAL_RESET \ + (1 << RESET_EXT_STAT8_PERIPHERAL_RESET_SHIFT) + +/* --- RESET_EXT_STAT9 values ----------------------------------- */ + +/* PERIPHERAL_RESET: Reset activated by PERIPHERAL_RST output */ +#define RESET_EXT_STAT9_PERIPHERAL_RESET_SHIFT (2) +#define RESET_EXT_STAT9_PERIPHERAL_RESET \ + (1 << RESET_EXT_STAT9_PERIPHERAL_RESET_SHIFT) + +/* --- RESET_EXT_STAT13 values ---------------------------------- */ + +/* MASTER_RESET: Reset activated by MASTER_RST output */ +#define RESET_EXT_STAT13_MASTER_RESET_SHIFT (3) +#define RESET_EXT_STAT13_MASTER_RESET (1 << RESET_EXT_STAT13_MASTER_RESET_SHIFT) + +/* --- RESET_EXT_STAT16 values ---------------------------------- */ + +/* MASTER_RESET: Reset activated by MASTER_RST output */ +#define RESET_EXT_STAT16_MASTER_RESET_SHIFT (3) +#define RESET_EXT_STAT16_MASTER_RESET (1 << RESET_EXT_STAT16_MASTER_RESET_SHIFT) + +/* --- RESET_EXT_STAT17 values ---------------------------------- */ + +/* MASTER_RESET: Reset activated by MASTER_RST output */ +#define RESET_EXT_STAT17_MASTER_RESET_SHIFT (3) +#define RESET_EXT_STAT17_MASTER_RESET (1 << RESET_EXT_STAT17_MASTER_RESET_SHIFT) + +/* --- RESET_EXT_STAT18 values ---------------------------------- */ + +/* MASTER_RESET: Reset activated by MASTER_RST output */ +#define RESET_EXT_STAT18_MASTER_RESET_SHIFT (3) +#define RESET_EXT_STAT18_MASTER_RESET (1 << RESET_EXT_STAT18_MASTER_RESET_SHIFT) + +/* --- RESET_EXT_STAT19 values ---------------------------------- */ + +/* MASTER_RESET: Reset activated by MASTER_RST output */ +#define RESET_EXT_STAT19_MASTER_RESET_SHIFT (3) +#define RESET_EXT_STAT19_MASTER_RESET (1 << RESET_EXT_STAT19_MASTER_RESET_SHIFT) + +/* --- RESET_EXT_STAT20 values ---------------------------------- */ + +/* MASTER_RESET: Reset activated by MASTER_RST output */ +#define RESET_EXT_STAT20_MASTER_RESET_SHIFT (3) +#define RESET_EXT_STAT20_MASTER_RESET (1 << RESET_EXT_STAT20_MASTER_RESET_SHIFT) + +/* --- RESET_EXT_STAT21 values ---------------------------------- */ + +/* MASTER_RESET: Reset activated by MASTER_RST output */ +#define RESET_EXT_STAT21_MASTER_RESET_SHIFT (3) +#define RESET_EXT_STAT21_MASTER_RESET (1 << RESET_EXT_STAT21_MASTER_RESET_SHIFT) + +/* --- RESET_EXT_STAT22 values ---------------------------------- */ + +/* MASTER_RESET: Reset activated by MASTER_RST output */ +#define RESET_EXT_STAT22_MASTER_RESET_SHIFT (3) +#define RESET_EXT_STAT22_MASTER_RESET (1 << RESET_EXT_STAT22_MASTER_RESET_SHIFT) + +/* --- RESET_EXT_STAT25 values ---------------------------------- */ + +/* PERIPHERAL_RESET: Reset activated by PERIPHERAL_RST output */ +#define RESET_EXT_STAT25_PERIPHERAL_RESET_SHIFT (2) +#define RESET_EXT_STAT25_PERIPHERAL_RESET \ + (1 << RESET_EXT_STAT25_PERIPHERAL_RESET_SHIFT) + +/* --- RESET_EXT_STAT27 values ---------------------------------- */ + +/* PERIPHERAL_RESET: Reset activated by PERIPHERAL_RST output */ +#define RESET_EXT_STAT27_PERIPHERAL_RESET_SHIFT (2) +#define RESET_EXT_STAT27_PERIPHERAL_RESET \ + (1 << RESET_EXT_STAT27_PERIPHERAL_RESET_SHIFT) + +/* --- RESET_EXT_STAT28 values ---------------------------------- */ + +/* PERIPHERAL_RESET: Reset activated by PERIPHERAL_RST output */ +#define RESET_EXT_STAT28_PERIPHERAL_RESET_SHIFT (2) +#define RESET_EXT_STAT28_PERIPHERAL_RESET \ + (1 << RESET_EXT_STAT28_PERIPHERAL_RESET_SHIFT) + +/* --- RESET_EXT_STAT29 values ---------------------------------- */ + +/* PERIPHERAL_RESET: Reset activated by PERIPHERAL_RST output */ +#define RESET_EXT_STAT29_PERIPHERAL_RESET_SHIFT (2) +#define RESET_EXT_STAT29_PERIPHERAL_RESET \ + (1 << RESET_EXT_STAT29_PERIPHERAL_RESET_SHIFT) + +/* --- RESET_EXT_STAT32 values ---------------------------------- */ + +/* PERIPHERAL_RESET: Reset activated by PERIPHERAL_RST output */ +#define RESET_EXT_STAT32_PERIPHERAL_RESET_SHIFT (2) +#define RESET_EXT_STAT32_PERIPHERAL_RESET \ + (1 << RESET_EXT_STAT32_PERIPHERAL_RESET_SHIFT) + +/* --- RESET_EXT_STAT33 values ---------------------------------- */ + +/* PERIPHERAL_RESET: Reset activated by PERIPHERAL_RST output */ +#define RESET_EXT_STAT33_PERIPHERAL_RESET_SHIFT (2) +#define RESET_EXT_STAT33_PERIPHERAL_RESET \ + (1 << RESET_EXT_STAT33_PERIPHERAL_RESET_SHIFT) + +/* --- RESET_EXT_STAT34 values ---------------------------------- */ + +/* PERIPHERAL_RESET: Reset activated by PERIPHERAL_RST output */ +#define RESET_EXT_STAT34_PERIPHERAL_RESET_SHIFT (2) +#define RESET_EXT_STAT34_PERIPHERAL_RESET \ + (1 << RESET_EXT_STAT34_PERIPHERAL_RESET_SHIFT) + +/* --- RESET_EXT_STAT35 values ---------------------------------- */ + +/* PERIPHERAL_RESET: Reset activated by PERIPHERAL_RST output */ +#define RESET_EXT_STAT35_PERIPHERAL_RESET_SHIFT (2) +#define RESET_EXT_STAT35_PERIPHERAL_RESET \ + (1 << RESET_EXT_STAT35_PERIPHERAL_RESET_SHIFT) + +/* --- RESET_EXT_STAT36 values ---------------------------------- */ + +/* PERIPHERAL_RESET: Reset activated by PERIPHERAL_RST output */ +#define RESET_EXT_STAT36_PERIPHERAL_RESET_SHIFT (2) +#define RESET_EXT_STAT36_PERIPHERAL_RESET \ + (1 << RESET_EXT_STAT36_PERIPHERAL_RESET_SHIFT) + +/* --- RESET_EXT_STAT37 values ---------------------------------- */ + +/* PERIPHERAL_RESET: Reset activated by PERIPHERAL_RST output */ +#define RESET_EXT_STAT37_PERIPHERAL_RESET_SHIFT (2) +#define RESET_EXT_STAT37_PERIPHERAL_RESET \ + (1 << RESET_EXT_STAT37_PERIPHERAL_RESET_SHIFT) + +/* --- RESET_EXT_STAT38 values ---------------------------------- */ + +/* PERIPHERAL_RESET: Reset activated by PERIPHERAL_RST output */ +#define RESET_EXT_STAT38_PERIPHERAL_RESET_SHIFT (2) +#define RESET_EXT_STAT38_PERIPHERAL_RESET \ + (1 << RESET_EXT_STAT38_PERIPHERAL_RESET_SHIFT) + +/* --- RESET_EXT_STAT39 values ---------------------------------- */ + +/* PERIPHERAL_RESET: Reset activated by PERIPHERAL_RST output */ +#define RESET_EXT_STAT39_PERIPHERAL_RESET_SHIFT (2) +#define RESET_EXT_STAT39_PERIPHERAL_RESET \ + (1 << RESET_EXT_STAT39_PERIPHERAL_RESET_SHIFT) + +/* --- RESET_EXT_STAT40 values ---------------------------------- */ + +/* PERIPHERAL_RESET: Reset activated by PERIPHERAL_RST output */ +#define RESET_EXT_STAT40_PERIPHERAL_RESET_SHIFT (2) +#define RESET_EXT_STAT40_PERIPHERAL_RESET \ + (1 << RESET_EXT_STAT40_PERIPHERAL_RESET_SHIFT) + +/* --- RESET_EXT_STAT41 values ---------------------------------- */ + +/* PERIPHERAL_RESET: Reset activated by PERIPHERAL_RST output */ +#define RESET_EXT_STAT41_PERIPHERAL_RESET_SHIFT (2) +#define RESET_EXT_STAT41_PERIPHERAL_RESET \ + (1 << RESET_EXT_STAT41_PERIPHERAL_RESET_SHIFT) + +/* --- RESET_EXT_STAT42 values ---------------------------------- */ + +/* PERIPHERAL_RESET: Reset activated by PERIPHERAL_RST output */ +#define RESET_EXT_STAT42_PERIPHERAL_RESET_SHIFT (2) +#define RESET_EXT_STAT42_PERIPHERAL_RESET \ + (1 << RESET_EXT_STAT42_PERIPHERAL_RESET_SHIFT) + +/* --- RESET_EXT_STAT44 values ---------------------------------- */ + +/* PERIPHERAL_RESET: Reset activated by PERIPHERAL_RST output */ +#define RESET_EXT_STAT44_PERIPHERAL_RESET_SHIFT (2) +#define RESET_EXT_STAT44_PERIPHERAL_RESET \ + (1 << RESET_EXT_STAT44_PERIPHERAL_RESET_SHIFT) + +/* --- RESET_EXT_STAT45 values ---------------------------------- */ + +/* PERIPHERAL_RESET: Reset activated by PERIPHERAL_RST output */ +#define RESET_EXT_STAT45_PERIPHERAL_RESET_SHIFT (2) +#define RESET_EXT_STAT45_PERIPHERAL_RESET \ + (1 << RESET_EXT_STAT45_PERIPHERAL_RESET_SHIFT) + +/* --- RESET_EXT_STAT46 values ---------------------------------- */ + +/* PERIPHERAL_RESET: Reset activated by PERIPHERAL_RST output */ +#define RESET_EXT_STAT46_PERIPHERAL_RESET_SHIFT (2) +#define RESET_EXT_STAT46_PERIPHERAL_RESET \ + (1 << RESET_EXT_STAT46_PERIPHERAL_RESET_SHIFT) + +/* --- RESET_EXT_STAT47 values ---------------------------------- */ + +/* PERIPHERAL_RESET: Reset activated by PERIPHERAL_RST output */ +#define RESET_EXT_STAT47_PERIPHERAL_RESET_SHIFT (2) +#define RESET_EXT_STAT47_PERIPHERAL_RESET \ + (1 << RESET_EXT_STAT47_PERIPHERAL_RESET_SHIFT) + +/* --- RESET_EXT_STAT48 values ---------------------------------- */ + +/* PERIPHERAL_RESET: Reset activated by PERIPHERAL_RST output */ +#define RESET_EXT_STAT48_PERIPHERAL_RESET_SHIFT (2) +#define RESET_EXT_STAT48_PERIPHERAL_RESET \ + (1 << RESET_EXT_STAT48_PERIPHERAL_RESET_SHIFT) + +/* --- RESET_EXT_STAT49 values ---------------------------------- */ + +/* PERIPHERAL_RESET: Reset activated by PERIPHERAL_RST output */ +#define RESET_EXT_STAT49_PERIPHERAL_RESET_SHIFT (2) +#define RESET_EXT_STAT49_PERIPHERAL_RESET \ + (1 << RESET_EXT_STAT49_PERIPHERAL_RESET_SHIFT) + +/* --- RESET_EXT_STAT50 values ---------------------------------- */ + +/* PERIPHERAL_RESET: Reset activated by PERIPHERAL_RST output */ +#define RESET_EXT_STAT50_PERIPHERAL_RESET_SHIFT (2) +#define RESET_EXT_STAT50_PERIPHERAL_RESET \ + (1 << RESET_EXT_STAT50_PERIPHERAL_RESET_SHIFT) + +/* --- RESET_EXT_STAT51 values ---------------------------------- */ + +/* PERIPHERAL_RESET: Reset activated by PERIPHERAL_RST output */ +#define RESET_EXT_STAT51_PERIPHERAL_RESET_SHIFT (2) +#define RESET_EXT_STAT51_PERIPHERAL_RESET \ + (1 << RESET_EXT_STAT51_PERIPHERAL_RESET_SHIFT) + +/* --- RESET_EXT_STAT52 values ---------------------------------- */ + +/* PERIPHERAL_RESET: Reset activated by PERIPHERAL_RST output */ +#define RESET_EXT_STAT52_PERIPHERAL_RESET_SHIFT (2) +#define RESET_EXT_STAT52_PERIPHERAL_RESET \ + (1 << RESET_EXT_STAT52_PERIPHERAL_RESET_SHIFT) + +/* --- RESET_EXT_STAT53 values ---------------------------------- */ + +/* PERIPHERAL_RESET: Reset activated by PERIPHERAL_RST output */ +#define RESET_EXT_STAT53_PERIPHERAL_RESET_SHIFT (2) +#define RESET_EXT_STAT53_PERIPHERAL_RESET \ + (1 << RESET_EXT_STAT53_PERIPHERAL_RESET_SHIFT) + +/* --- RESET_EXT_STAT54 values ---------------------------------- */ + +/* PERIPHERAL_RESET: Reset activated by PERIPHERAL_RST output */ +#define RESET_EXT_STAT54_PERIPHERAL_RESET_SHIFT (2) +#define RESET_EXT_STAT54_PERIPHERAL_RESET \ + (1 << RESET_EXT_STAT54_PERIPHERAL_RESET_SHIFT) + +/* --- RESET_EXT_STAT55 values ---------------------------------- */ + +/* PERIPHERAL_RESET: Reset activated by PERIPHERAL_RST output */ +#define RESET_EXT_STAT55_PERIPHERAL_RESET_SHIFT (2) +#define RESET_EXT_STAT55_PERIPHERAL_RESET \ + (1 << RESET_EXT_STAT55_PERIPHERAL_RESET_SHIFT) + +/* --- RESET_EXT_STAT56 values ---------------------------------- */ + +/* PERIPHERAL_RESET: Reset activated by PERIPHERAL_RST output */ +#define RESET_EXT_STAT56_PERIPHERAL_RESET_SHIFT (2) +#define RESET_EXT_STAT56_PERIPHERAL_RESET \ + (1 << RESET_EXT_STAT56_PERIPHERAL_RESET_SHIFT) + +/* --- RESET_EXT_STAT57 values ---------------------------------- */ + +/* PERIPHERAL_RESET: Reset activated by PERIPHERAL_RST output */ +#define RESET_EXT_STAT57_PERIPHERAL_RESET_SHIFT (2) +#define RESET_EXT_STAT57_PERIPHERAL_RESET \ + (1 << RESET_EXT_STAT57_PERIPHERAL_RESET_SHIFT) + +/* --- RESET_EXT_STAT58 values ---------------------------------- */ + +/* PERIPHERAL_RESET: Reset activated by PERIPHERAL_RST output */ +#define RESET_EXT_STAT58_PERIPHERAL_RESET_SHIFT (2) +#define RESET_EXT_STAT58_PERIPHERAL_RESET \ + (1 << RESET_EXT_STAT58_PERIPHERAL_RESET_SHIFT) + +/**@}*/ + +#endif diff --git a/libopencm3/include/libopencm3/lpc43xx/ritimer.h b/libopencm3/include/libopencm3/lpc43xx/ritimer.h new file mode 100644 index 0000000..e736bc3 --- /dev/null +++ b/libopencm3/include/libopencm3/lpc43xx/ritimer.h @@ -0,0 +1,59 @@ +/** @defgroup ritimer_defines Repetitive Interrupt Timer Defines + +@brief <b>Defined Constants and Types for the LPC43xx Repetitive Interrupt +Timer</b> + +@ingroup LPC43xx_defines + +@version 1.0.0 + +@author @htmlonly © @endhtmlonly 2012 Michael Ossmann <mike@ossmann.com> + +@date 10 March 2013 + +LGPL License Terms @ref lgpl_license + */ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2012 Michael Ossmann <mike@ossmann.com> + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see <http://www.gnu.org/licenses/>. + */ + +#ifndef LPC43XX_RITIMER_H +#define LPC43XX_RITIMER_H + +/**@{*/ + +#include <libopencm3/cm3/common.h> +#include <libopencm3/lpc43xx/memorymap.h> + +/* --- Repetitive Interrupt Timer registers -------------------------------- */ + +/* Compare register */ +#define RITIMER_COMPVAL MMIO32(RITIMER_BASE + 0x000) + +/* Mask register */ +#define RITIMER_MASK MMIO32(RITIMER_BASE + 0x004) + +/* Control register */ +#define RITIMER_CTRL MMIO32(RITIMER_BASE + 0x008) + +/* 32-bit counter */ +#define RITIMER_COUNTER MMIO32(RITIMER_BASE + 0x00C) + +/**@}*/ + +#endif diff --git a/libopencm3/include/libopencm3/lpc43xx/scu.h b/libopencm3/include/libopencm3/lpc43xx/scu.h new file mode 100644 index 0000000..b869318 --- /dev/null +++ b/libopencm3/include/libopencm3/lpc43xx/scu.h @@ -0,0 +1,780 @@ +/** @defgroup scu_defines System Control Unit Defines + +@brief <b>Defined Constants and Types for the LPC43xx System Control Unit</b> + +@ingroup LPC43xx_defines + +@version 1.0.0 + +@author @htmlonly © @endhtmlonly 2012 Michael Ossmann <mike@ossmann.com> + +@date 10 March 2013 + +LGPL License Terms @ref lgpl_license + */ +/* +* This file is part of the libopencm3 project. +* +* Copyright (C) 2012 Michael Ossmann <mike@ossmann.com> +* Copyright (C) 2012 Benjamin Vernoux <titanmkd@gmail.com> +* +* This library is free software: you can redistribute it and/or modify +* it under the terms of the GNU Lesser General Public License as published by +* the Free Software Foundation, either version 3 of the License, or +* (at your option) any later version. +* +* This library is distributed in the hope that it will be useful, +* but WITHOUT ANY WARRANTY; without even the implied warranty of +* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +* GNU Lesser General Public License for more details. +* +* You should have received a copy of the GNU Lesser General Public License +* along with this library. If not, see <http://www.gnu.org/licenses/>. +*/ + +#ifndef LPC43XX_SCU_H +#define LPC43XX_SCU_H + +/**@{*/ + +#include <libopencm3/cm3/common.h> +#include <libopencm3/lpc43xx/memorymap.h> + +/* --- Convenience macros -------------------------------------------------- */ + +/* Pin group base addresses */ +#define PIN_GROUP0 (SCU_BASE + 0x000) +#define PIN_GROUP1 (SCU_BASE + 0x080) +#define PIN_GROUP2 (SCU_BASE + 0x100) +#define PIN_GROUP3 (SCU_BASE + 0x180) +#define PIN_GROUP4 (SCU_BASE + 0x200) +#define PIN_GROUP5 (SCU_BASE + 0x280) +#define PIN_GROUP6 (SCU_BASE + 0x300) +#define PIN_GROUP7 (SCU_BASE + 0x380) +#define PIN_GROUP8 (SCU_BASE + 0x400) +#define PIN_GROUP9 (SCU_BASE + 0x480) +#define PIN_GROUPA (SCU_BASE + 0x500) +#define PIN_GROUPB (SCU_BASE + 0x580) +#define PIN_GROUPC (SCU_BASE + 0x600) +#define PIN_GROUPD (SCU_BASE + 0x680) +#define PIN_GROUPE (SCU_BASE + 0x700) +#define PIN_GROUPF (SCU_BASE + 0x780) + +#define PIN0 0x000 +#define PIN1 0x004 +#define PIN2 0x008 +#define PIN3 0x00C +#define PIN4 0x010 +#define PIN5 0x014 +#define PIN6 0x018 +#define PIN7 0x01C +#define PIN8 0x020 +#define PIN9 0x024 +#define PIN10 0x028 +#define PIN11 0x02C +#define PIN12 0x030 +#define PIN13 0x034 +#define PIN14 0x038 +#define PIN15 0x03C +#define PIN16 0x040 +#define PIN17 0x044 +#define PIN18 0x048 +#define PIN19 0x04C +#define PIN20 0x050 + + +/* --- SCU registers ------------------------------------------------------- */ + +/* Pin configuration registers */ + +#define SCU_SFS(group, pin) MMIO32(group + pin) + +/* Pins P0_n */ +#define SCU_SFSP0_0 SCU_SFS(PIN_GROUP0, PIN0) +#define SCU_SFSP0_1 SCU_SFS(PIN_GROUP0, PIN1) + +/* Pins P1_n */ +#define SCU_SFSP1_0 SCU_SFS(PIN_GROUP1, PIN0) +#define SCU_SFSP1_1 SCU_SFS(PIN_GROUP1, PIN1) +#define SCU_SFSP1_2 SCU_SFS(PIN_GROUP1, PIN2) +#define SCU_SFSP1_3 SCU_SFS(PIN_GROUP1, PIN3) +#define SCU_SFSP1_4 SCU_SFS(PIN_GROUP1, PIN4) +#define SCU_SFSP1_5 SCU_SFS(PIN_GROUP1, PIN5) +#define SCU_SFSP1_6 SCU_SFS(PIN_GROUP1, PIN6) +#define SCU_SFSP1_7 SCU_SFS(PIN_GROUP1, PIN7) +#define SCU_SFSP1_8 SCU_SFS(PIN_GROUP1, PIN8) +#define SCU_SFSP1_9 SCU_SFS(PIN_GROUP1, PIN9) +#define SCU_SFSP1_10 SCU_SFS(PIN_GROUP1, PIN10) +#define SCU_SFSP1_11 SCU_SFS(PIN_GROUP1, PIN11) +#define SCU_SFSP1_12 SCU_SFS(PIN_GROUP1, PIN12) +#define SCU_SFSP1_13 SCU_SFS(PIN_GROUP1, PIN13) +#define SCU_SFSP1_14 SCU_SFS(PIN_GROUP1, PIN14) +#define SCU_SFSP1_15 SCU_SFS(PIN_GROUP1, PIN15) +#define SCU_SFSP1_16 SCU_SFS(PIN_GROUP1, PIN16) +#define SCU_SFSP1_17 SCU_SFS(PIN_GROUP1, PIN17) +#define SCU_SFSP1_18 SCU_SFS(PIN_GROUP1, PIN18) +#define SCU_SFSP1_19 SCU_SFS(PIN_GROUP1, PIN19) +#define SCU_SFSP1_20 SCU_SFS(PIN_GROUP1, PIN20) + +/* Pins P2_n */ +#define SCU_SFSP2_0 SCU_SFS(PIN_GROUP2, PIN0) +#define SCU_SFSP2_1 SCU_SFS(PIN_GROUP2, PIN1) +#define SCU_SFSP2_2 SCU_SFS(PIN_GROUP2, PIN2) +#define SCU_SFSP2_3 SCU_SFS(PIN_GROUP2, PIN3) +#define SCU_SFSP2_4 SCU_SFS(PIN_GROUP2, PIN4) +#define SCU_SFSP2_5 SCU_SFS(PIN_GROUP2, PIN5) +#define SCU_SFSP2_6 SCU_SFS(PIN_GROUP2, PIN6) +#define SCU_SFSP2_7 SCU_SFS(PIN_GROUP2, PIN7) +#define SCU_SFSP2_8 SCU_SFS(PIN_GROUP2, PIN8) +#define SCU_SFSP2_9 SCU_SFS(PIN_GROUP2, PIN9) +#define SCU_SFSP2_10 SCU_SFS(PIN_GROUP2, PIN10) +#define SCU_SFSP2_11 SCU_SFS(PIN_GROUP2, PIN11) +#define SCU_SFSP2_12 SCU_SFS(PIN_GROUP2, PIN12) +#define SCU_SFSP2_13 SCU_SFS(PIN_GROUP2, PIN13) + +/* Pins P3_n */ +#define SCU_SFSP3_0 SCU_SFS(PIN_GROUP3, PIN0) +#define SCU_SFSP3_1 SCU_SFS(PIN_GROUP3, PIN1) +#define SCU_SFSP3_2 SCU_SFS(PIN_GROUP3, PIN2) +#define SCU_SFSP3_3 SCU_SFS(PIN_GROUP3, PIN3) +#define SCU_SFSP3_4 SCU_SFS(PIN_GROUP3, PIN4) +#define SCU_SFSP3_5 SCU_SFS(PIN_GROUP3, PIN5) +#define SCU_SFSP3_6 SCU_SFS(PIN_GROUP3, PIN6) +#define SCU_SFSP3_7 SCU_SFS(PIN_GROUP3, PIN7) +#define SCU_SFSP3_8 SCU_SFS(PIN_GROUP3, PIN8) + +/* Pins P4_n */ +#define SCU_SFSP4_0 SCU_SFS(PIN_GROUP4, PIN0) +#define SCU_SFSP4_1 SCU_SFS(PIN_GROUP4, PIN1) +#define SCU_SFSP4_2 SCU_SFS(PIN_GROUP4, PIN2) +#define SCU_SFSP4_3 SCU_SFS(PIN_GROUP4, PIN3) +#define SCU_SFSP4_4 SCU_SFS(PIN_GROUP4, PIN4) +#define SCU_SFSP4_5 SCU_SFS(PIN_GROUP4, PIN5) +#define SCU_SFSP4_6 SCU_SFS(PIN_GROUP4, PIN6) +#define SCU_SFSP4_7 SCU_SFS(PIN_GROUP4, PIN7) +#define SCU_SFSP4_8 SCU_SFS(PIN_GROUP4, PIN8) +#define SCU_SFSP4_9 SCU_SFS(PIN_GROUP4, PIN9) +#define SCU_SFSP4_10 SCU_SFS(PIN_GROUP4, PIN10) + +/* Pins P5_n */ +#define SCU_SFSP5_0 SCU_SFS(PIN_GROUP5, PIN0) +#define SCU_SFSP5_1 SCU_SFS(PIN_GROUP5, PIN1) +#define SCU_SFSP5_2 SCU_SFS(PIN_GROUP5, PIN2) +#define SCU_SFSP5_3 SCU_SFS(PIN_GROUP5, PIN3) +#define SCU_SFSP5_4 SCU_SFS(PIN_GROUP5, PIN4) +#define SCU_SFSP5_5 SCU_SFS(PIN_GROUP5, PIN5) +#define SCU_SFSP5_6 SCU_SFS(PIN_GROUP5, PIN6) +#define SCU_SFSP5_7 SCU_SFS(PIN_GROUP5, PIN7) + +/* Pins P6_n */ +#define SCU_SFSP6_0 SCU_SFS(PIN_GROUP6, PIN0) +#define SCU_SFSP6_1 SCU_SFS(PIN_GROUP6, PIN1) +#define SCU_SFSP6_2 SCU_SFS(PIN_GROUP6, PIN2) +#define SCU_SFSP6_3 SCU_SFS(PIN_GROUP6, PIN3) +#define SCU_SFSP6_4 SCU_SFS(PIN_GROUP6, PIN4) +#define SCU_SFSP6_5 SCU_SFS(PIN_GROUP6, PIN5) +#define SCU_SFSP6_6 SCU_SFS(PIN_GROUP6, PIN6) +#define SCU_SFSP6_7 SCU_SFS(PIN_GROUP6, PIN7) +#define SCU_SFSP6_8 SCU_SFS(PIN_GROUP6, PIN8) +#define SCU_SFSP6_9 SCU_SFS(PIN_GROUP6, PIN9) +#define SCU_SFSP6_10 SCU_SFS(PIN_GROUP6, PIN10) +#define SCU_SFSP6_11 SCU_SFS(PIN_GROUP6, PIN11) +#define SCU_SFSP6_12 SCU_SFS(PIN_GROUP6, PIN12) + +/* Pins P7_n */ +#define SCU_SFSP7_0 SCU_SFS(PIN_GROUP7, PIN0) +#define SCU_SFSP7_1 SCU_SFS(PIN_GROUP7, PIN1) +#define SCU_SFSP7_2 SCU_SFS(PIN_GROUP7, PIN2) +#define SCU_SFSP7_3 SCU_SFS(PIN_GROUP7, PIN3) +#define SCU_SFSP7_4 SCU_SFS(PIN_GROUP7, PIN4) +#define SCU_SFSP7_5 SCU_SFS(PIN_GROUP7, PIN5) +#define SCU_SFSP7_6 SCU_SFS(PIN_GROUP7, PIN6) +#define SCU_SFSP7_7 SCU_SFS(PIN_GROUP7, PIN7) + +/* Pins P8_n */ +#define SCU_SFSP8_0 SCU_SFS(PIN_GROUP8, PIN0) +#define SCU_SFSP8_1 SCU_SFS(PIN_GROUP8, PIN1) +#define SCU_SFSP8_2 SCU_SFS(PIN_GROUP8, PIN2) +#define SCU_SFSP8_3 SCU_SFS(PIN_GROUP8, PIN3) +#define SCU_SFSP8_4 SCU_SFS(PIN_GROUP8, PIN4) +#define SCU_SFSP8_5 SCU_SFS(PIN_GROUP8, PIN5) +#define SCU_SFSP8_6 SCU_SFS(PIN_GROUP8, PIN6) +#define SCU_SFSP8_7 SCU_SFS(PIN_GROUP8, PIN7) +#define SCU_SFSP8_8 SCU_SFS(PIN_GROUP8, PIN8) + +/* Pins P9_n */ +#define SCU_SFSP9_0 SCU_SFS(PIN_GROUP9, PIN0) +#define SCU_SFSP9_1 SCU_SFS(PIN_GROUP9, PIN1) +#define SCU_SFSP9_2 SCU_SFS(PIN_GROUP9, PIN2) +#define SCU_SFSP9_3 SCU_SFS(PIN_GROUP9, PIN3) +#define SCU_SFSP9_4 SCU_SFS(PIN_GROUP9, PIN4) +#define SCU_SFSP9_5 SCU_SFS(PIN_GROUP9, PIN5) +#define SCU_SFSP9_6 SCU_SFS(PIN_GROUP9, PIN6) + +/* Pins PA_n */ +#define SCU_SFSPA_0 SCU_SFS(PIN_GROUPA, PIN0) +#define SCU_SFSPA_1 SCU_SFS(PIN_GROUPA, PIN1) +#define SCU_SFSPA_2 SCU_SFS(PIN_GROUPA, PIN2) +#define SCU_SFSPA_3 SCU_SFS(PIN_GROUPA, PIN3) +#define SCU_SFSPA_4 SCU_SFS(PIN_GROUPA, PIN4) + +/* Pins PB_n */ +#define SCU_SFSPB_0 SCU_SFS(PIN_GROUPB, PIN0) +#define SCU_SFSPB_1 SCU_SFS(PIN_GROUPB, PIN1) +#define SCU_SFSPB_2 SCU_SFS(PIN_GROUPB, PIN2) +#define SCU_SFSPB_3 SCU_SFS(PIN_GROUPB, PIN3) +#define SCU_SFSPB_4 SCU_SFS(PIN_GROUPB, PIN4) +#define SCU_SFSPB_5 SCU_SFS(PIN_GROUPB, PIN5) +#define SCU_SFSPB_6 SCU_SFS(PIN_GROUPB, PIN6) + +/* Pins PC_n */ +#define SCU_SFSPC_0 SCU_SFS(PIN_GROUPC, PIN0) +#define SCU_SFSPC_1 SCU_SFS(PIN_GROUPC, PIN1) +#define SCU_SFSPC_2 SCU_SFS(PIN_GROUPC, PIN2) +#define SCU_SFSPC_3 SCU_SFS(PIN_GROUPC, PIN3) +#define SCU_SFSPC_4 SCU_SFS(PIN_GROUPC, PIN4) +#define SCU_SFSPC_5 SCU_SFS(PIN_GROUPC, PIN5) +#define SCU_SFSPC_6 SCU_SFS(PIN_GROUPC, PIN6) +#define SCU_SFSPC_7 SCU_SFS(PIN_GROUPC, PIN7) +#define SCU_SFSPC_8 SCU_SFS(PIN_GROUPC, PIN8) +#define SCU_SFSPC_9 SCU_SFS(PIN_GROUPC, PIN9) +#define SCU_SFSPC_10 SCU_SFS(PIN_GROUPC, PIN10) +#define SCU_SFSPC_11 SCU_SFS(PIN_GROUPC, PIN11) +#define SCU_SFSPC_12 SCU_SFS(PIN_GROUPC, PIN12) +#define SCU_SFSPC_13 SCU_SFS(PIN_GROUPC, PIN13) +#define SCU_SFSPC_14 SCU_SFS(PIN_GROUPC, PIN14) + +/* Pins PD_n */ +#define SCU_SFSPD_0 SCU_SFS(PIN_GROUPD, PIN0) +#define SCU_SFSPD_1 SCU_SFS(PIN_GROUPD, PIN1) +#define SCU_SFSPD_2 SCU_SFS(PIN_GROUPD, PIN2) +#define SCU_SFSPD_3 SCU_SFS(PIN_GROUPD, PIN3) +#define SCU_SFSPD_4 SCU_SFS(PIN_GROUPD, PIN4) +#define SCU_SFSPD_5 SCU_SFS(PIN_GROUPD, PIN5) +#define SCU_SFSPD_6 SCU_SFS(PIN_GROUPD, PIN6) +#define SCU_SFSPD_7 SCU_SFS(PIN_GROUPD, PIN7) +#define SCU_SFSPD_8 SCU_SFS(PIN_GROUPD, PIN8) +#define SCU_SFSPD_9 SCU_SFS(PIN_GROUPD, PIN9) +#define SCU_SFSPD_10 SCU_SFS(PIN_GROUPD, PIN10) +#define SCU_SFSPD_11 SCU_SFS(PIN_GROUPD, PIN11) +#define SCU_SFSPD_12 SCU_SFS(PIN_GROUPD, PIN12) +#define SCU_SFSPD_13 SCU_SFS(PIN_GROUPD, PIN13) +#define SCU_SFSPD_14 SCU_SFS(PIN_GROUPD, PIN14) +#define SCU_SFSPD_15 SCU_SFS(PIN_GROUPD, PIN15) +#define SCU_SFSPD_16 SCU_SFS(PIN_GROUPD, PIN16) + +/* Pins PE_n */ +#define SCU_SFSPE_0 SCU_SFS(PIN_GROUPE, PIN0) +#define SCU_SFSPE_1 SCU_SFS(PIN_GROUPE, PIN1) +#define SCU_SFSPE_2 SCU_SFS(PIN_GROUPE, PIN2) +#define SCU_SFSPE_3 SCU_SFS(PIN_GROUPE, PIN3) +#define SCU_SFSPE_4 SCU_SFS(PIN_GROUPE, PIN4) +#define SCU_SFSPE_5 SCU_SFS(PIN_GROUPE, PIN5) +#define SCU_SFSPE_6 SCU_SFS(PIN_GROUPE, PIN6) +#define SCU_SFSPE_7 SCU_SFS(PIN_GROUPE, PIN7) +#define SCU_SFSPE_8 SCU_SFS(PIN_GROUPE, PIN8) +#define SCU_SFSPE_9 SCU_SFS(PIN_GROUPE, PIN9) +#define SCU_SFSPE_10 SCU_SFS(PIN_GROUPE, PIN10) +#define SCU_SFSPE_11 SCU_SFS(PIN_GROUPE, PIN11) +#define SCU_SFSPE_12 SCU_SFS(PIN_GROUPE, PIN12) +#define SCU_SFSPE_13 SCU_SFS(PIN_GROUPE, PIN13) +#define SCU_SFSPE_14 SCU_SFS(PIN_GROUPE, PIN14) +#define SCU_SFSPE_15 SCU_SFS(PIN_GROUPE, PIN15) + +/* Pins PF_n */ +#define SCU_SFSPF_0 SCU_SFS(PIN_GROUPF, PIN0) +#define SCU_SFSPF_1 SCU_SFS(PIN_GROUPF, PIN1) +#define SCU_SFSPF_2 SCU_SFS(PIN_GROUPF, PIN2) +#define SCU_SFSPF_3 SCU_SFS(PIN_GROUPF, PIN3) +#define SCU_SFSPF_4 SCU_SFS(PIN_GROUPF, PIN4) +#define SCU_SFSPF_5 SCU_SFS(PIN_GROUPF, PIN5) +#define SCU_SFSPF_6 SCU_SFS(PIN_GROUPF, PIN6) +#define SCU_SFSPF_7 SCU_SFS(PIN_GROUPF, PIN7) +#define SCU_SFSPF_8 SCU_SFS(PIN_GROUPF, PIN8) +#define SCU_SFSPF_9 SCU_SFS(PIN_GROUPF, PIN9) +#define SCU_SFSPF_10 SCU_SFS(PIN_GROUPF, PIN10) +#define SCU_SFSPF_11 SCU_SFS(PIN_GROUPF, PIN11) + +/* CLKn pins */ +#define SCU_SFSCLK0 MMIO32(SCU_BASE + 0xC00) +#define SCU_SFSCLK1 MMIO32(SCU_BASE + 0xC04) +#define SCU_SFSCLK2 MMIO32(SCU_BASE + 0xC08) +#define SCU_SFSCLK3 MMIO32(SCU_BASE + 0xC0C) + +/* USB1 USB1_DP/USB1_DM pins and I2C-bus open-drain pins */ +#define SCU_SFSUSB MMIO32(SCU_BASE + 0xC80) +#define SCU_SFSI2C0 MMIO32(SCU_BASE + 0xC84) + +/* ADC pin select registers */ + +/* ADC0 function select register */ +#define SCU_ENAIO0 MMIO32(SCU_BASE + 0xC88) + +/* ADC1 function select register */ +#define SCU_ENAIO1 MMIO32(SCU_BASE + 0xC8C) + +/* Analog function select register */ +#define SCU_ENAIO2 MMIO32(SCU_BASE + 0xC90) + +/* EMC clock delay register */ +#define SCU_EMCDELAYCLK MMIO32(SCU_BASE + 0xD00) + +/* Pin interrupt select registers */ + +/* Pin interrupt select register for pin interrupts 0 to 3 */ +#define SCU_PINTSEL0 MMIO32(SCU_BASE + 0xE00) + +/* Pin interrupt select register for pin interrupts 4 to 7 */ +#define SCU_PINTSEL1 MMIO32(SCU_BASE + 0xE04) + +/**************************/ +/* SCU I2C0 Configuration */ +/**************************/ +/* +* Select input glitch filter time constant for the SCL pin. +* 0 = 50 ns glitch filter. +* 1 = 3ns glitch filter. +*/ +#define SCU_SCL_EFP (BIT0) + +/* BIT1 Reserved. Always write a 0 to this bit. */ + +/* +* Select I2C mode for the SCL pin. +* 0 = Standard/Fast mode transmit. +* 1 = Fast-mode Plus transmit. +*/ +#define SCU_SCL_EHD (BIT2) + +/* +* Enable the input receiver for the SCL pin. +* Always write a 1 to this bit when using the +* I2C0. +* 0 = Disabled. +* 1 = Enabled. +*/ +#define SCU_SCL_EZI_EN (BIT3) + +/* BIT4-6 Reserved. */ + +/* +* Enable or disable input glitch filter for the +* SCL pin. The filter time constant is +* determined by bit EFP. +* 0 = Enable input filter. +* 1 = Disable input filter. +*/ +#define SCU_SCL_ZIF_DIS (BIT7) + +/* +* Select input glitch filter time constant for the SDA pin. +* 0 = 50 ns glitch filter. +* 1 = 3ns glitch filter. +*/ +#define SCU_SDA_EFP (BIT8) + +/* BIT9 Reserved. Always write a 0 to this bit. */ + +/* +* Select I2C mode for the SDA pin. +* 0 = Standard/Fast mode transmit. +* 1 = Fast-mode Plus transmit. +*/ +#define SCU_SDA_EHD (BIT10) + +/* +* Enable the input receiver for the SDA pin. +* Always write a 1 to this bit when using the +* I2C0. +* 0 = Disabled. +* 1 = Enabled. +*/ +#define SCU_SDA_EZI_EN (BIT11) + +/* BIT 12-14 - Reserved */ + +/* +* Enable or disable input glitch filter for the +* SDA pin. The filter time constant is +* determined by bit SDA_EFP. +* 0 = Enable input filter. +* 1 = Disable input filter. +*/ +#define SCU_SDA_ZIF_DIS (BIT15) + +/* Standard mode for I2C SCL/SDA Standard/Fast mode */ +#define SCU_I2C0_NOMINAL (SCU_SCL_EZI_EN | SCU_SDA_EZI_EN) + +/* Standard mode for I2C SCL/SDA Fast-mode Plus transmit */ +#define SCU_I2C0_FAST (SCU_SCL_EFP | SCU_SCL_EHD | SCU_SCL_EZI_EN | \ + SCU_SCL_ZIF_DIS | SCU_SDA_EFP | SCU_SDA_EHD | \ + SCU_SDA_EZI_EN) + +/* +* SCU PIN Normal Drive: +* The configuration registers for normal-drive pins control the following pins: +* - P0_0 and P0_1 +* - P1_0 to P1_16 and P1_18 to P1_20 +* - P2_0 to P2_2 and P2_6 to P2_13 +* - P3_0 to P3_2 and P3_4 to P3_8 +* - P4_0 to P4_10 +* - P5_0 to P5_7 +* - P6_0 to P6_12 +* - P7_0 to P7_7 +* - P8_3 to P8_8 +* - P9_0 to P9_6 +* - PA_0 and PA_4 +* - PB_0 to PB_6 +* - PC_0 to PC_14 +* - PE_0 to PE_15 +* - PF_0 to PF_11 +* +* Pin configuration registers for High-Drive pins. +* The configuration registers for high-drive pins control the following pins: +* - P1_17 +* - P2_3 to P2_5 +* - P8_0 to P8_2 +* - PA_1 to PA_3 +* +* Pin configuration registers for High-Speed pins. +* This register controls the following pins: +* - P3_3 and pins CLK0 to CLK3. +*/ +typedef enum { + /* Group Port 0 */ + P0_0 = (PIN_GROUP0+PIN0), + P0_1 = (PIN_GROUP0+PIN1), + + /* Group Port 1 */ + P1_0 = (PIN_GROUP1+PIN0), + P1_1 = (PIN_GROUP1+PIN1), + P1_2 = (PIN_GROUP1+PIN2), + P1_3 = (PIN_GROUP1+PIN3), + P1_4 = (PIN_GROUP1+PIN4), + P1_5 = (PIN_GROUP1+PIN5), + P1_6 = (PIN_GROUP1+PIN6), + P1_7 = (PIN_GROUP1+PIN7), + P1_8 = (PIN_GROUP1+PIN8), + P1_9 = (PIN_GROUP1+PIN9), + P1_10 = (PIN_GROUP1+PIN10), + P1_11 = (PIN_GROUP1+PIN11), + P1_12 = (PIN_GROUP1+PIN12), + P1_13 = (PIN_GROUP1+PIN13), + P1_14 = (PIN_GROUP1+PIN14), + P1_15 = (PIN_GROUP1+PIN15), + P1_16 = (PIN_GROUP1+PIN16), + + /* P1_17 is High-Drive pin */ + P1_17 = (PIN_GROUP1+PIN17), + + P1_18 = (PIN_GROUP1+PIN18), + P1_19 = (PIN_GROUP1+PIN19), + P1_20 = (PIN_GROUP1+PIN20), + + /* Group Port 2 */ + P2_0 = (PIN_GROUP2+PIN0), + P2_1 = (PIN_GROUP2+PIN1), + P2_2 = (PIN_GROUP2+PIN2), + + /* P2_3 to P2_5 are High-Drive pins */ + P2_3 = (PIN_GROUP2+PIN3), + P2_4 = (PIN_GROUP2+PIN4), + P2_5 = (PIN_GROUP2+PIN5), + + P2_6 = (PIN_GROUP2+PIN6), + P2_7 = (PIN_GROUP2+PIN7), + P2_8 = (PIN_GROUP2+PIN8), + P2_9 = (PIN_GROUP2+PIN9), + P2_10 = (PIN_GROUP2+PIN10), + P2_11 = (PIN_GROUP2+PIN11), + P2_12 = (PIN_GROUP2+PIN12), + P2_13 = (PIN_GROUP2+PIN13), + + /* Group Port 3 */ + P3_0 = (PIN_GROUP3+PIN0), + P3_1 = (PIN_GROUP3+PIN1), + P3_2 = (PIN_GROUP3+PIN2), + + /* P3_3 is High-Speed pin */ + P3_3 = (PIN_GROUP3+PIN3), + + P3_4 = (PIN_GROUP3+PIN4), + P3_5 = (PIN_GROUP3+PIN5), + P3_6 = (PIN_GROUP3+PIN6), + P3_7 = (PIN_GROUP3+PIN7), + P3_8 = (PIN_GROUP3+PIN8), + + /* Group Port 4 */ + P4_0 = (PIN_GROUP4+PIN0), + P4_1 = (PIN_GROUP4+PIN1), + P4_2 = (PIN_GROUP4+PIN2), + P4_3 = (PIN_GROUP4+PIN3), + P4_4 = (PIN_GROUP4+PIN4), + P4_5 = (PIN_GROUP4+PIN5), + P4_6 = (PIN_GROUP4+PIN6), + P4_7 = (PIN_GROUP4+PIN7), + P4_8 = (PIN_GROUP4+PIN8), + P4_9 = (PIN_GROUP4+PIN9), + P4_10 = (PIN_GROUP4+PIN10), + + /* Group Port 5 */ + P5_0 = (PIN_GROUP5+PIN0), + P5_1 = (PIN_GROUP5+PIN1), + P5_2 = (PIN_GROUP5+PIN2), + P5_3 = (PIN_GROUP5+PIN3), + P5_4 = (PIN_GROUP5+PIN4), + P5_5 = (PIN_GROUP5+PIN5), + P5_6 = (PIN_GROUP5+PIN6), + P5_7 = (PIN_GROUP5+PIN7), + + /* Group Port 6 */ + P6_0 = (PIN_GROUP6+PIN0), + P6_1 = (PIN_GROUP6+PIN1), + P6_2 = (PIN_GROUP6+PIN2), + P6_3 = (PIN_GROUP6+PIN3), + P6_4 = (PIN_GROUP6+PIN4), + P6_5 = (PIN_GROUP6+PIN5), + P6_6 = (PIN_GROUP6+PIN6), + P6_7 = (PIN_GROUP6+PIN7), + P6_8 = (PIN_GROUP6+PIN8), + P6_9 = (PIN_GROUP6+PIN9), + P6_10 = (PIN_GROUP6+PIN10), + P6_11 = (PIN_GROUP6+PIN11), + P6_12 = (PIN_GROUP6+PIN12), + + /* Group Port 7 */ + P7_0 = (PIN_GROUP7+PIN0), + P7_1 = (PIN_GROUP7+PIN1), + P7_2 = (PIN_GROUP7+PIN2), + P7_3 = (PIN_GROUP7+PIN3), + P7_4 = (PIN_GROUP7+PIN4), + P7_5 = (PIN_GROUP7+PIN5), + P7_6 = (PIN_GROUP7+PIN6), + P7_7 = (PIN_GROUP7+PIN7), + + /* Group Port 8 */ + /* P8_0 to P8_2 are High-Drive pins */ + P8_0 = (PIN_GROUP8+PIN0), + P8_1 = (PIN_GROUP8+PIN1), + P8_2 = (PIN_GROUP8+PIN2), + + P8_3 = (PIN_GROUP8+PIN3), + P8_4 = (PIN_GROUP8+PIN4), + P8_5 = (PIN_GROUP8+PIN5), + P8_6 = (PIN_GROUP8+PIN6), + P8_7 = (PIN_GROUP8+PIN7), + P8_8 = (PIN_GROUP8+PIN8), + + /* Group Port 9 */ + P9_0 = (PIN_GROUP9+PIN0), + P9_1 = (PIN_GROUP9+PIN1), + P9_2 = (PIN_GROUP9+PIN2), + P9_3 = (PIN_GROUP9+PIN3), + P9_4 = (PIN_GROUP9+PIN4), + P9_5 = (PIN_GROUP9+PIN5), + P9_6 = (PIN_GROUP9+PIN6), + + /* Group Port A */ + PA_0 = (PIN_GROUPA+PIN0), + /* PA_1 to PA_3 are Normal & High-Drive Pins */ + PA_1 = (PIN_GROUPA+PIN1), + PA_2 = (PIN_GROUPA+PIN2), + PA_3 = (PIN_GROUPA+PIN3), + PA_4 = (PIN_GROUPA+PIN4), + + /* Group Port B */ + PB_0 = (PIN_GROUPB+PIN0), + PB_1 = (PIN_GROUPB+PIN1), + PB_2 = (PIN_GROUPB+PIN2), + PB_3 = (PIN_GROUPB+PIN3), + PB_4 = (PIN_GROUPB+PIN4), + PB_5 = (PIN_GROUPB+PIN5), + PB_6 = (PIN_GROUPB+PIN6), + + /* Group Port C */ + PC_0 = (PIN_GROUPC+PIN0), + PC_1 = (PIN_GROUPC+PIN1), + PC_2 = (PIN_GROUPC+PIN2), + PC_3 = (PIN_GROUPC+PIN3), + PC_4 = (PIN_GROUPC+PIN4), + PC_5 = (PIN_GROUPC+PIN5), + PC_6 = (PIN_GROUPC+PIN6), + PC_7 = (PIN_GROUPC+PIN7), + PC_8 = (PIN_GROUPC+PIN8), + PC_9 = (PIN_GROUPC+PIN9), + PC_10 = (PIN_GROUPC+PIN10), + PC_11 = (PIN_GROUPC+PIN11), + PC_12 = (PIN_GROUPC+PIN12), + PC_13 = (PIN_GROUPC+PIN13), + PC_14 = (PIN_GROUPC+PIN14), + + /* Group Port D (seems not configurable through SCU, not defined in + * UM10503.pdf Rev.1, keep it here) + */ + PD_0 = (PIN_GROUPD+PIN0), + PD_1 = (PIN_GROUPD+PIN1), + PD_2 = (PIN_GROUPD+PIN2), + PD_3 = (PIN_GROUPD+PIN3), + PD_4 = (PIN_GROUPD+PIN4), + PD_5 = (PIN_GROUPD+PIN5), + PD_6 = (PIN_GROUPD+PIN6), + PD_7 = (PIN_GROUPD+PIN7), + PD_8 = (PIN_GROUPD+PIN8), + PD_9 = (PIN_GROUPD+PIN9), + PD_10 = (PIN_GROUPD+PIN10), + PD_11 = (PIN_GROUPD+PIN11), + PD_12 = (PIN_GROUPD+PIN12), + PD_13 = (PIN_GROUPD+PIN13), + PD_14 = (PIN_GROUPD+PIN14), + PD_15 = (PIN_GROUPD+PIN15), + PD_16 = (PIN_GROUPD+PIN16), + + /* Group Port E */ + PE_0 = (PIN_GROUPE+PIN0), + PE_1 = (PIN_GROUPE+PIN1), + PE_2 = (PIN_GROUPE+PIN2), + PE_3 = (PIN_GROUPE+PIN3), + PE_4 = (PIN_GROUPE+PIN4), + PE_5 = (PIN_GROUPE+PIN5), + PE_6 = (PIN_GROUPE+PIN6), + PE_7 = (PIN_GROUPE+PIN7), + PE_8 = (PIN_GROUPE+PIN8), + PE_9 = (PIN_GROUPE+PIN9), + PE_10 = (PIN_GROUPE+PIN10), + PE_11 = (PIN_GROUPE+PIN11), + PE_12 = (PIN_GROUPE+PIN12), + PE_13 = (PIN_GROUPE+PIN13), + PE_14 = (PIN_GROUPE+PIN14), + PE_15 = (PIN_GROUPE+PIN15), + + /* Group Port F */ + PF_0 = (PIN_GROUPF+PIN0), + PF_1 = (PIN_GROUPF+PIN1), + PF_2 = (PIN_GROUPF+PIN2), + PF_3 = (PIN_GROUPF+PIN3), + PF_4 = (PIN_GROUPF+PIN4), + PF_5 = (PIN_GROUPF+PIN5), + PF_6 = (PIN_GROUPF+PIN6), + PF_7 = (PIN_GROUPF+PIN7), + PF_8 = (PIN_GROUPF+PIN8), + PF_9 = (PIN_GROUPF+PIN9), + PF_10 = (PIN_GROUPF+PIN10), + PF_11 = (PIN_GROUPF+PIN11), + + /* Group Clock 0 to 3 High-Speed pins */ + CLK0 = (SCU_BASE + 0xC00), + CLK1 = (SCU_BASE + 0xC04), + CLK2 = (SCU_BASE + 0xC08), + CLK3 = (SCU_BASE + 0xC0C) + +} scu_grp_pin_t; + +/* +* Pin Configuration to be used for scu_pinmux() parameter scu_conf +* For normal-drive pins, high-drive pins, high-speed pins +*/ +/* +* Function BIT0 to 2. +* Common to normal-drive pins, high-drive pins, high-speed pins. +*/ +#define SCU_CONF_FUNCTION0 (0x0) +#define SCU_CONF_FUNCTION1 (0x1) +#define SCU_CONF_FUNCTION2 (0x2) +#define SCU_CONF_FUNCTION3 (0x3) +#define SCU_CONF_FUNCTION4 (0x4) +#define SCU_CONF_FUNCTION5 (0x5) +#define SCU_CONF_FUNCTION6 (0x6) +#define SCU_CONF_FUNCTION7 (0x7) + +/* +* Enable pull-down resistor at pad +* By default=0 Disable pull-down. +* Available to normal-drive pins, high-drive pins, high-speed pins +*/ +#define SCU_CONF_EPD_EN_PULLDOWN (BIT3) + +/* +* Disable pull-up resistor at pad. +* By default=0 the pull-up resistor is enabled at reset. +* Available to normal-drive pins, high-drive pins, high-speed pins +*/ +#define SCU_CONF_EPUN_DIS_PULLUP (BIT4) + +/* +* Select Slew Rate. +* By Default=0 Slow. +* Available to normal-drive and high-speed pins, reserved for high-drive pins. +*/ +#define SCU_CONF_EHS_FAST (BIT5) + +/* +* Input buffer enable. +* By Default=0 Disable Input Buffer. +* The input buffer is disabled by default at reset and must be enabled for +* receiving(in normal/highspeed-drive) or to transfer data from the I/O buffer +* to the pad(in high-drive pins). +* Available to normal-drive pins, high-drive pins, high-speed pins. +*/ +#define SCU_CONF_EZI_EN_IN_BUFFER (BIT6) + +/* +* Input glitch filter. Disable the input glitch filter for clocking signals +* higher than 30 MHz. +* Available to normal-drive pins, high-drive pins, high-speed pins. +*/ +#define SCU_CONF_ZIF_DIS_IN_GLITCH_FILT (BIT7) + +/* +* Select drive strength. (default=0 Normal-drive: 4 mA drive strength) (BIT8/9). +* Available to high-drive pins, reserved for others. +*/ +#define SCU_CONF_EHD_NORMAL_DRIVE_8MILLIA (0x100) +#define SCU_CONF_EHD_NORMAL_DRIVE_14MILLIA (0x200) +#define SCU_CONF_EHD_NORMAL_DRIVE_20MILLIA (0x300) + +/* BIT10 to 31 are Reserved */ + +/* Configuration for different I/O pins types */ +#define SCU_EMC_IO (SCU_CONF_EPD_EN_PULLDOWN | \ + SCU_CONF_EHS_FAST | \ + SCU_CONF_EZI_EN_IN_BUFFER | \ + SCU_CONF_ZIF_DIS_IN_GLITCH_FILT) +#define SCU_LCD (SCU_CONF_EPUN_DIS_PULLUP | \ + SCU_CONF_EHS_FAST | \ + SCU_CONF_EZI_EN_IN_BUFFER | \ + SCU_CONF_ZIF_DIS_IN_GLITCH_FILT) +#define SCU_CLK_IN (SCU_CONF_EPD_EN_PULLDOWN | \ + SCU_CONF_EHS_FAST | \ + SCU_CONF_EZI_EN_IN_BUFFER | \ + SCU_CONF_ZIF_DIS_IN_GLITCH_FILT) +#define SCU_CLK_OUT (SCU_CONF_EPD_EN_PULLDOWN | \ + SCU_CONF_EHS_FAST | \ + SCU_CONF_EZI_EN_IN_BUFFER | \ + SCU_CONF_ZIF_DIS_IN_GLITCH_FILT) +#define SCU_GPIO_PUP (SCU_CONF_EZI_EN_IN_BUFFER) +#define SCU_GPIO_PDN (SCU_CONF_EPUN_DIS_PULLUP | \ + SCU_CONF_EPD_EN_PULLDOWN | \ + SCU_CONF_EZI_EN_IN_BUFFER) +#define SCU_GPIO_NOPULL (SCU_CONF_EPUN_DIS_PULLUP | \ + SCU_CONF_EZI_EN_IN_BUFFER) +#define SCU_GPIO_FAST (SCU_CONF_EPUN_DIS_PULLUP | \ + SCU_CONF_EHS_FAST | \ + SCU_CONF_EZI_EN_IN_BUFFER | \ + SCU_CONF_ZIF_DIS_IN_GLITCH_FILT) +#define SCU_UART_RX_TX (SCU_CONF_EPUN_DIS_PULLUP | \ + SCU_CONF_EPD_EN_PULLDOWN | \ + SCU_CONF_EZI_EN_IN_BUFFER) +#define SCU_SSP_IO (SCU_CONF_EPUN_DIS_PULLUP | \ + SCU_CONF_EHS_FAST | \ + SCU_CONF_EZI_EN_IN_BUFFER | \ + SCU_CONF_ZIF_DIS_IN_GLITCH_FILT) + +BEGIN_DECLS + +void scu_pinmux(scu_grp_pin_t group_pin, uint32_t scu_conf); + +END_DECLS + +/**@}*/ + +#endif diff --git a/libopencm3/include/libopencm3/lpc43xx/sdio.h b/libopencm3/include/libopencm3/lpc43xx/sdio.h new file mode 100644 index 0000000..164dda4 --- /dev/null +++ b/libopencm3/include/libopencm3/lpc43xx/sdio.h @@ -0,0 +1,151 @@ +/** @defgroup sdio_defines SDIO + +@brief <b>Defined Constants and Types for the LPC43xx SDIO</b> + +@ingroup LPC43xx_defines + +@version 1.0.0 + +@author @htmlonly © @endhtmlonly 2012 Michael Ossmann <mike@ossmann.com> + +@date 10 March 2013 + +LGPL License Terms @ref lgpl_license + */ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2012 Michael Ossmann <mike@ossmann.com> + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see <http://www.gnu.org/licenses/>. + */ + +#ifndef LPC43XX_SDIO_H +#define LPC43XX_SDIO_H + +/**@{*/ + +#include <libopencm3/cm3/common.h> +#include <libopencm3/lpc43xx/memorymap.h> + +/* --- SDIO registers ----------------------------------------------------- */ + +/* Control Register */ +#define SDIO_CTRL MMIO32(SDIO_BASE + 0x000) + +/* Power Enable Register */ +#define SDIO_PWREN MMIO32(SDIO_BASE + 0x004) + +/* Clock Divider Register */ +#define SDIO_CLKDIV MMIO32(SDIO_BASE + 0x008) + +/* SD Clock Source Register */ +#define SDIO_CLKSRC MMIO32(SDIO_BASE + 0x00C) + +/* Clock Enable Register */ +#define SDIO_CLKENA MMIO32(SDIO_BASE + 0x010) + +/* Time-out Register */ +#define SDIO_TMOUT MMIO32(SDIO_BASE + 0x014) + +/* Card Type Register */ +#define SDIO_CTYPE MMIO32(SDIO_BASE + 0x018) + +/* Block Size Register */ +#define SDIO_BLKSIZ MMIO32(SDIO_BASE + 0x01C) + +/* Byte Count Register */ +#define SDIO_BYTCNT MMIO32(SDIO_BASE + 0x020) + +/* Interrupt Mask Register */ +#define SDIO_INTMASK MMIO32(SDIO_BASE + 0x024) + +/* Command Argument Register */ +#define SDIO_CMDARG MMIO32(SDIO_BASE + 0x028) + +/* Command Register */ +#define SDIO_CMD MMIO32(SDIO_BASE + 0x02C) + +/* Response Register 0 */ +#define SDIO_RESP0 MMIO32(SDIO_BASE + 0x030) + +/* Response Register 1 */ +#define SDIO_RESP1 MMIO32(SDIO_BASE + 0x034) + +/* Response Register 2 */ +#define SDIO_RESP2 MMIO32(SDIO_BASE + 0x038) + +/* Response Register 3 */ +#define SDIO_RESP3 MMIO32(SDIO_BASE + 0x03C) + +/* Masked Interrupt Status Register */ +#define SDIO_MINTSTS MMIO32(SDIO_BASE + 0x040) + +/* Raw Interrupt Status Register */ +#define SDIO_RINTSTS MMIO32(SDIO_BASE + 0x044) + +/* Status Register */ +#define SDIO_STATUS MMIO32(SDIO_BASE + 0x048) + +/* FIFO Threshold Watermark Register */ +#define SDIO_FIFOTH MMIO32(SDIO_BASE + 0x04C) + +/* Card Detect Register */ +#define SDIO_CDETECT MMIO32(SDIO_BASE + 0x050) + +/* Write Protect Register */ +#define SDIO_WRTPRT MMIO32(SDIO_BASE + 0x054) + +/* Transferred CIU Card Byte Count Register */ +#define SDIO_TCBCNT MMIO32(SDIO_BASE + 0x05C) + +/* Transferred Host to BIU-FIFO Byte Count Register */ +#define SDIO_TBBCNT MMIO32(SDIO_BASE + 0x060) + +/* Debounce Count Register */ +#define SDIO_DEBNCE MMIO32(SDIO_BASE + 0x064) + +/* UHS-1 Register */ +#define SDIO_UHS_REG MMIO32(SDIO_BASE + 0x074) + +/* Hardware Reset */ +#define SDIO_RST_N MMIO32(SDIO_BASE + 0x078) + +/* Bus Mode Register */ +#define SDIO_BMOD MMIO32(SDIO_BASE + 0x080) + +/* Poll Demand Register */ +#define SDIO_PLDMND MMIO32(SDIO_BASE + 0x084) + +/* Descriptor List Base Address Register */ +#define SDIO_DBADDR MMIO32(SDIO_BASE + 0x088) + +/* Internal DMAC Status Register */ +#define SDIO_IDSTS MMIO32(SDIO_BASE + 0x08C) + +/* Internal DMAC Interrupt Enable Register */ +#define SDIO_IDINTEN MMIO32(SDIO_BASE + 0x090) + +/* Current Host Descriptor Address Register */ +#define SDIO_DSCADDR MMIO32(SDIO_BASE + 0x094) + +/* Current Buffer Descriptor Address Register */ +#define SDIO_BUFADDR MMIO32(SDIO_BASE + 0x098) + +/* Data FIFO read/write */ +#define SDIO_DATA MMIO32(SDIO_BASE + 0x100) + +/**@}*/ + +#endif diff --git a/libopencm3/include/libopencm3/lpc43xx/sgpio.h b/libopencm3/include/libopencm3/lpc43xx/sgpio.h new file mode 100644 index 0000000..4b8d5b6 --- /dev/null +++ b/libopencm3/include/libopencm3/lpc43xx/sgpio.h @@ -0,0 +1,691 @@ +/** @defgroup sgpio_defines Serial General Purpose I/O + +@brief <b>Defined Constants and Types for the LPC43xx Serial General Purpose +I/O</b> + +@ingroup LPC43xx_defines + +@version 1.0.0 + +@author @htmlonly © @endhtmlonly 2012 Michael Ossmann <mike@ossmann.com> + +@date 10 March 2013 + +LGPL License Terms @ref lgpl_license + */ +/** @defgroup sdio_defines SDIO + +@brief <b>Defined Constants and Types for the LPC43xx SDIO</b> + +@ingroup LPC43xx_defines + +@version 1.0.0 + +@author @htmlonly © @endhtmlonly 2012 Michael Ossmann <mike@ossmann.com> + +@date 10 March 2013 + +LGPL License Terms @ref lgpl_license + */ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2012 Michael Ossmann <mike@ossmann.com> + * Copyright (C) 2012 Jared Boone <jared@sharebrained.com> + * Copyright (C) 2012 Benjamin Vernoux <titanmkd@gmail.com> + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see <http://www.gnu.org/licenses/>. + */ + +#ifndef LPC43XX_SGPIO_H +#define LPC43XX_SGPIO_H + +/**@{*/ + +#include <libopencm3/cm3/common.h> +#include <libopencm3/lpc43xx/memorymap.h> + +/* --- SGPIO registers ----------------------------------------------------- */ + +/* Pin multiplexer configuration registers (OUT_MUX_CFG0 to 15) */ +#define SGPIO_OUT_MUX_CFG(pin) MMIO32(SGPIO_PORT_BASE + (pin * 0x04)) +#define SGPIO_OUT_MUX_CFG0 MMIO32(SGPIO_PORT_BASE + 0x00) +#define SGPIO_OUT_MUX_CFG1 MMIO32(SGPIO_PORT_BASE + 0x04) +#define SGPIO_OUT_MUX_CFG2 MMIO32(SGPIO_PORT_BASE + 0x08) +#define SGPIO_OUT_MUX_CFG3 MMIO32(SGPIO_PORT_BASE + 0x0C) +#define SGPIO_OUT_MUX_CFG4 MMIO32(SGPIO_PORT_BASE + 0x10) +#define SGPIO_OUT_MUX_CFG5 MMIO32(SGPIO_PORT_BASE + 0x14) +#define SGPIO_OUT_MUX_CFG6 MMIO32(SGPIO_PORT_BASE + 0x18) +#define SGPIO_OUT_MUX_CFG7 MMIO32(SGPIO_PORT_BASE + 0x1C) +#define SGPIO_OUT_MUX_CFG8 MMIO32(SGPIO_PORT_BASE + 0x20) +#define SGPIO_OUT_MUX_CFG9 MMIO32(SGPIO_PORT_BASE + 0x24) +#define SGPIO_OUT_MUX_CFG10 MMIO32(SGPIO_PORT_BASE + 0x28) +#define SGPIO_OUT_MUX_CFG11 MMIO32(SGPIO_PORT_BASE + 0x2C) +#define SGPIO_OUT_MUX_CFG12 MMIO32(SGPIO_PORT_BASE + 0x30) +#define SGPIO_OUT_MUX_CFG13 MMIO32(SGPIO_PORT_BASE + 0x34) +#define SGPIO_OUT_MUX_CFG14 MMIO32(SGPIO_PORT_BASE + 0x38) +#define SGPIO_OUT_MUX_CFG15 MMIO32(SGPIO_PORT_BASE + 0x3C) + +/* SGPIO multiplexer configuration registers (SGPIO_MUX_CFG0 to 15) */ +#define SGPIO_MUX_CFG(slice) MMIO32(SGPIO_PORT_BASE + 0x40 + \ + (slice * 0x04)) +#define SGPIO_MUX_CFG0 MMIO32(SGPIO_PORT_BASE + 0x40) +#define SGPIO_MUX_CFG1 MMIO32(SGPIO_PORT_BASE + 0x44) +#define SGPIO_MUX_CFG2 MMIO32(SGPIO_PORT_BASE + 0x48) +#define SGPIO_MUX_CFG3 MMIO32(SGPIO_PORT_BASE + 0x4C) +#define SGPIO_MUX_CFG4 MMIO32(SGPIO_PORT_BASE + 0x50) +#define SGPIO_MUX_CFG5 MMIO32(SGPIO_PORT_BASE + 0x54) +#define SGPIO_MUX_CFG6 MMIO32(SGPIO_PORT_BASE + 0x58) +#define SGPIO_MUX_CFG7 MMIO32(SGPIO_PORT_BASE + 0x5C) +#define SGPIO_MUX_CFG8 MMIO32(SGPIO_PORT_BASE + 0x60) +#define SGPIO_MUX_CFG9 MMIO32(SGPIO_PORT_BASE + 0x64) +#define SGPIO_MUX_CFG10 MMIO32(SGPIO_PORT_BASE + 0x68) +#define SGPIO_MUX_CFG11 MMIO32(SGPIO_PORT_BASE + 0x6C) +#define SGPIO_MUX_CFG12 MMIO32(SGPIO_PORT_BASE + 0x70) +#define SGPIO_MUX_CFG13 MMIO32(SGPIO_PORT_BASE + 0x74) +#define SGPIO_MUX_CFG14 MMIO32(SGPIO_PORT_BASE + 0x78) +#define SGPIO_MUX_CFG15 MMIO32(SGPIO_PORT_BASE + 0x7C) + +/* Slice multiplexer configuration registers (SLICE_MUX_CFG0 to 15) */ +#define SGPIO_SLICE_MUX_CFG(slice) MMIO32(SGPIO_PORT_BASE + 0x80 + \ + (slice * 0x04)) +#define SGPIO_SLICE_MUX_CFG0 MMIO32(SGPIO_PORT_BASE + 0x80) +#define SGPIO_SLICE_MUX_CFG1 MMIO32(SGPIO_PORT_BASE + 0x84) +#define SGPIO_SLICE_MUX_CFG2 MMIO32(SGPIO_PORT_BASE + 0x88) +#define SGPIO_SLICE_MUX_CFG3 MMIO32(SGPIO_PORT_BASE + 0x8C) +#define SGPIO_SLICE_MUX_CFG4 MMIO32(SGPIO_PORT_BASE + 0x90) +#define SGPIO_SLICE_MUX_CFG5 MMIO32(SGPIO_PORT_BASE + 0x94) +#define SGPIO_SLICE_MUX_CFG6 MMIO32(SGPIO_PORT_BASE + 0x98) +#define SGPIO_SLICE_MUX_CFG7 MMIO32(SGPIO_PORT_BASE + 0x9C) +#define SGPIO_SLICE_MUX_CFG8 MMIO32(SGPIO_PORT_BASE + 0xA0) +#define SGPIO_SLICE_MUX_CFG9 MMIO32(SGPIO_PORT_BASE + 0xA4) +#define SGPIO_SLICE_MUX_CFG10 MMIO32(SGPIO_PORT_BASE + 0xA8) +#define SGPIO_SLICE_MUX_CFG11 MMIO32(SGPIO_PORT_BASE + 0xAC) +#define SGPIO_SLICE_MUX_CFG12 MMIO32(SGPIO_PORT_BASE + 0xB0) +#define SGPIO_SLICE_MUX_CFG13 MMIO32(SGPIO_PORT_BASE + 0xB4) +#define SGPIO_SLICE_MUX_CFG14 MMIO32(SGPIO_PORT_BASE + 0xB8) +#define SGPIO_SLICE_MUX_CFG15 MMIO32(SGPIO_PORT_BASE + 0xBC) + +/* Slice data registers (REG0 to 15) */ +#define SGPIO_REG(slice) MMIO32(SGPIO_PORT_BASE + 0xC0 + \ + (slice * 0x04)) +#define SGPIO_REG0 MMIO32(SGPIO_PORT_BASE + 0xC0) +#define SGPIO_REG1 MMIO32(SGPIO_PORT_BASE + 0xC4) +#define SGPIO_REG2 MMIO32(SGPIO_PORT_BASE + 0xC8) +#define SGPIO_REG3 MMIO32(SGPIO_PORT_BASE + 0xCC) +#define SGPIO_REG4 MMIO32(SGPIO_PORT_BASE + 0xD0) +#define SGPIO_REG5 MMIO32(SGPIO_PORT_BASE + 0xD4) +#define SGPIO_REG6 MMIO32(SGPIO_PORT_BASE + 0xD8) +#define SGPIO_REG7 MMIO32(SGPIO_PORT_BASE + 0xDC) +#define SGPIO_REG8 MMIO32(SGPIO_PORT_BASE + 0xE0) +#define SGPIO_REG9 MMIO32(SGPIO_PORT_BASE + 0xE4) +#define SGPIO_REG10 MMIO32(SGPIO_PORT_BASE + 0xE8) +#define SGPIO_REG11 MMIO32(SGPIO_PORT_BASE + 0xEC) +#define SGPIO_REG12 MMIO32(SGPIO_PORT_BASE + 0xF0) +#define SGPIO_REG13 MMIO32(SGPIO_PORT_BASE + 0xF4) +#define SGPIO_REG14 MMIO32(SGPIO_PORT_BASE + 0xF8) +#define SGPIO_REG15 MMIO32(SGPIO_PORT_BASE + 0xFC) + +/* Slice data shadow registers (REG_SS0 to 15) */ +#define SGPIO_REG_SS(slice) MMIO32(SGPIO_PORT_BASE + 0x100 + \ + (slice * 0x04)) +#define SGPIO_REG_SS0 MMIO32(SGPIO_PORT_BASE + 0x100) +#define SGPIO_REG_SS1 MMIO32(SGPIO_PORT_BASE + 0x104) +#define SGPIO_REG_SS2 MMIO32(SGPIO_PORT_BASE + 0x108) +#define SGPIO_REG_SS3 MMIO32(SGPIO_PORT_BASE + 0x10C) +#define SGPIO_REG_SS4 MMIO32(SGPIO_PORT_BASE + 0x110) +#define SGPIO_REG_SS5 MMIO32(SGPIO_PORT_BASE + 0x114) +#define SGPIO_REG_SS6 MMIO32(SGPIO_PORT_BASE + 0x118) +#define SGPIO_REG_SS7 MMIO32(SGPIO_PORT_BASE + 0x11C) +#define SGPIO_REG_SS8 MMIO32(SGPIO_PORT_BASE + 0x120) +#define SGPIO_REG_SS9 MMIO32(SGPIO_PORT_BASE + 0x124) +#define SGPIO_REG_SS10 MMIO32(SGPIO_PORT_BASE + 0x128) +#define SGPIO_REG_SS11 MMIO32(SGPIO_PORT_BASE + 0x12C) +#define SGPIO_REG_SS12 MMIO32(SGPIO_PORT_BASE + 0x130) +#define SGPIO_REG_SS13 MMIO32(SGPIO_PORT_BASE + 0x134) +#define SGPIO_REG_SS14 MMIO32(SGPIO_PORT_BASE + 0x138) +#define SGPIO_REG_SS15 MMIO32(SGPIO_PORT_BASE + 0x13C) + +/* Reload registers (PRESET0 to 15) */ +#define SGPIO_PRESET(slice) MMIO32(SGPIO_PORT_BASE + 0x140 + \ + (slice * 0x04)) +#define SGPIO_PRESET0 MMIO32(SGPIO_PORT_BASE + 0x140) +#define SGPIO_PRESET1 MMIO32(SGPIO_PORT_BASE + 0x144) +#define SGPIO_PRESET2 MMIO32(SGPIO_PORT_BASE + 0x148) +#define SGPIO_PRESET3 MMIO32(SGPIO_PORT_BASE + 0x14C) +#define SGPIO_PRESET4 MMIO32(SGPIO_PORT_BASE + 0x150) +#define SGPIO_PRESET5 MMIO32(SGPIO_PORT_BASE + 0x154) +#define SGPIO_PRESET6 MMIO32(SGPIO_PORT_BASE + 0x158) +#define SGPIO_PRESET7 MMIO32(SGPIO_PORT_BASE + 0x15C) +#define SGPIO_PRESET8 MMIO32(SGPIO_PORT_BASE + 0x160) +#define SGPIO_PRESET9 MMIO32(SGPIO_PORT_BASE + 0x164) +#define SGPIO_PRESET10 MMIO32(SGPIO_PORT_BASE + 0x168) +#define SGPIO_PRESET11 MMIO32(SGPIO_PORT_BASE + 0x16C) +#define SGPIO_PRESET12 MMIO32(SGPIO_PORT_BASE + 0x170) +#define SGPIO_PRESET13 MMIO32(SGPIO_PORT_BASE + 0x174) +#define SGPIO_PRESET14 MMIO32(SGPIO_PORT_BASE + 0x178) +#define SGPIO_PRESET15 MMIO32(SGPIO_PORT_BASE + 0x17C) + +/* Down counter registers (COUNT0 to 15) */ +#define SGPIO_COUNT(slice) MMIO32(SGPIO_PORT_BASE + 0x180 + \ + (slice * 0x04)) +#define SGPIO_COUNT0 MMIO32(SGPIO_PORT_BASE + 0x180) +#define SGPIO_COUNT1 MMIO32(SGPIO_PORT_BASE + 0x184) +#define SGPIO_COUNT2 MMIO32(SGPIO_PORT_BASE + 0x188) +#define SGPIO_COUNT3 MMIO32(SGPIO_PORT_BASE + 0x18C) +#define SGPIO_COUNT4 MMIO32(SGPIO_PORT_BASE + 0x190) +#define SGPIO_COUNT5 MMIO32(SGPIO_PORT_BASE + 0x194) +#define SGPIO_COUNT6 MMIO32(SGPIO_PORT_BASE + 0x198) +#define SGPIO_COUNT7 MMIO32(SGPIO_PORT_BASE + 0x19C) +#define SGPIO_COUNT8 MMIO32(SGPIO_PORT_BASE + 0x1A0) +#define SGPIO_COUNT9 MMIO32(SGPIO_PORT_BASE + 0x1A4) +#define SGPIO_COUNT10 MMIO32(SGPIO_PORT_BASE + 0x1A8) +#define SGPIO_COUNT11 MMIO32(SGPIO_PORT_BASE + 0x1AC) +#define SGPIO_COUNT12 MMIO32(SGPIO_PORT_BASE + 0x1B0) +#define SGPIO_COUNT13 MMIO32(SGPIO_PORT_BASE + 0x1B4) +#define SGPIO_COUNT14 MMIO32(SGPIO_PORT_BASE + 0x1B8) +#define SGPIO_COUNT15 MMIO32(SGPIO_PORT_BASE + 0x1BC) + +/* Position registers (POS0 to 15) */ +#define SGPIO_POS(slice) MMIO32(SGPIO_PORT_BASE + 0x1C0 + \ + (slice * 0x04)) +#define SGPIO_POS0 MMIO32(SGPIO_PORT_BASE + 0x1C0) +#define SGPIO_POS1 MMIO32(SGPIO_PORT_BASE + 0x1C4) +#define SGPIO_POS2 MMIO32(SGPIO_PORT_BASE + 0x1C8) +#define SGPIO_POS3 MMIO32(SGPIO_PORT_BASE + 0x1CC) +#define SGPIO_POS4 MMIO32(SGPIO_PORT_BASE + 0x1D0) +#define SGPIO_POS5 MMIO32(SGPIO_PORT_BASE + 0x1D4) +#define SGPIO_POS6 MMIO32(SGPIO_PORT_BASE + 0x1D8) +#define SGPIO_POS7 MMIO32(SGPIO_PORT_BASE + 0x1DC) +#define SGPIO_POS8 MMIO32(SGPIO_PORT_BASE + 0x1E0) +#define SGPIO_POS9 MMIO32(SGPIO_PORT_BASE + 0x1E4) +#define SGPIO_POS10 MMIO32(SGPIO_PORT_BASE + 0x1E8) +#define SGPIO_POS11 MMIO32(SGPIO_PORT_BASE + 0x1EC) +#define SGPIO_POS12 MMIO32(SGPIO_PORT_BASE + 0x1F0) +#define SGPIO_POS13 MMIO32(SGPIO_PORT_BASE + 0x1F4) +#define SGPIO_POS14 MMIO32(SGPIO_PORT_BASE + 0x1F8) +#define SGPIO_POS15 MMIO32(SGPIO_PORT_BASE + 0x1FC) + +/* Slice name to slice index mapping */ +#define SGPIO_SLICE_A 0 +#define SGPIO_SLICE_B 1 +#define SGPIO_SLICE_C 2 +#define SGPIO_SLICE_D 3 +#define SGPIO_SLICE_E 4 +#define SGPIO_SLICE_F 5 +#define SGPIO_SLICE_G 6 +#define SGPIO_SLICE_H 7 +#define SGPIO_SLICE_I 8 +#define SGPIO_SLICE_J 9 +#define SGPIO_SLICE_K 10 +#define SGPIO_SLICE_L 11 +#define SGPIO_SLICE_M 12 +#define SGPIO_SLICE_N 13 +#define SGPIO_SLICE_O 14 +#define SGPIO_SLICE_P 15 + +/* Mask for pattern match function of slice A */ +#define SGPIO_MASK_A MMIO32(SGPIO_PORT_BASE + 0x200) + +/* Mask for pattern match function of slice H */ +#define SGPIO_MASK_H MMIO32(SGPIO_PORT_BASE + 0x204) + +/* Mask for pattern match function of slice I */ +#define SGPIO_MASK_I MMIO32(SGPIO_PORT_BASE + 0x208) + +/* Mask for pattern match function of slice P */ +#define SGPIO_MASK_P MMIO32(SGPIO_PORT_BASE + 0x20C) + +/* GPIO input status register */ +#define SGPIO_GPIO_INREG MMIO32(SGPIO_PORT_BASE + 0x210) + +/* GPIO output control register */ +#define SGPIO_GPIO_OUTREG MMIO32(SGPIO_PORT_BASE + 0x214) + +/* GPIO OE control register */ +#define SGPIO_GPIO_OENREG MMIO32(SGPIO_PORT_BASE + 0x218) + +/* Enables the slice COUNT counter */ +#define SGPIO_CTRL_ENABLE MMIO32(SGPIO_PORT_BASE + 0x21C) + +/* Disables the slice COUNT counter */ +#define SGPIO_CTRL_DISABLE MMIO32(SGPIO_PORT_BASE + 0x220) + +/* Shift clock interrupt clear mask */ +#define SGPIO_CLR_EN_0 MMIO32(SGPIO_PORT_BASE + 0xF00) + +/* Shift clock interrupt set mask */ +#define SGPIO_SET_EN_0 MMIO32(SGPIO_PORT_BASE + 0xF04) + +/* Shift clock interrupt enable */ +#define SGPIO_ENABLE_0 MMIO32(SGPIO_PORT_BASE + 0xF08) + +/* Shift clock interrupt status */ +#define SGPIO_STATUS_0 MMIO32(SGPIO_PORT_BASE + 0xF0C) + +/* Shift clock interrupt clear status */ +#define SGPIO_CLR_STATUS_0 MMIO32(SGPIO_PORT_BASE + 0xF10) + +/* Shift clock interrupt set status */ +#define SGPIO_SET_STATUS_0 MMIO32(SGPIO_PORT_BASE + 0xF14) + +/* Exchange clock interrupt clear mask */ +#define SGPIO_CLR_EN_1 MMIO32(SGPIO_PORT_BASE + 0xF20) + +/* Exchange clock interrupt set mask */ +#define SGPIO_SET_EN_1 MMIO32(SGPIO_PORT_BASE + 0xF24) + +/* Exchange clock interrupt enable */ +#define SGPIO_ENABLE_1 MMIO32(SGPIO_PORT_BASE + 0xF28) + +/* Exchange clock interrupt status */ +#define SGPIO_STATUS_1 MMIO32(SGPIO_PORT_BASE + 0xF2C) + +/* Exchange clock interrupt clear status */ +#define SGPIO_CLR_STATUS_1 MMIO32(SGPIO_PORT_BASE + 0xF30) + +/* Exchange clock interrupt set status */ +#define SGPIO_SET_STATUS_1 MMIO32(SGPIO_PORT_BASE + 0xF34) + +/* Pattern match interrupt clear mask */ +#define SGPIO_CLR_EN_2 MMIO32(SGPIO_PORT_BASE + 0xF40) + +/* Pattern match interrupt set mask */ +#define SGPIO_SET_EN_2 MMIO32(SGPIO_PORT_BASE + 0xF44) + +/* Pattern match interrupt enable */ +#define SGPIO_ENABLE_2 MMIO32(SGPIO_PORT_BASE + 0xF48) + +/* Pattern match interrupt status */ +#define SGPIO_STATUS_2 MMIO32(SGPIO_PORT_BASE + 0xF4C) + +/* Pattern match interrupt clear status */ +#define SGPIO_CLR_STATUS_2 MMIO32(SGPIO_PORT_BASE + 0xF50) + +/* Pattern match interrupt set status */ +#define SGPIO_SET_STATUS_2 MMIO32(SGPIO_PORT_BASE + 0xF54) + +/* Input interrupt clear mask */ +#define SGPIO_CLR_EN_3 MMIO32(SGPIO_PORT_BASE + 0xF60) + +/* Input bit match interrupt set mask */ +#define SGPIO_SET_EN_3 MMIO32(SGPIO_PORT_BASE + 0xF64) + +/* Input bit match interrupt enable */ +#define SGPIO_ENABLE_3 MMIO32(SGPIO_PORT_BASE + 0xF68) + +/* Input bit match interrupt status */ +#define SGPIO_STATUS_3 MMIO32(SGPIO_PORT_BASE + 0xF6C) + +/* Input bit match interrupt clear status */ +#define SGPIO_CLR_STATUS_3 MMIO32(SGPIO_PORT_BASE + 0xF70) + +/* Input bit match interrupt set status */ +#define SGPIO_SET_STATUS_3 MMIO32(SGPIO_PORT_BASE + 0xF74) + +/* --- Common register fields ----------------------------------- */ +/* TODO: Generate this stuff with the gen.py script as well! */ + +#define SGPIO_OUT_MUX_CFG_P_OUT_CFG_SHIFT (0) +#define SGPIO_OUT_MUX_CFG_P_OUT_CFG_MASK \ + (0xf << SGPIO_OUT_MUX_CFG_P_OUT_CFG_SHIFT) +#define SGPIO_OUT_MUX_CFG_P_OUT_CFG(x) \ + ((x) << SGPIO_OUT_MUX_CFG_P_OUT_CFG_SHIFT) + +#define SGPIO_OUT_MUX_CFG_P_OE_CFG_SHIFT (4) +#define SGPIO_OUT_MUX_CFG_P_OE_CFG_MASK \ + (0x7 << SGPIO_OUT_MUX_CFG_P_OE_CFG_SHIFT) +#define SGPIO_OUT_MUX_CFG_P_OE_CFG(x) \ + ((x) << SGPIO_OUT_MUX_CFG_P_OE_CFG_SHIFT) + +#define SGPIO_MUX_CFG_EXT_CLK_ENABLE_SHIFT (0) +#define SGPIO_MUX_CFG_EXT_CLK_ENABLE_MASK \ + (1 << SGPIO_MUX_CFG_EXT_CLK_ENABLE_SHIFT) +#define SGPIO_MUX_CFG_EXT_CLK_ENABLE(x) \ + ((x) << SGPIO_MUX_CFG_EXT_CLK_ENABLE_SHIFT) + +#define SGPIO_MUX_CFG_CLK_SOURCE_PIN_MODE_SHIFT (1) +#define SGPIO_MUX_CFG_CLK_SOURCE_PIN_MODE_MASK \ + (0x3 << SGPIO_MUX_CFG_CLK_SOURCE_PIN_MODE_SHIFT) +#define SGPIO_MUX_CFG_CLK_SOURCE_PIN_MODE(x) \ + ((x) << SGPIO_MUX_CFG_CLK_SOURCE_PIN_MODE_SHIFT) + +#define SGPIO_MUX_CFG_CLK_SOURCE_SLICE_MODE_SHIFT (3) +#define SGPIO_MUX_CFG_CLK_SOURCE_SLICE_MODE_MASK \ + (0x3 << SGPIO_MUX_CFG_CLK_SOURCE_SLICE_MODE_SHIFT) +#define SGPIO_MUX_CFG_CLK_SOURCE_SLICE_MODE(x) \ + ((x) << SGPIO_MUX_CFG_CLK_SOURCE_SLICE_MODE_SHIFT) + +#define SGPIO_MUX_CFG_QUALIFIER_MODE_SHIFT (5) +#define SGPIO_MUX_CFG_QUALIFIER_MODE_MASK \ + (0x3 << SGPIO_MUX_CFG_QUALIFIER_MODE_SHIFT) +#define SGPIO_MUX_CFG_QUALIFIER_MODE(x) \ + ((x) << SGPIO_MUX_CFG_QUALIFIER_MODE_SHIFT) + +#define SGPIO_MUX_CFG_QUALIFIER_PIN_MODE_SHIFT (7) +#define SGPIO_MUX_CFG_QUALIFIER_PIN_MODE_MASK \ + (0x3 << SGPIO_MUX_CFG_QUALIFIER_PIN_MODE_SHIFT) +#define SGPIO_MUX_CFG_QUALIFIER_PIN_MODE(x) \ + ((x) << SGPIO_MUX_CFG_QUALIFIER_PIN_MODE_SHIFT) + +#define SGPIO_MUX_CFG_QUALIFIER_SLICE_MODE_SHIFT (9) +#define SGPIO_MUX_CFG_QUALIFIER_SLICE_MODE_MASK \ + (0x3 << SGPIO_MUX_CFG_QUALIFIER_SLICE_MODE_SHIFT) +#define SGPIO_MUX_CFG_QUALIFIER_SLICE_MODE(x) \ + ((x) << SGPIO_MUX_CFG_QUALIFIER_SLICE_MODE_SHIFT) + +#define SGPIO_MUX_CFG_CONCAT_ENABLE_SHIFT (11) +#define SGPIO_MUX_CFG_CONCAT_ENABLE_MASK \ + (1 << SGPIO_MUX_CFG_CONCAT_ENABLE_SHIFT) +#define SGPIO_MUX_CFG_CONCAT_ENABLE(x) \ + ((x) << SGPIO_MUX_CFG_CONCAT_ENABLE_SHIFT) + +#define SGPIO_MUX_CFG_CONCAT_ORDER_SHIFT (12) +#define SGPIO_MUX_CFG_CONCAT_ORDER_MASK \ + (0x3 << SGPIO_MUX_CFG_CONCAT_ORDER_SHIFT) +#define SGPIO_MUX_CFG_CONCAT_ORDER(x) \ + ((x) << SGPIO_MUX_CFG_CONCAT_ORDER_SHIFT) + +#define SGPIO_SLICE_MUX_CFG_MATCH_MODE_SHIFT (0) +#define SGPIO_SLICE_MUX_CFG_MATCH_MODE_MASK \ + (1 << SGPIO_SLICE_MUX_CFG_MATCH_MODE_SHIFT) +#define SGPIO_SLICE_MUX_CFG_MATCH_MODE(x) \ + ((x) << SGPIO_SLICE_MUX_CFG_MATCH_MODE_SHIFT) + +#define SGPIO_SLICE_MUX_CFG_CLK_CAPTURE_MODE_SHIFT (1) +#define SGPIO_SLICE_MUX_CFG_CLK_CAPTURE_MODE_MASK \ + (1 << SGPIO_SLICE_MUX_CFG_CLK_CAPTURE_MODE_SHIFT) +#define SGPIO_SLICE_MUX_CFG_CLK_CAPTURE_MODE(x) \ + ((x) << SGPIO_SLICE_MUX_CFG_CLK_CAPTURE_MODE_SHIFT) + +#define SGPIO_SLICE_MUX_CFG_CLKGEN_MODE_SHIFT (2) +#define SGPIO_SLICE_MUX_CFG_CLKGEN_MODE_MASK \ + (1 << SGPIO_SLICE_MUX_CFG_CLKGEN_MODE_SHIFT) +#define SGPIO_SLICE_MUX_CFG_CLKGEN_MODE(x) \ + ((x) << SGPIO_SLICE_MUX_CFG_CLKGEN_MODE_SHIFT) + +#define SGPIO_SLICE_MUX_CFG_INV_OUT_CLK_SHIFT (3) +#define SGPIO_SLICE_MUX_CFG_INV_OUT_CLK_MASK \ + (1 << SGPIO_SLICE_MUX_CFG_INV_OUT_CLK_SHIFT) +#define SGPIO_SLICE_MUX_CFG_INV_OUT_CLK(x) \ + ((x) << SGPIO_SLICE_MUX_CFG_INV_OUT_CLK_SHIFT) + +#define SGPIO_SLICE_MUX_CFG_DATA_CAPTURE_MODE_SHIFT (4) +#define SGPIO_SLICE_MUX_CFG_DATA_CAPTURE_MODE_MASK \ + (0x3 << SGPIO_SLICE_MUX_CFG_DATA_CAPTURE_MODE_SHIFT) +#define SGPIO_SLICE_MUX_CFG_DATA_CAPTURE_MODE(x) \ + ((x) << SGPIO_SLICE_MUX_CFG_DATA_CAPTURE_MODE_SHIFT) + +#define SGPIO_SLICE_MUX_CFG_PARALLEL_MODE_SHIFT (6) +#define SGPIO_SLICE_MUX_CFG_PARALLEL_MODE_MASK \ + (0x3 << SGPIO_SLICE_MUX_CFG_PARALLEL_MODE_SHIFT) +#define SGPIO_SLICE_MUX_CFG_PARALLEL_MODE(x) \ + ((x) << SGPIO_SLICE_MUX_CFG_PARALLEL_MODE_SHIFT) + +#define SGPIO_SLICE_MUX_CFG_INV_QUALIFIER_SHIFT (8) +#define SGPIO_SLICE_MUX_CFG_INV_QUALIFIER_MASK \ + (1 << SGPIO_SLICE_MUX_CFG_INV_QUALIFIER_SHIFT) +#define SGPIO_SLICE_MUX_CFG_INV_QUALIFIER(x) \ + ((x) << SGPIO_SLICE_MUX_CFG_INV_QUALIFIER_SHIFT) + +#define SGPIO_POS_POS_SHIFT (0) +#define SGPIO_POS_POS_MASK (0xff << SGPIO_POS_POS_SHIFT) +#define SGPIO_POS_POS(x) ((x) << SGPIO_POS_POS_SHIFT) + +#define SGPIO_POS_POS_RESET_SHIFT (8) +#define SGPIO_POS_POS_RESET_MASK (0xff << SGPIO_POS_POS_RESET_SHIFT) +#define SGPIO_POS_POS_RESET(x) ((x) << SGPIO_POS_POS_RESET_SHIFT) + +/* --- AUTO-GENERATED STUFF FOLLOWS ----------------------------- */ + +/* --- SGPIO_OUT_MUX_CFG[0..15] values ------------------------------------ */ + +/* P_OUT_CFG: Output control of output SGPIOn */ +#define SGPIO_OUT_MUX_CFGx_P_OUT_CFG_SHIFT (0) +#define SGPIO_OUT_MUX_CFGx_P_OUT_CFG_MASK \ + (0xf << SGPIO_OUT_MUX_CFGx_P_OUT_CFG_SHIFT) +#define SGPIO_OUT_MUX_CFGx_P_OUT_CFG(x) \ + ((x) << SGPIO_OUT_MUX_CFGx_P_OUT_CFG_SHIFT) + +/* P_OE_CFG: Output enable source */ +#define SGPIO_OUT_MUX_CFGx_P_OE_CFG_SHIFT (4) +#define SGPIO_OUT_MUX_CFGx_P_OE_CFG_MASK \ + (0x7 << SGPIO_OUT_MUX_CFGx_P_OE_CFG_SHIFT) +#define SGPIO_OUT_MUX_CFGx_P_OE_CFG(x) \ + ((x) << SGPIO_OUT_MUX_CFGx_P_OE_CFG_SHIFT) + +/* --- SGPIO_MUX_CFG[0..15] values ---------------------------------------- */ + +/* EXT_CLK_ENABLE: Select clock signal */ +#define SGPIO_MUX_CFGx_EXT_CLK_ENABLE_SHIFT (0) +#define SGPIO_MUX_CFGx_EXT_CLK_ENABLE \ + (1 << SGPIO_MUX_CFGx_EXT_CLK_ENABLE_SHIFT) + +/* CLK_SOURCE_PIN_MODE: Select source clock pin */ +#define SGPIO_MUX_CFGx_CLK_SOURCE_PIN_MODE_SHIFT (1) +#define SGPIO_MUX_CFGx_CLK_SOURCE_PIN_MODE_MASK \ + (0x3 << SGPIO_MUX_CFGx_CLK_SOURCE_PIN_MODE_SHIFT) +#define SGPIO_MUX_CFGx_CLK_SOURCE_PIN_MODE(x) \ + ((x) << SGPIO_MUX_CFGx_CLK_SOURCE_PIN_MODE_SHIFT) + +/* CLK_SOURCE_SLICE_MODE: Select clock source slice */ +#define SGPIO_MUX_CFGx_CLK_SOURCE_SLICE_MODE_SHIFT (3) +#define SGPIO_MUX_CFGx_CLK_SOURCE_SLICE_MODE_MASK \ + (0x3 << SGPIO_MUX_CFGx_CLK_SOURCE_SLICE_MODE_SHIFT) +#define SGPIO_MUX_CFGx_CLK_SOURCE_SLICE_MODE(x) \ + ((x) << SGPIO_MUX_CFGx_CLK_SOURCE_SLICE_MODE_SHIFT) + +/* QUALIFIER_MODE: Select qualifier mode */ +#define SGPIO_MUX_CFGx_QUALIFIER_MODE_SHIFT (5) +#define SGPIO_MUX_CFGx_QUALIFIER_MODE_MASK \ + (0x3 << SGPIO_MUX_CFGx_QUALIFIER_MODE_SHIFT) +#define SGPIO_MUX_CFGx_QUALIFIER_MODE(x) \ + ((x) << SGPIO_MUX_CFGx_QUALIFIER_MODE_SHIFT) + +/* QUALIFIER_PIN_MODE: Select qualifier pin */ +#define SGPIO_MUX_CFGx_QUALIFIER_PIN_MODE_SHIFT (7) +#define SGPIO_MUX_CFGx_QUALIFIER_PIN_MODE_MASK \ + (0x3 << SGPIO_MUX_CFGx_QUALIFIER_PIN_MODE_SHIFT) +#define SGPIO_MUX_CFGx_QUALIFIER_PIN_MODE(x) \ + ((x) << SGPIO_MUX_CFGx_QUALIFIER_PIN_MODE_SHIFT) + +/* QUALIFIER_SLICE_MODE: Select qualifier slice */ +#define SGPIO_MUX_CFGx_QUALIFIER_SLICE_MODE_SHIFT (9) +#define SGPIO_MUX_CFGx_QUALIFIER_SLICE_MODE_MASK \ + (0x3 << SGPIO_MUX_CFGx_QUALIFIER_SLICE_MODE_SHIFT) +#define SGPIO_MUX_CFGx_QUALIFIER_SLICE_MODE(x) \ + ((x) << SGPIO_MUX_CFG0_QUALIFIER_SLICE_MODE_SHIFT) + +/* CONCAT_ENABLE: Enable concatenation */ +#define SGPIO_MUX_CFGx_CONCAT_ENABLE_SHIFT (11) +#define SGPIO_MUX_CFGx_CONCAT_ENABLE \ + (1 << SGPIO_MUX_CFGx_CONCAT_ENABLE_SHIFT) + +/* CONCAT_ORDER: Select concatenation order */ +#define SGPIO_MUX_CFGx_CONCAT_ORDER_SHIFT (12) +#define SGPIO_MUX_CFGx_CONCAT_ORDER_MASK \ + (0x3 << SGPIO_MUX_CFGx_CONCAT_ORDER_SHIFT) +#define SGPIO_MUX_CFGx_CONCAT_ORDER(x) \ + ((x) << SGPIO_MUX_CFGx_CONCAT_ORDER_SHIFT) + +/* --- SGPIO_SLICE_MUX_CFG[0..15] values ---------------------------------- */ + +/* MATCH_MODE: Match mode */ +#define SGPIO_SLICE_MUX_CFGx_MATCH_MODE_SHIFT (0) +#define SGPIO_SLICE_MUX_CFGx_MATCH_MODE \ + (1 << SGPIO_SLICE_MUX_CFG0_MATCH_MODE_SHIFT) + +/* CLK_CAPTURE_MODE: Capture clock mode */ +#define SGPIO_SLICE_MUX_CFGx_CLK_CAPTURE_MODE_SHIFT (1) +#define SGPIO_SLICE_MUX_CFGx_CLK_CAPTURE_MODE \ + (1 << SGPIO_SLICE_MUX_CFGx_CLK_CAPTURE_MODE_SHIFT) + +/* CLKGEN_MODE: Clock generation mode */ +#define SGPIO_SLICE_MUX_CFGx_CLKGEN_MODE_SHIFT (2) +#define SGPIO_SLICE_MUX_CFGx_CLKGEN_MODE \ + (1 << SGPIO_SLICE_MUX_CFGx_CLKGEN_MODE_SHIFT) + +/* INV_OUT_CLK: Invert output clock */ +#define SGPIO_SLICE_MUX_CFGx_INV_OUT_CLK_SHIFT (3) +#define SGPIO_SLICE_MUX_CFGx_INV_OUT_CLK \ + (1 << SGPIO_SLICE_MUX_CFGx_INV_OUT_CLK_SHIFT) + +/* DATA_CAPTURE_MODE: Condition for input bit match interrupt */ +#define SGPIO_SLICE_MUX_CFGx_DATA_CAPTURE_MODE_SHIFT (4) +#define SGPIO_SLICE_MUX_CFGx_DATA_CAPTURE_MODE_MASK \ + (0x3 << SGPIO_SLICE_MUX_CFGx_DATA_CAPTURE_MODE_SHIFT) +#define SGPIO_SLICE_MUX_CFGx_DATA_CAPTURE_MODE(x) \ + ((x) << SGPIO_SLICE_MUX_CFGx_DATA_CAPTURE_MODE_SHIFT) + +/* PARALLEL_MODE: Parallel mode */ +#define SGPIO_SLICE_MUX_CFGx_PARALLEL_MODE_SHIFT (6) +#define SGPIO_SLICE_MUX_CFGx_PARALLEL_MODE_MASK \ + (0x3 << SGPIO_SLICE_MUX_CFGx_PARALLEL_MODE_SHIFT) +#define SGPIO_SLICE_MUX_CFGx_PARALLEL_MODE(x) \ + ((x) << SGPIO_SLICE_MUX_CFGx_PARALLEL_MODE_SHIFT) + +/* INV_QUALIFIER: Inversion qualifier */ +#define SGPIO_SLICE_MUX_CFGx_INV_QUALIFIER_SHIFT (8) +#define SGPIO_SLICE_MUX_CFGx_INV_QUALIFIER \ + (1 << SGPIO_SLICE_MUX_CFGx_INV_QUALIFIER_SHIFT) + + +/* --- SGPIO_POS[0..15] values -------------------------------------------- */ + +/* POS: Each time COUNT reaches 0x0 POS counts down */ +#define SGPIO_POSx_POS_SHIFT (0) +#define SGPIO_POSx_POS_MASK (0xff << SGPIO_POSx_POS_SHIFT) +#define SGPIO_POSx_POS(x) ((x) << SGPIO_POSx_POS_SHIFT) + +/* POS_RESET: Reload value for POS after POS reaches 0x0 */ +#define SGPIO_POSx_POS_RESET_SHIFT (8) +#define SGPIO_POSx_POS_RESET_MASK (0xff << SGPIO_POSx_POS_RESET_SHIFT) +#define SGPIO_POSx_POS_RESET(x) ((x) << SGPIO_POSx_POS_RESET_SHIFT) + + +/* SGPIO structure for faster/better code generation (especially when optimized + * with -O2/-O3) + */ +/* This structure is compliant with LPC43xx User Manual UM10503 Rev.1.4 - 3 + * September 2012 + */ +typedef struct { + /* Pin multiplexer configuration registers. RW */ + volatile uint32_t OUT_MUX_CFG[16]; + /* SGPIO multiplexer configuration registers. RW */ + volatile uint32_t SGPIO_MUX_CFG[16]; + /* Slice multiplexer configuration registers. RW */ + volatile uint32_t SLICE_MUX_CFG[16]; + /* Slice data registers. RW */ + volatile uint32_t REG[16]; + /* Slice data shadow registers. Each time POS reaches 0x0 the contents + * of REG_SS is exchanged with the content of REG. RW + */ + volatile uint32_t REG_SS[16]; + /* Reload registers. Counter reload value; loaded when COUNT reaches + * 0x0 RW + */ + volatile uint32_t PRESET[16]; + /* Down counter registers, counts down each shift clock cycle. RW */ + volatile uint32_t COUNT[16]; + /* Position registers. POS Each time COUNT reaches 0x0 POS counts down. + * POS_RESET Reload value for POS after POS reaches 0x0. RW + */ + volatile uint32_t POS[16]; + /* Slice A mask register. Mask for pattern match function of slice A. + * RW + */ + volatile uint32_t MASK_A; + /* Slice H mask register. Mask for pattern match function of slice H. + * RW + */ + volatile uint32_t MASK_H; + /* Slice I mask register. Mask for pattern match function of slice I. + * RW + */ + volatile uint32_t MASK_I; + /* Slice P mask register. Mask for pattern match function of slice P. + * RW + */ + volatile uint32_t MASK_P; + /* GPIO input status register. R */ + volatile uint32_t GPIO_INREG; + /* GPIO output control register. RW */ + volatile uint32_t GPIO_OUTREG; + /* GPIO output enable register. RW */ + volatile uint32_t GPIO_OENREG; + /* Slice count enable register. RW */ + volatile uint32_t CTRL_ENABLE; + /* Slice count disable register. RW */ + volatile uint32_t CTRL_DISABLE; + volatile uint32_t RES0[823]; + /* Shift clock interrupt clear mask register. W */ + volatile uint32_t CLR_EN_0; + /* Shift clock interrupt set mask register. W */ + volatile uint32_t SET_EN_0; + /* Shift clock interrupt enable register. R */ + volatile uint32_t ENABLE_0; + /* Shift clock interrupt status register. R */ + volatile uint32_t STATUS_0; + /* Shift clock interrupt clear status register. W */ + volatile uint32_t CLR_STATUS_0; + /* Shift clock interrupt set status register. W */ + volatile uint32_t SET_STATUS_0; + volatile uint32_t RES1[2]; + /* Exchange clock interrupt clear mask register. W */ + volatile uint32_t CLR_EN_1; + /* Exchange clock interrupt set mask register. W */ + volatile uint32_t SET_EN_1; + /* Exchange clock interrupt enable. R */ + volatile uint32_t ENABLE_1; + /* Exchange clock interrupt status register. R */ + volatile uint32_t STATUS_1; + /* Exchange clock interrupt clear status register. W */ + volatile uint32_t CLR_STATUS_1; + /* Exchange clock interrupt set status register. W */ + volatile uint32_t SET_STATUS_1; + volatile uint32_t RES2[2]; + /* Pattern match interrupt clear mask register. W */ + volatile uint32_t CLR_EN_2; + /* Pattern match interrupt set mask register. W */ + volatile uint32_t SET_EN_2; + /* Pattern match interrupt enable register. R */ + volatile uint32_t ENABLE_2; + /* Pattern match interrupt status register. R */ + volatile uint32_t STATUS_2; + /* Pattern match interrupt clear status register. W */ + volatile uint32_t CLR_STATUS_2; + /* Pattern match interrupt set status register. W */ + volatile uint32_t SET_STATUS_2; + volatile uint32_t RES3[2]; + /* Input interrupt clear mask register. W */ + volatile uint32_t CLR_EN_3; + /* Input bit match interrupt set mask register. W */ + volatile uint32_t SET_EN_3; + /* Input bit match interrupt enable register. R */ + volatile uint32_t ENABLE_3; + /* Input bit match interrupt status register. R */ + volatile uint32_t STATUS_3; + /* Input bit match interrupt clear status register. W */ + volatile uint32_t CLR_STATUS_3; + /* Input bit match interrupt set status register. W */ + volatile uint32_t SET_STATUS_3; +} sgpio_t; + +/* Global access to SGPIO structure */ +#define SGPIO ((sgpio_t *)SGPIO_PORT_BASE) + +/**@}*/ + +#endif diff --git a/libopencm3/include/libopencm3/lpc43xx/ssp.h b/libopencm3/include/libopencm3/lpc43xx/ssp.h new file mode 100644 index 0000000..a336652 --- /dev/null +++ b/libopencm3/include/libopencm3/lpc43xx/ssp.h @@ -0,0 +1,209 @@ +/** @defgroup ssp_defines Synchronous Serial Port + +@brief <b>Defined Constants and Types for the LPC43xx Synchronous Serial +Port</b> + +@ingroup LPC43xx_defines + +@version 1.0.0 + +@author @htmlonly © @endhtmlonly 2012 Michael Ossmann <mike@ossmann.com> + +@date 10 March 2013 + +LGPL License Terms @ref lgpl_license + */ +/* +* This file is part of the libopencm3 project. +* +* Copyright (C) 2012 Michael Ossmann <mike@ossmann.com> +* +* This library is free software: you can redistribute it and/or modify +* it under the terms of the GNU Lesser General Public License as published by +* the Free Software Foundation, either version 3 of the License, or +* (at your option) any later version. +* +* This library is distributed in the hope that it will be useful, +* but WITHOUT ANY WARRANTY; without even the implied warranty of +* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +* GNU Lesser General Public License for more details. +* +* You should have received a copy of the GNU Lesser General Public License +* along with this library. If not, see <http://www.gnu.org/licenses/>. +*/ + +#ifndef LPC43XX_SSP_H +#define LPC43XX_SSP_H + +/**@{*/ + +#include <libopencm3/cm3/common.h> +#include <libopencm3/lpc43xx/memorymap.h> + +/* --- Convenience macros -------------------------------------------------- */ + +/* SSP port base addresses (for convenience) */ +#define SSP0 SSP0_BASE +#define SSP1 SSP1_BASE + + +/* --- SSP registers ------------------------------------------------------- */ + +/* Control Register 0 */ +#define SSP_CR0(port) MMIO32(port + 0x000) +#define SSP0_CR0 SSP_CR0(SSP0) +#define SSP1_CR0 SSP_CR0(SSP1) + +/* Control Register 1 */ +#define SSP_CR1(port) MMIO32(port + 0x004) +#define SSP0_CR1 SSP_CR1(SSP0) +#define SSP1_CR1 SSP_CR1(SSP1) + +/* Data Register */ +#define SSP_DR(port) MMIO32(port + 0x008) +#define SSP0_DR SSP_DR(SSP0) +#define SSP1_DR SSP_DR(SSP1) + +/* Status Register */ +#define SSP_SR(port) MMIO32(port + 0x00C) +#define SSP0_SR SSP_SR(SSP0) +#define SSP1_SR SSP_SR(SSP1) + +#define SSP_SR_TFE BIT0 +#define SSP_SR_TNF BIT1 +#define SSP_SR_RNE BIT2 +#define SSP_SR_RFF BIT3 +#define SSP_SR_BSY BIT4 + +/* Clock Prescale Register */ +#define SSP_CPSR(port) MMIO32(port + 0x010) +#define SSP0_CPSR SSP_CPSR(SSP0) +#define SSP1_CPSR SSP_CPSR(SSP1) + +/* Interrupt Mask Set and Clear Register */ +#define SSP_IMSC(port) MMIO32(port + 0x014) +#define SSP0_IMSC SSP_IMSC(SSP0) +#define SSP1_IMSC SSP_IMSC(SSP1) + +/* Raw Interrupt Status Register */ +#define SSP_RIS(port) MMIO32(port + 0x018) +#define SSP0_RIS SSP_RIS(SSP0) +#define SSP1_RIS SSP_RIS(SSP1) + +/* Masked Interrupt Status Register */ +#define SSP_MIS(port) MMIO32(port + 0x01C) +#define SSP0_MIS SSP_MIS(SSP0) +#define SSP1_MIS SSP_MIS(SSP1) + +/* SSPICR Interrupt Clear Register */ +#define SSP_ICR(port) MMIO32(port + 0x020) +#define SSP0_ICR SSP_ICR(SSP0) +#define SSP1_ICR SSP_ICR(SSP1) + +/* SSP1 DMA control register */ +#define SSP_DMACR(port) MMIO32(port + 0x024) +#define SSP0_DMACR SSP_DMACR(SSP0) +#define SSP1_DMACR SSP_DMACR(SSP1) + +/* RXDMAE: Receive DMA enable */ +#define SSP_DMACR_RXDMAE 0x1 + +/* RXDMAE: Transmit DMA enable */ +#define SSP_DMACR_TXDMAE 0x2 + +typedef enum { + SSP0_NUM = 0x0, + SSP1_NUM = 0x1 +} ssp_num_t; + +/* + * SSP Control Register 0 + */ +/* SSP Data Size Bits 0 to 3 */ +typedef enum { + SSP_DATA_4BITS = 0x3, + SSP_DATA_5BITS = 0x4, + SSP_DATA_6BITS = 0x5, + SSP_DATA_7BITS = 0x6, + SSP_DATA_8BITS = 0x7, + SSP_DATA_9BITS = 0x8, + SSP_DATA_10BITS = 0x9, + SSP_DATA_11BITS = 0xA, + SSP_DATA_12BITS = 0xB, + SSP_DATA_13BITS = 0xC, + SSP_DATA_14BITS = 0xD, + SSP_DATA_15BITS = 0xE, + SSP_DATA_16BITS = 0xF +} ssp_datasize_t; + +/* SSP Frame Format/Type Bits 4 & 5 */ +typedef enum { + SSP_FRAME_SPI = 0x00, + SSP_FRAME_TI = BIT4, + SSP_FRAM_MICROWIRE = BIT5 +} ssp_frame_format_t; + +/* Clock Out Polarity / Clock Out Phase Bits Bits 6 & 7 */ +typedef enum { + SSP_CPOL_0_CPHA_0 = 0x0, + SSP_CPOL_1_CPHA_0 = BIT6, + SSP_CPOL_0_CPHA_1 = BIT7, + SSP_CPOL_1_CPHA_1 = (BIT6|BIT7) +} ssp_cpol_cpha_t; + +/* + * SSP Control Register 1 + */ +/* SSP Mode Bit0 */ +typedef enum { + SSP_MODE_NORMAL = 0x0, + SSP_MODE_LOOPBACK = BIT0 +} ssp_mode_t; + +/* SSP Enable Bit1 */ +#define SSP_ENABLE BIT1 + +/* SSP Master/Slave Mode Bit2 */ +typedef enum { + SSP_MASTER = 0x0, + SSP_SLAVE = BIT2 +} ssp_master_slave_t; + +/* +* SSP Slave Output Disable Bit3 +* Slave Output Disable. This bit is relevant only in slave mode +* (MS = 1). If it is 1, this blocks this SSP controller from driving the +* transmit data line (MISO). +*/ +typedef enum { + SSP_SLAVE_OUT_ENABLE = 0x0, + SSP_SLAVE_OUT_DISABLE = BIT3 +} ssp_slave_option_t; /* This option is relevant only in slave mode */ + +BEGIN_DECLS + +void ssp_disable(ssp_num_t ssp_num); + +/* + * SSP Init + * clk_prescale shall be in range 2 to 254 (even number only). + * Clock computation: PCLK / (CPSDVSR * [SCR+1]) => CPSDVSR=clk_prescale, + * SCR=serial_clock_rate + */ +void ssp_init(ssp_num_t ssp_num, + ssp_datasize_t data_size, + ssp_frame_format_t frame_format, + ssp_cpol_cpha_t cpol_cpha_format, + uint8_t serial_clock_rate, + uint8_t clk_prescale, + ssp_mode_t mode, + ssp_master_slave_t master_slave, + ssp_slave_option_t slave_option); + +uint16_t ssp_transfer(ssp_num_t ssp_num, uint16_t data); + +END_DECLS + +/**@}*/ + +#endif diff --git a/libopencm3/include/libopencm3/lpc43xx/timer.h b/libopencm3/include/libopencm3/lpc43xx/timer.h new file mode 100644 index 0000000..2c691e7 --- /dev/null +++ b/libopencm3/include/libopencm3/lpc43xx/timer.h @@ -0,0 +1,270 @@ +/** @defgroup timer_defines Timer + +@brief <b>Defined Constants and Types for the LPC43xx timer</b> + +@ingroup LPC43xx_defines + +@version 1.0.0 + +@author @htmlonly © @endhtmlonly 2012 Michael Ossmann <mike@ossmann.com> + +@date 10 March 2013 + +LGPL License Terms @ref lgpl_license + */ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2012 Michael Ossmann <mike@ossmann.com> + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see <http://www.gnu.org/licenses/>. + */ + +#ifndef LPC43XX_TIMER_H +#define LPC43XX_TIMER_H + +/**@{*/ + +#include <libopencm3/cm3/common.h> +#include <libopencm3/lpc43xx/memorymap.h> + +/* --- Convenience macros -------------------------------------------------- */ + +/* Timer base addresses */ +#define TIMER0 TIMER0_BASE +#define TIMER1 TIMER1_BASE +#define TIMER2 TIMER2_BASE +#define TIMER3 TIMER3_BASE + + +/* --- Timer registers ----------------------------------------------------- */ + +/* Interrupt Register */ +#define TIMER_IR(timer) MMIO32(timer + 0x000) +#define TIMER0_IR TIMER_IR(TIMER0) +#define TIMER1_IR TIMER_IR(TIMER1) +#define TIMER2_IR TIMER_IR(TIMER2) +#define TIMER3_IR TIMER_IR(TIMER3) + +/* Timer Control Register */ +#define TIMER_TCR(timer) MMIO32(timer + 0x004) +#define TIMER0_TCR TIMER_TCR(TIMER0) +#define TIMER1_TCR TIMER_TCR(TIMER1) +#define TIMER2_TCR TIMER_TCR(TIMER2) +#define TIMER3_TCR TIMER_TCR(TIMER3) + +/* Timer Counter */ +#define TIMER_TC(timer) MMIO32(timer + 0x008) +#define TIMER0_TC TIMER_TC(TIMER0) +#define TIMER1_TC TIMER_TC(TIMER1) +#define TIMER2_TC TIMER_TC(TIMER2) +#define TIMER3_TC TIMER_TC(TIMER3) + +/* Prescale Register */ +#define TIMER_PR(timer) MMIO32(timer + 0x00C) +#define TIMER0_PR TIMER_PR(TIMER0) +#define TIMER1_PR TIMER_PR(TIMER1) +#define TIMER2_PR TIMER_PR(TIMER2) +#define TIMER3_PR TIMER_PR(TIMER3) + +/* Prescale Counter */ +#define TIMER_PC(timer) MMIO32(timer + 0x010) +#define TIMER0_PC TIMER_PC(TIMER0) +#define TIMER1_PC TIMER_PC(TIMER1) +#define TIMER2_PC TIMER_PC(TIMER2) +#define TIMER3_PC TIMER_PC(TIMER3) + +/* Match Control Register */ +#define TIMER_MCR(timer) MMIO32(timer + 0x014) +#define TIMER0_MCR TIMER_MCR(TIMER0) +#define TIMER1_MCR TIMER_MCR(TIMER1) +#define TIMER2_MCR TIMER_MCR(TIMER2) +#define TIMER3_MCR TIMER_MCR(TIMER3) + +/* Match Register 0 */ +#define TIMER_MR0(timer) MMIO32(timer + 0x018) +#define TIMER0_MR0 TIMER_MR0(TIMER0) +#define TIMER1_MR0 TIMER_MR0(TIMER1) +#define TIMER2_MR0 TIMER_MR0(TIMER2) +#define TIMER3_MR0 TIMER_MR0(TIMER3) + +/* Match Register 1 */ +#define TIMER_MR1(timer) MMIO32(timer + 0x01C) +#define TIMER0_MR1 TIMER_MR1(TIMER0) +#define TIMER1_MR1 TIMER_MR1(TIMER1) +#define TIMER2_MR1 TIMER_MR1(TIMER2) +#define TIMER3_MR1 TIMER_MR1(TIMER3) + +/* Match Register 2 */ +#define TIMER_MR2(timer) MMIO32(timer + 0x020) +#define TIMER0_MR2 TIMER_MR2(TIMER0) +#define TIMER1_MR2 TIMER_MR2(TIMER1) +#define TIMER2_MR2 TIMER_MR2(TIMER2) +#define TIMER3_MR2 TIMER_MR2(TIMER3) + +/* Match Register 3 */ +#define TIMER_MR3(timer) MMIO32(timer + 0x024) +#define TIMER0_MR3 TIMER_MR3(TIMER0) +#define TIMER1_MR3 TIMER_MR3(TIMER1) +#define TIMER2_MR3 TIMER_MR3(TIMER2) +#define TIMER3_MR3 TIMER_MR3(TIMER3) + +/* Capture Control Register */ +#define TIMER_CCR(timer) MMIO32(timer + 0x028) +#define TIMER0_CCR TIMER_CCR(TIMER0) +#define TIMER1_CCR TIMER_CCR(TIMER1) +#define TIMER2_CCR TIMER_CCR(TIMER2) +#define TIMER3_CCR TIMER_CCR(TIMER3) + +/* Capture Register 0 */ +#define TIMER_CR0(timer) MMIO32(timer + 0x02C) +#define TIMER0_CR0 TIMER_CR0(TIMER0) +#define TIMER1_CR0 TIMER_CR0(TIMER1) +#define TIMER2_CR0 TIMER_CR0(TIMER2) +#define TIMER3_CR0 TIMER_CR0(TIMER3) + +/* Capture Register 1 */ +#define TIMER_CR1(timer) MMIO32(timer + 0x030) +#define TIMER0_CR1 TIMER_CR1(TIMER0) +#define TIMER1_CR1 TIMER_CR1(TIMER1) +#define TIMER2_CR1 TIMER_CR1(TIMER2) +#define TIMER3_CR1 TIMER_CR1(TIMER3) + +/* Capture Register 2 */ +#define TIMER_CR2(timer) MMIO32(timer + 0x034) +#define TIMER0_CR2 TIMER_CR2(TIMER0) +#define TIMER1_CR2 TIMER_CR2(TIMER1) +#define TIMER2_CR2 TIMER_CR2(TIMER2) +#define TIMER3_CR2 TIMER_CR2(TIMER3) + +/* Capture Register 3 */ +#define TIMER_CR3(timer) MMIO32(timer + 0x038) +#define TIMER0_CR3 TIMER_CR3(TIMER0) +#define TIMER1_CR3 TIMER_CR3(TIMER1) +#define TIMER2_CR3 TIMER_CR3(TIMER2) +#define TIMER3_CR3 TIMER_CR3(TIMER3) + +/* External Match Register */ +#define TIMER_EMR(timer) MMIO32(timer + 0x03C) +#define TIMER0_EMR TIMER_EMR(TIMER0) +#define TIMER1_EMR TIMER_EMR(TIMER1) +#define TIMER2_EMR TIMER_EMR(TIMER2) +#define TIMER3_EMR TIMER_EMR(TIMER3) + +/* Count Control Register */ +#define TIMER_CTCR(timer) MMIO32(timer + 0x070) +#define TIMER0_CTCR TIMER_CTCR(TIMER0) +#define TIMER1_CTCR TIMER_CTCR(TIMER1) +#define TIMER2_CTCR TIMER_CTCR(TIMER2) +#define TIMER3_CTCR TIMER_CTCR(TIMER3) + +/* --- TIMERx_IR values ----------------------------------------------------- */ + +#define TIMER_IR_MR0INT (1 << 0) +#define TIMER_IR_MR1INT (1 << 1) +#define TIMER_IR_MR2INT (1 << 2) +#define TIMER_IR_MR3INT (1 << 3) +#define TIMER_IR_CR0INT (1 << 4) +#define TIMER_IR_CR1INT (1 << 5) +#define TIMER_IR_CR2INT (1 << 6) +#define TIMER_IR_CR3INT (1 << 7) + +/* --- TIMERx_TCR values --------------------------------------------------- */ + +#define TIMER_TCR_CEN (1 << 0) +#define TIMER_TCR_CRST (1 << 1) + +/* --- TIMERx_MCR values --------------------------------------------------- */ + +#define TIMER_MCR_MR0I (1 << 0) +#define TIMER_MCR_MR0R (1 << 1) +#define TIMER_MCR_MR0S (1 << 2) +#define TIMER_MCR_MR1I (1 << 3) +#define TIMER_MCR_MR1R (1 << 4) +#define TIMER_MCR_MR1S (1 << 5) +#define TIMER_MCR_MR2I (1 << 6) +#define TIMER_MCR_MR2R (1 << 7) +#define TIMER_MCR_MR2S (1 << 8) +#define TIMER_MCR_MR3I (1 << 9) +#define TIMER_MCR_MR3R (1 << 10) +#define TIMER_MCR_MR3S (1 << 11) + +/* --- TIMERx_MCR values --------------------------------------------------- */ + +#define TIMER_CCR_CAP0RE (1 << 0) +#define TIMER_CCR_CAP0FE (1 << 1) +#define TIMER_CCR_CAP0I (1 << 2) +#define TIMER_CCR_CAP1RE (1 << 3) +#define TIMER_CCR_CAP1FE (1 << 4) +#define TIMER_CCR_CAP1I (1 << 5) +#define TIMER_CCR_CAP2RE (1 << 6) +#define TIMER_CCR_CAP2FE (1 << 7) +#define TIMER_CCR_CAP2I (1 << 8) +#define TIMER_CCR_CAP3RE (1 << 9) +#define TIMER_CCR_CAP3FE (1 << 10) +#define TIMER_CCR_CAP3I (1 << 11) + +/* --- TIMERx_EMR values --------------------------------------------------- */ + +#define TIMER_EMR_EM0 (1 << 0) +#define TIMER_EMR_EM1 (1 << 1) +#define TIMER_EMR_EM2 (1 << 2) +#define TIMER_EMR_EM3 (1 << 3) +#define TIMER_EMR_EMC0_SHIFT 4 +#define TIMER_EMR_EMC0_MASK (0x3 << TIMER_EMR_EMC0_SHIFT) +#define TIMER_EMR_EMC1_SHIFT 6 +#define TIMER_EMR_EMC1_MASK (0x3 << TIMER_EMR_EMC1_SHIFT) +#define TIMER_EMR_EMC2_SHIFT 8 +#define TIMER_EMR_EMC2_MASK (0x3 << TIMER_EMR_EMC2_SHIFT) +#define TIMER_EMR_EMC3_SHIFT 10 +#define TIMER_EMR_EMC3_MASK (0x3 << TIMER_EMR_EMC3_SHIFT) + +#define TIMER_EMR_EMC_NOTHING 0x0 +#define TIMER_EMR_EMC_CLEAR 0x1 +#define TIMER_EMR_EMC_SET 0x2 +#define TIMER_EMR_EMC_TOGGLE 0x3 + +/* --- TIMERx_CTCR values -------------------------------------------------- */ + +#define TIMER_CTCR_MODE_TIMER (0x0 << 0) +#define TIMER_CTCR_MODE_COUNTER_RISING (0x1 << 0) +#define TIMER_CTCR_MODE_COUNTER_FALLING (0x2 << 0) +#define TIMER_CTCR_MODE_COUNTER_BOTH (0x3 << 0) +#define TIMER_CTCR_MODE_MASK (0x3 << 0) + +#define TIMER_CTCR_CINSEL_CAPN_0 (0x0 << 2) +#define TIMER_CTCR_CINSEL_CAPN_1 (0x1 << 2) +#define TIMER_CTCR_CINSEL_CAPN_2 (0x2 << 2) +#define TIMER_CTCR_CINSEL_CAPN_3 (0x3 << 2) +#define TIMER_CTCR_CINSEL_MASK (0x3 << 2) + +/* --- TIMER function prototypes ------------------------------------------- */ + +BEGIN_DECLS + +void timer_reset(uint32_t timer_peripheral); +void timer_enable_counter(uint32_t timer_peripheral); +void timer_disable_counter(uint32_t timer_peripheral); +uint32_t timer_get_counter(uint32_t timer_peripheral); +void timer_set_counter(uint32_t timer_peripheral, uint32_t count); +uint32_t timer_get_prescaler(uint32_t timer_peripheral); +void timer_set_prescaler(uint32_t timer_peripheral, uint32_t prescaler); +void timer_set_mode(uint32_t timer_peripheral, uint32_t mode); +void timer_set_count_input(uint32_t timer_peripheral, uint32_t input); + +END_DECLS + +/**@}*/ + +#endif diff --git a/libopencm3/include/libopencm3/lpc43xx/uart.h b/libopencm3/include/libopencm3/lpc43xx/uart.h new file mode 100644 index 0000000..28830e3 --- /dev/null +++ b/libopencm3/include/libopencm3/lpc43xx/uart.h @@ -0,0 +1,438 @@ +/* +* This file is part of the libopencm3 project. +* +* Copyright (C) 2012 Benjamin Vernoux <titanmkd@gmail.com> +* +* This library is free software: you can redistribute it and/or modify +* it under the terms of the GNU Lesser General Public License as published by +* the Free Software Foundation, either version 3 of the License, or +* (at your option) any later version. +* +* This library is distributed in the hope that it will be useful, +* but WITHOUT ANY WARRANTY; without even the implied warranty of +* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +* GNU Lesser General Public License for more details. +* +* You should have received a copy of the GNU Lesser General Public License +* along with this library. If not, see <http://www.gnu.org/licenses/>. +*/ + +#ifndef LPC43XX_UART_H +#define LPC43XX_UART_H + +#include <libopencm3/cm3/common.h> +#include <libopencm3/lpc43xx/memorymap.h> + +/* --- Convenience macros -------------------------------------------------- */ + +/* UART port base addresses (for convenience) */ +#define UART0 USART0_BASE /* APB0 */ +#define UART1 UART1_BASE /* APB0 */ +#define UART2 USART2_BASE /* APB2 */ +#define UART3 USART3_BASE /* APB2 */ + +/* --- UART registers ------------------------------------------------------- */ + +/* Receiver Buffer Register (DLAB=0) Read Only */ +#define UART_RBR(port) MMIO32(port + 0x000) /* 8bits */ + +/* Transmitter Holding Register (DLAB=0) Write Only */ +#define UART_THR(port) MMIO32(port + 0x000) /* 8bits */ + +/* Divisor Latch LSB Register (DLAB=1) */ +#define UART_DLL(port) MMIO32(port + 0x000) /* 8bits */ + +/* Divisor Latch MSB Register (DLAB=1) */ +#define UART_DLM(port) MMIO32(port + 0x004) /* 8bits */ + +/* Interrupt Enable Register (DLAB=0) */ +#define UART_IER(port) MMIO32(port + 0x004) + +/* Interrupt ID Register Read Only */ +#define UART_IIR(port) MMIO32(port + 0x008) + +/* FIFO Control Register Write Only */ +#define UART_FCR(port) MMIO32(port + 0x008) + +/* Line Control Register */ +#define UART_LCR(port) MMIO32(port + 0x00C) + +/* MCR only for UART1 */ + +/* Line Status Register */ +#define UART_LSR(port) MMIO32(port + 0x014) + +/* Auto Baud Control Register */ +#define UART_ACR(port) MMIO32(port + 0x020) + +/* IrDA Control Register only for UART0/2/3 */ +#define UART_ICR(port) MMIO32(port + 0x024) + +/* Fractional Divider Register */ +#define UART_FDR(port) MMIO32(port + 0x028) + +/* Oversampling Register only for UART0/2/3 */ +#define UART_OSR(port) MMIO32(port + 0x02C) + +/* Half-Duplex enable Register only for UART0/2/3 */ +#define UART_HDEN(port) MMIO32(port + 0x040) + +/* Smart card Interface Register Only for UART0/2/3 */ +#define UART_SCICTRL(port) MMIO32(port + 0x048) + +/* RS-485/EIA-485 Control Register */ +#define UART_RS485CTRL(port) MMIO32(port + 0x04C) + +/* RS-485/EIA-485 Address Match Register */ +#define UART_RS485ADRMATCH(port) MMIO32(port + 0x050) + +/* RS-485/EIA-485 Direction Control Delay Register */ +#define UART_RS485DLY(port) MMIO32(port + 0x054) + +/* Synchronous Mode Control Register only for UART0/2/3 */ +#define UART_SYNCCTRL(port) MMIO32(port + 0x058) + +/* Transmit Enable Register */ +#define UART_TER(port) MMIO32(port + 0x05C) + +/* --------------------- BIT DEFINITIONS ----------------------------------- */ +/*********************************************************************** +* Macro defines for Macro defines for UARTn Receiver Buffer Register +**********************************************************************/ +/* UART Received Buffer mask bit (8 bits) */ +#define UART_RBR_MASKBIT ((uint8_t)0xFF) + +/*********************************************************************** +* Macro defines for Macro defines for UARTn Transmit Holding Register +**********************************************************************/ +/* UART Transmit Holding mask bit (8 bits) */ +#define UART_THR_MASKBIT ((uint8_t)0xFF) + +/*********************************************************************** +* Macro defines for Macro defines for UARTn Divisor Latch LSB register +**********************************************************************/ +/* Macro for loading least significant halfs of divisors */ +#define UART_LOAD_DLL(div) ((div) & 0xFF) + +/* Divisor latch LSB bit mask */ +#define UART_DLL_MASKBIT ((uint8_t)0xFF) + +/*********************************************************************** +* Macro defines for Macro defines for UARTn Divisor Latch MSB register +**********************************************************************/ +/* Divisor latch MSB bit mask */ +#define UART_DLM_MASKBIT ((uint8_t)0xFF) + +/* Macro for loading most significant halfs of divisors */ +#define UART_LOAD_DLM(div) (((div) >> 8) & 0xFF) + +/*********************************************************************** +* Macro defines for Macro defines for UART interrupt enable register +**********************************************************************/ +/* RBR Interrupt enable*/ +#define UART_IER_RBRINT_EN (1 << 0) +/* THR Interrupt enable*/ +#define UART_IER_THREINT_EN (1 << 1) +/* RX line status interrupt enable*/ +#define UART_IER_RLSINT_EN (1 << 2) +/* Modem status interrupt enable */ +#define UART1_IER_MSINT_EN (1 << 3) +/* CTS1 signal transition interrupt enable */ +#define UART1_IER_CTSINT_EN (1 << 7) +/* Enables the end of auto-baud interrupt */ +#define UART_IER_ABEOINT_EN (1 << 8) +/* Enables the auto-baud time-out interrupt */ +#define UART_IER_ABTOINT_EN (1 << 9) +/* UART interrupt enable register bit mask */ +#define UART_IER_BITMASK ((uint32_t)(0x307)) +/* UART1 interrupt enable register bit mask */ +#define UART1_IER_BITMASK ((uint32_t)(0x38F)) + +/********************************************************************** +* Macro defines for Macro defines for UART interrupt identification register +**********************************************************************/ + +/* Interrupt Status - Active low */ +#define UART_IIR_INTSTAT_PEND (1 << 0) +/* Interrupt identification: Modem interrupt*/ +#define UART1_IIR_INTID_MODEM (0 << 1) +/* Interrupt identification: THRE interrupt*/ +#define UART_IIR_INTID_THRE (1 << 1) +/* Interrupt identification: Receive data available*/ +#define UART_IIR_INTID_RDA (2 << 1) +/* Interrupt identification: Receive line status*/ +#define UART_IIR_INTID_RLS (3 << 1) +/* Interrupt identification: Character time-out indicator*/ +#define UART_IIR_INTID_CTI (6 << 1) +/* Interrupt identification: Interrupt ID mask */ +#define UART_IIR_INTID_MASK (7 << 1) +/* These bits are equivalent to UnFCR[0] */ +#define UART_IIR_FIFO_EN (3 << 6) +/* End of auto-baud interrupt */ +#define UART_IIR_ABEO_INT (1 << 8) +/* Auto-baud time-out interrupt */ +#define UART_IIR_ABTO_INT (1 << 9) +/* UART interrupt identification register bit mask */ +#define UART_IIR_BITMASK ((uint32_t)(0x3CF)) + +/********************************************************************** +* Macro defines for Macro defines for UART FIFO control register +**********************************************************************/ +/* UART FIFO enable */ +#define UART_FCR_FIFO_EN (1 << 0) +/* UART FIFO RX reset */ +#define UART_FCR_RX_RS (1 << 1) +/* UART FIFO TX reset */ +#define UART_FCR_TX_RS (1 << 2) +/* UART DMA mode selection */ +#define UART_FCR_DMAMODE_SEL (1 << 3) +/* UART FIFO trigger level 0: 1 character */ +#define UART_FCR_TRG_LEV0 (0 << 6) +/* UART FIFO trigger level 1: 4 character */ +#define UART_FCR_TRG_LEV1 (1 << 6) +/* UART FIFO trigger level 2: 8 character */ +#define UART_FCR_TRG_LEV2 (2 << 6) +/* UART FIFO trigger level 3: 14 character */ +#define UART_FCR_TRG_LEV3 (3 << 6) +/* UART FIFO control bit mask */ +#define UART_FCR_BITMASK ((uint8_t)(0xCF)) +#define UART_TX_FIFO_SIZE (16) + +/********************************************************************** +* Macro defines for Macro defines for UART line control register +**********************************************************************/ +/* UART 5 bit data mode */ +#define UART_LCR_WLEN5 (0 << 0) +/* UART 6 bit data mode */ +#define UART_LCR_WLEN6 (1 << 0) +/* UART 7 bit data mode */ +#define UART_LCR_WLEN7 (2 << 0) +/* UART 8 bit data mode */ +#define UART_LCR_WLEN8 (3 << 0) +/* UART One Stop Bits */ +#define UART_LCR_ONE_STOPBIT (0 << 2) +/* UART Two Stop Bits */ +#define UART_LCR_TWO_STOPBIT (1 << 2) + +/* UART Parity Disabled / No Parity */ +#define UART_LCR_NO_PARITY (0 << 3) +/* UART Parity Enable */ +#define UART_LCR_PARITY_EN (1 << 3) +/* UART Odd Parity Select */ +#define UART_LCR_PARITY_ODD (0 << 4) +/* UART Even Parity Select */ +#define UART_LCR_PARITY_EVEN (1 << 4) +/* UART force 1 stick parity */ +#define UART_LCR_PARITY_SP_1 (1 << 5) +/* UART force 0 stick parity */ +#define UART_LCR_PARITY_SP_0 ((1 << 5) | (1 << 4)) +/* UART Transmission Break enable */ +#define UART_LCR_BREAK_EN (1 << 6) +/* UART Divisor Latches Access bit enable */ +#define UART_LCR_DLAB_EN (1 << 7) +/* UART line control bit mask */ +#define UART_LCR_BITMASK ((uint8_t)(0xFF)) + +/********************************************************************** +* Macro defines for Macro defines for UART line status register +**********************************************************************/ +/* Line status register: Receive data ready */ +#define UART_LSR_RDR (1 << 0) +/* Line status register: Overrun error */ +#define UART_LSR_OE (1 << 1) +/* Line status register: Parity error */ +#define UART_LSR_PE (1 << 2) +/* Line status register: Framing error */ +#define UART_LSR_FE (1 << 3) +/* Line status register: Break interrupt */ +#define UART_LSR_BI (1 << 4) +/* Line status register: Transmit holding register empty */ +#define UART_LSR_THRE (1 << 5) +/* Line status register: Transmitter empty */ +#define UART_LSR_TEMT (1 << 6) +/* Error in RX FIFO */ +#define UART_LSR_RXFE (1 << 7) +/* UART Line status bit mask */ +#define UART_LSR_BITMASK ((uint8_t)(0xFF)) +#define UART_LSR_ERROR_MASK \ + (UART_LSR_OE | UART_LSR_PE | UART_LSR_FE | UART_LSR_BI | UART_LSR_RXFE) + +/********************************************************************** +* Macro defines for Macro defines for UART Scratch Pad Register +**********************************************************************/ + +/* UART Scratch Pad bit mask */ +#define UART_SCR_BIMASK ((uint8_t)(0xFF)) + +/*********************************************************************** +* Macro defines for Macro defines for UART Auto baudrate control register +**********************************************************************/ + +/* UART Auto-baud start */ +#define UART_ACR_START (1 << 0) +/* UART Auto baudrate Mode 1 */ +#define UART_ACR_MODE (1 << 1) +/* UART Auto baudrate restart */ +#define UART_ACR_AUTO_RESTART (1 << 2) +/* UART End of auto-baud interrupt clear */ +#define UART_ACR_ABEOINT_CLR (1 << 8) +/* UART Auto-baud time-out interrupt clear */ +#define UART_ACR_ABTOINT_CLR (1 << 9) +/* UART Auto Baudrate register bit mask */ +#define UART_ACR_BITMASK ((uint32_t)(0x307)) + +/********************************************************************* +* Macro defines for Macro defines for UART IrDA control register +**********************************************************************/ +/* IrDA mode enable */ +#define UART_ICR_IRDAEN (1 << 0) +/* IrDA serial input inverted */ +#define UART_ICR_IRDAINV (1 << 1) +/* IrDA fixed pulse width mode */ +#define UART_ICR_FIXPULSE_EN (1 << 2) +/* PulseDiv - Configures the pulse when FixPulseEn = 1 */ +#define UART_ICR_PULSEDIV(n) ((uint32_t)((n&0x07)<<3)) +/* UART IRDA bit mask */ +#define UART_ICR_BITMASK ((uint32_t)(0x3F)) + +/********************************************************************** +* Macro defines for Macro defines for UART half duplex register +**********************************************************************/ +/* enable half-duplex mode*/ +#define UART_HDEN_HDEN (1 << 0) + +/********************************************************************** +* Macro defines for Macro defines for UART smart card interface control register +**********************************************************************/ +/* enable asynchronous half-duplex smart card interface*/ +#define UART_SCICTRL_SCIEN (1 << 0) +/* NACK response is inhibited*/ +#define UART_SCICTRL_NACKDIS (1 << 1) +/* ISO7816-3 protocol T1 is selected*/ +#define UART_SCICTRL_PROTSEL_T1 (1 << 2) +/* number of retransmission*/ +#define UART_SCICTRL_TXRETRY(n) ((uint32_t)((n&0x07)<<5)) +/* Extra guard time*/ +#define UART_SCICTRL_GUARDTIME(n) ((uint32_t)((n&0xFF)<<8)) + +/********************************************************************* +* Macro defines for Macro defines for UART synchronous control register +**********************************************************************/ +/* enable synchronous mode*/ +#define UART_SYNCCTRL_SYNC (1 << 0) +/* synchronous master mode*/ +#define UART_SYNCCTRL_CSRC_MASTER (1 << 1) +/* sample on falling edge*/ +#define UART_SYNCCTRL_FES (1 << 2) +/* to be defined*/ +#define UART_SYNCCTRL_TSBYPASS (1 << 3) +/* continuous running clock enable (master mode only) */ +#define UART_SYNCCTRL_CSCEN (1 << 4) +/* Do not send start/stop bit */ +#define UART_SYNCCTRL_NOSTARTSTOP (1 << 5) +/* stop continuous clock */ +#define UART_SYNCCTRL_CCCLR (1 << 6) + +/********************************************************************* +* Macro defines for Macro defines for UART Fractional divider register +**********************************************************************/ + +/* Baud-rate generation pre-scaler divisor */ +#define UART_FDR_DIVADDVAL(n) ((uint32_t)(n&0x0F)) +/* Baud-rate pre-scaler multiplier value */ +#define UART_FDR_MULVAL(n) ((uint32_t)((n<<4)&0xF0)) +/* UART Fractional Divider register bit mask */ +#define UART_FDR_BITMASK ((uint32_t)(0xFF)) + +/********************************************************************* +* Macro defines for Macro defines for UART Tx Enable register +**********************************************************************/ + +#define UART_TER_TXEN (1 << 0) /* Transmit enable bit */ + +/********************************************************************** +* Macro defines for Macro defines for UART FIFO Level register +**********************************************************************/ +/* Reflects the current level of the UART receiver FIFO */ +#define UART_FIFOLVL_RX(n) ((uint32_t)(n&0x0F)) +/* Reflects the current level of the UART transmitter FIFO */ +#define UART_FIFOLVL_TX(n) ((uint32_t)((n>>8)&0x0F)) +/* UART FIFO Level Register bit mask */ +#define UART_FIFOLVL_BITMASK ((uint32_t)(0x0F0F)) + +/********************************************************************* +* UART enum +**********************************************************************/ + +/* +* UART Databit type definitions +*/ +typedef enum { + UART_DATABIT_5 = UART_LCR_WLEN5,/* UART 5 bit data mode */ + UART_DATABIT_6 = UART_LCR_WLEN6,/* UART 6 bit data mode */ + UART_DATABIT_7 = UART_LCR_WLEN7,/* UART 7 bit data mode */ + UART_DATABIT_8 = UART_LCR_WLEN8/* UART 8 bit data mode */ +} uart_databit_t; + +/* +* UART Stop bit type definitions +*/ +typedef enum { + /* UART 1 Stop Bits Select */ + UART_STOPBIT_1 = UART_LCR_ONE_STOPBIT, + /* UART 2 Stop Bits Select */ + UART_STOPBIT_2 = UART_LCR_TWO_STOPBIT +} uart_stopbit_t; + +/* +* UART Parity type definitions +*/ +typedef enum { + /* No parity */ + UART_PARITY_NONE = UART_LCR_NO_PARITY, + /* Odd parity */ + UART_PARITY_ODD = (UART_LCR_PARITY_ODD | UART_LCR_PARITY_EN), + /* Even parity */ + UART_PARITY_EVEN = (UART_LCR_PARITY_EVEN | UART_LCR_PARITY_EN), + /* Forced 1 stick parity */ + UART_PARITY_SP_1 = (UART_LCR_PARITY_SP_1 | UART_LCR_PARITY_EN), + /* Forced 0 stick parity */ + UART_PARITY_SP_0 = (UART_LCR_PARITY_SP_0 | UART_LCR_PARITY_EN) +} uart_parity_t; + +typedef enum { + UART0_NUM = UART0, + UART1_NUM = UART1, + UART2_NUM = UART2, + UART3_NUM = UART3 +} uart_num_t; + +typedef enum { + UART_NO_ERROR = 0, + UART_TIMEOUT_ERROR = 1 +} uart_error_t; + +typedef enum { + UART_RX_NO_DATA = 0, + UART_RX_DATA_READY = 1, + UART_RX_DATA_ERROR = 2 +} uart_rx_data_ready_t; + +/* function prototypes */ + +BEGIN_DECLS + +/* Init UART and set PLL1 as clock source (PCLK) */ +void uart_init(uart_num_t uart_num, uart_databit_t data_nb_bits, + uart_stopbit_t data_nb_stop, uart_parity_t data_parity, + uint16_t uart_divisor, uint8_t uart_divaddval, uint8_t uart_mulval); + +uart_rx_data_ready_t uart_rx_data_ready(uart_num_t uart_num); +uint8_t uart_read(uart_num_t uart_num); +uint8_t uart_read_timeout(uart_num_t uart_num, uint32_t rx_timeout_nb_cycles, + uart_error_t *error); +void uart_write(uart_num_t uart_num, uint8_t data); + +END_DECLS + +#endif diff --git a/libopencm3/include/libopencm3/lpc43xx/usb.h b/libopencm3/include/libopencm3/lpc43xx/usb.h new file mode 100644 index 0000000..2f1f156 --- /dev/null +++ b/libopencm3/include/libopencm3/lpc43xx/usb.h @@ -0,0 +1,1337 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2012 Michael Ossmann <mike@ossmann.com> + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see <http://www.gnu.org/licenses/>. + */ + +#ifndef LPC43XX_USB_H +#define LPC43XX_USB_H + +#include <libopencm3/cm3/common.h> +#include <libopencm3/lpc43xx/memorymap.h> + +#define BIT_MASK(base_name) \ + (((1 << base_name##_WIDTH) - 1) << base_name##_SHIFT) +#define BIT_ARG(base_name, x) ((x) << base_name##_SHIFT) + +/* USB device data structures */ + +/* "The software must ensure that no interface data structure reachable + * by the Device controller crosses a 4kB-page boundary." + */ + +/* --- Endpoint Transfer Descriptor (dTD) ---------------------------------- */ + +typedef struct usb_transfer_descriptor_t usb_transfer_descriptor_t; +struct usb_transfer_descriptor_t { + volatile usb_transfer_descriptor_t *next_dtd_pointer; + volatile uint32_t total_bytes; + volatile uint32_t buffer_pointer_page[5]; + volatile uint32_t _reserved; +}; + +#define USB_TD_NEXT_DTD_POINTER_TERMINATE_SHIFT (0) +#define USB_TD_NEXT_DTD_POINTER_TERMINATE \ + ((volatile usb_transfer_descriptor_t *) \ + (1 << USB_TD_NEXT_DTD_POINTER_TERMINATE_SHIFT)) + +#define USB_TD_DTD_TOKEN_TOTAL_BYTES_SHIFT (16) +#define USB_TD_DTD_TOKEN_TOTAL_BYTES_WIDTH (15) +#define USB_TD_DTD_TOKEN_TOTAL_BYTES_MASK BIT_MASK(USB_TD_DTD_TOKEN_TOTAL_BYTES) +#define USB_TD_DTD_TOKEN_TOTAL_BYTES(x) BIT_ARG(USB_TD_DTD_TOKEN_TOTAL_BYTES, x) + +#define USB_TD_DTD_TOKEN_IOC_SHIFT (15) +#define USB_TD_DTD_TOKEN_IOC (1 << USB_TD_DTD_TOKEN_IOC_SHIFT) + +#define USB_TD_DTD_TOKEN_MULTO_SHIFT (10) +#define USB_TD_DTD_TOKEN_MULTO_WIDTH (2) +#define USB_TD_DTD_TOKEN_MULTO_MASK BIT_MASK(USB_TD_DTD_TOKEN_MULTO) +#define USB_TD_DTD_TOKEN_MULTO(x) BIT_ARG(USB_TD_DTD_TOKEN_MULTO, x) + +#define USB_TD_DTD_TOKEN_STATUS_ACTIVE_SHIFT (7) +#define USB_TD_DTD_TOKEN_STATUS_ACTIVE \ + (1 << USB_TD_DTD_TOKEN_STATUS_ACTIVE_SHIFT) + +#define USB_TD_DTD_TOKEN_STATUS_HALTED_SHIFT (6) +#define USB_TD_DTD_TOKEN_STATUS_HALTED \ + (1 << USB_TD_DTD_TOKEN_STATUS_HALTED_SHIFT) + +#define USB_TD_DTD_TOKEN_STATUS_BUFFER_ERROR_SHIFT (5) +#define USB_TD_DTD_TOKEN_STATUS_BUFFER_ERROR \ + (1 << USB_TD_DTD_TOKEN_STATUS_BUFFER_ERROR_SHIFT) + +#define USB_TD_DTD_TOKEN_STATUS_TRANSACTION_ERROR_SHIFT (3) +#define USB_TD_DTD_TOKEN_STATUS_TRANSACTION_ERROR \ + (1 << USB_TD_DTD_TOKEN_STATUS_TRANSACTION_ERROR_SHIFT) + +/* --- Endpoint Queue Head (dQH) ------------------------------------------- */ + +/* - must be aligned on 64-byte boundaries. */ +typedef struct { + volatile uint32_t capabilities; + volatile usb_transfer_descriptor_t *current_dtd_pointer; + volatile usb_transfer_descriptor_t *next_dtd_pointer; + volatile uint32_t total_bytes; + volatile uint32_t buffer_pointer_page[5]; + volatile uint32_t _reserved_0; + volatile uint8_t setup[8]; + volatile uint32_t _reserved_1[4]; +} usb_queue_head_t; + +#define USB_QH_CAPABILITIES_IOS_SHIFT (15) +#define USB_QH_CAPABILITIES_IOS (1 << USB_QH_CAPABILITIES_IOS_SHIFT) + +#define USB_QH_CAPABILITIES_MPL_SHIFT (16) +#define USB_QH_CAPABILITIES_MPL_WIDTH (11) +#define USB_QH_CAPABILITIES_MPL_MASK BIT_MASK(USB_QH_CAPABILITIES_MPL) +#define USB_QH_CAPABILITIES_MPL(x) BIT_ARG(USB_QH_CAPABILITIES_MPL, x) + +#define USB_QH_CAPABILITIES_ZLT_SHIFT (29) +#define USB_QH_CAPABILITIES_ZLT (1 << USB_QH_CAPABILITIES_ZLT_SHIFT) + +#define USB_QH_CAPABILITIES_MULT_SHIFT (30) +#define USB_QH_CAPABILITIES_MULT_WIDTH (2) +#define USB_QH_CAPABILITIES_MULT_MASK BIT_MASK(USB_QH_CAPABILITIES_MULT) +#define USB_QH_CAPABILITIES_MULT(x) BIT_ARG(USB_QH_CAPABILITIES_MULT, x) + +/* --- USB0 registers ------------------------------------------------------ */ + +/* Device/host capability registers */ + +/* Capability register length */ +#define USB0_CAPLENGTH MMIO32(USB0_BASE + 0x100) + +/* Host controller structural parameters */ +#define USB0_HCSPARAMS MMIO32(USB0_BASE + 0x104) + +/* Host controller capability parameters */ +#define USB0_HCCPARAMS MMIO32(USB0_BASE + 0x108) + +/* Device interface version number */ +#define USB0_DCIVERSION MMIO32(USB0_BASE + 0x120) + +/* Device controller capability parameters */ +#define USB0_DCCPARAMS MMIO32(USB0_BASE + 0x124) + + +/* Device/host operational registers */ + +/* USB command (device mode) */ +#define USB0_USBCMD_D MMIO32(USB0_BASE + 0x140) + +/* USB command (host mode) */ +#define USB0_USBCMD_H MMIO32(USB0_BASE + 0x140) + +/* USB status (device mode) */ +#define USB0_USBSTS_D MMIO32(USB0_BASE + 0x144) + +/* USB status (host mode) */ +#define USB0_USBSTS_H MMIO32(USB0_BASE + 0x144) + +/* USB interrupt enable (device mode) */ +#define USB0_USBINTR_D MMIO32(USB0_BASE + 0x148) + +/* USB interrupt enable (host mode) */ +#define USB0_USBINTR_H MMIO32(USB0_BASE + 0x148) + +/* USB frame index (device mode) */ +#define USB0_FRINDEX_D MMIO32(USB0_BASE + 0x14C) + +/* USB frame index (host mode) */ +#define USB0_FRINDEX_H MMIO32(USB0_BASE + 0x14C) + +/* USB device address (device mode) */ +#define USB0_DEVICEADDR MMIO32(USB0_BASE + 0x154) + +/* Frame list base address (host mode) */ +#define USB0_PERIODICLISTBASE MMIO32(USB0_BASE + 0x154) + +/* Address of endpoint list in memory */ +#define USB0_ENDPOINTLISTADDR MMIO32(USB0_BASE + 0x158) + +/* Asynchronous list address */ +#define USB0_ASYNCLISTADDR MMIO32(USB0_BASE + 0x158) + +/* Asynchronous buffer status for embedded TT (host mode) */ +#define USB0_TTCTRL MMIO32(USB0_BASE + 0x15C) + +/* Programmable burst size */ +#define USB0_BURSTSIZE MMIO32(USB0_BASE + 0x160) + +/* Host transmit pre-buffer packet tuning (host mode) */ +#define USB0_TXFILLTUNING MMIO32(USB0_BASE + 0x164) + +/* Length of virtual frame */ +#define USB0_BINTERVAL MMIO32(USB0_BASE + 0x174) + +/* Endpoint NAK (device mode) */ +#define USB0_ENDPTNAK MMIO32(USB0_BASE + 0x178) + +/* Endpoint NAK Enable (device mode) */ +#define USB0_ENDPTNAKEN MMIO32(USB0_BASE + 0x17C) + +/* Port 1 status/control (device mode) */ +#define USB0_PORTSC1_D MMIO32(USB0_BASE + 0x184) + +/* Port 1 status/control (host mode) */ +#define USB0_PORTSC1_H MMIO32(USB0_BASE + 0x184) + +/* OTG status and control */ +#define USB0_OTGSC MMIO32(USB0_BASE + 0x1A4) + +/* USB device mode (device mode) */ +#define USB0_USBMODE_D MMIO32(USB0_BASE + 0x1A8) + +/* USB device mode (host mode) */ +#define USB0_USBMODE_H MMIO32(USB0_BASE + 0x1A8) + + +/* Device endpoint registers */ + +/* Endpoint setup status */ +#define USB0_ENDPTSETUPSTAT MMIO32(USB0_BASE + 0x1AC) + +/* Endpoint initialization */ +#define USB0_ENDPTPRIME MMIO32(USB0_BASE + 0x1B0) + +/* Endpoint de-initialization */ +#define USB0_ENDPTFLUSH MMIO32(USB0_BASE + 0x1B4) + +/* Endpoint status */ +#define USB0_ENDPTSTAT MMIO32(USB0_BASE + 0x1B8) + +/* Endpoint complete */ +#define USB0_ENDPTCOMPLETE MMIO32(USB0_BASE + 0x1BC) + +/* Endpoint control */ +#define USB0_ENDPTCTRL(logical_ep) MMIO32(USB0_BASE + 0x1C0 + \ + (logical_ep * 4)) + +/* Endpoint control 0 */ +#define USB0_ENDPTCTRL0 USB0_ENDPTCTRL(0) + +/* Endpoint control 1 */ +#define USB0_ENDPTCTRL1 USB0_ENDPTCTRL(1) + +/* Endpoint control 2 */ +#define USB0_ENDPTCTRL2 USB0_ENDPTCTRL(2) + +/* Endpoint control 3 */ +#define USB0_ENDPTCTRL3 USB0_ENDPTCTRL(3) + +/* Endpoint control 4 */ +#define USB0_ENDPTCTRL4 USB0_ENDPTCTRL(4) + +/* Endpoint control 5 */ +#define USB0_ENDPTCTRL5 USB0_ENDPTCTRL(5) + +/* --- USB0_CAPLENGTH values ------------------------------------ */ + +/* CAPLENGTH: Indicates offset to add to the register base address at the + beginning of the Operational Register */ +#define USB0_CAPLENGTH_CAPLENGTH_SHIFT (0) +#define USB0_CAPLENGTH_CAPLENGTH_MASK (0xff << USB0_CAPLENGTH_CAPLENGTH_SHIFT) +#define USB0_CAPLENGTH_CAPLENGTH(x) ((x) << USB0_CAPLENGTH_CAPLENGTH_SHIFT) + +/* HCIVERSION: BCD encoding of the EHCI revision number supported by this host + controller */ +#define USB0_CAPLENGTH_HCIVERSION_SHIFT (8) +#define USB0_CAPLENGTH_HCIVERSION_MASK \ + (0xffff << USB0_CAPLENGTH_HCIVERSION_SHIFT) +#define USB0_CAPLENGTH_HCIVERSION(x) ((x) << USB0_CAPLENGTH_HCIVERSION_SHIFT) + +/* --- USB0_HCSPARAMS values ------------------------------------ */ + +/* N_PORTS: Number of downstream ports */ +#define USB0_HCSPARAMS_N_PORTS_SHIFT (0) +#define USB0_HCSPARAMS_N_PORTS_MASK (0xf << USB0_HCSPARAMS_N_PORTS_SHIFT) +#define USB0_HCSPARAMS_N_PORTS(x) ((x) << USB0_HCSPARAMS_N_PORTS_SHIFT) + +/* PPC: Port Power Control */ +#define USB0_HCSPARAMS_PPC_SHIFT (4) +#define USB0_HCSPARAMS_PPC (1 << USB0_HCSPARAMS_PPC_SHIFT) + +/* N_PCC: Number of Ports per Companion Controller */ +#define USB0_HCSPARAMS_N_PCC_SHIFT (8) +#define USB0_HCSPARAMS_N_PCC_MASK (0xf << USB0_HCSPARAMS_N_PCC_SHIFT) +#define USB0_HCSPARAMS_N_PCC(x) ((x) << USB0_HCSPARAMS_N_PCC_SHIFT) + +/* N_CC: Number of Companion Controller */ +#define USB0_HCSPARAMS_N_CC_SHIFT (12) +#define USB0_HCSPARAMS_N_CC_MASK (0xf << USB0_HCSPARAMS_N_CC_SHIFT) +#define USB0_HCSPARAMS_N_CC(x) ((x) << USB0_HCSPARAMS_N_CC_SHIFT) + +/* PI: Port indicators */ +#define USB0_HCSPARAMS_PI_SHIFT (16) +#define USB0_HCSPARAMS_PI (1 << USB0_HCSPARAMS_PI_SHIFT) + +/* N_PTT: Number of Ports per Transaction Translator */ +#define USB0_HCSPARAMS_N_PTT_SHIFT (20) +#define USB0_HCSPARAMS_N_PTT_MASK (0xf << USB0_HCSPARAMS_N_PTT_SHIFT) +#define USB0_HCSPARAMS_N_PTT(x) ((x) << USB0_HCSPARAMS_N_PTT_SHIFT) + +/* N_TT: Number of Transaction Translators */ +#define USB0_HCSPARAMS_N_TT_SHIFT (24) +#define USB0_HCSPARAMS_N_TT_MASK (0xf << USB0_HCSPARAMS_N_TT_SHIFT) +#define USB0_HCSPARAMS_N_TT(x) ((x) << USB0_HCSPARAMS_N_TT_SHIFT) + +/* --- USB0_HCCPARAMS values ------------------------------------ */ + +/* ADC: 64-bit Addressing Capability */ +#define USB0_HCCPARAMS_ADC_SHIFT (0) +#define USB0_HCCPARAMS_ADC (1 << USB0_HCCPARAMS_ADC_SHIFT) + +/* PFL: Programmable Frame List Flag */ +#define USB0_HCCPARAMS_PFL_SHIFT (1) +#define USB0_HCCPARAMS_PFL (1 << USB0_HCCPARAMS_PFL_SHIFT) + +/* ASP: Asynchronous Schedule Park Capability */ +#define USB0_HCCPARAMS_ASP_SHIFT (2) +#define USB0_HCCPARAMS_ASP (1 << USB0_HCCPARAMS_ASP_SHIFT) + +/* IST: Isochronous Scheduling Threshold */ +#define USB0_HCCPARAMS_IST_SHIFT (4) +#define USB0_HCCPARAMS_IST_MASK (0xf << USB0_HCCPARAMS_IST_SHIFT) +#define USB0_HCCPARAMS_IST(x) ((x) << USB0_HCCPARAMS_IST_SHIFT) + +/* EECP: EHCI Extended Capabilities Pointer */ +#define USB0_HCCPARAMS_EECP_SHIFT (8) +#define USB0_HCCPARAMS_EECP_MASK (0xf << USB0_HCCPARAMS_EECP_SHIFT) +#define USB0_HCCPARAMS_EECP(x) ((x) << USB0_HCCPARAMS_EECP_SHIFT) + +/* --- USB0_DCCPARAMS values ------------------------------------ */ + +/* DEN: Device Endpoint Number */ +#define USB0_DCCPARAMS_DEN_SHIFT (0) +#define USB0_DCCPARAMS_DEN_MASK (0x1f << USB0_DCCPARAMS_DEN_SHIFT) +#define USB0_DCCPARAMS_DEN(x) ((x) << USB0_DCCPARAMS_DEN_SHIFT) + +/* DC: Device Capable */ +#define USB0_DCCPARAMS_DC_SHIFT (7) +#define USB0_DCCPARAMS_DC (1 << USB0_DCCPARAMS_DC_SHIFT) + +/* HC: Host Capable */ +#define USB0_DCCPARAMS_HC_SHIFT (8) +#define USB0_DCCPARAMS_HC (1 << USB0_DCCPARAMS_HC_SHIFT) + +/* --- USB0_USBCMD_D values ------------------------------------- */ + +/* RS: Run/Stop */ +#define USB0_USBCMD_D_RS_SHIFT (0) +#define USB0_USBCMD_D_RS (1 << USB0_USBCMD_D_RS_SHIFT) + +/* RST: Controller reset */ +#define USB0_USBCMD_D_RST_SHIFT (1) +#define USB0_USBCMD_D_RST (1 << USB0_USBCMD_D_RST_SHIFT) + +/* SUTW: Setup trip wire */ +#define USB0_USBCMD_D_SUTW_SHIFT (13) +#define USB0_USBCMD_D_SUTW (1 << USB0_USBCMD_D_SUTW_SHIFT) + +/* ATDTW: Add dTD trip wire */ +#define USB0_USBCMD_D_ATDTW_SHIFT (14) +#define USB0_USBCMD_D_ATDTW (1 << USB0_USBCMD_D_ATDTW_SHIFT) + +/* ITC: Interrupt threshold control */ +#define USB0_USBCMD_D_ITC_SHIFT (16) +#define USB0_USBCMD_D_ITC_MASK (0xff << USB0_USBCMD_D_ITC_SHIFT) +#define USB0_USBCMD_D_ITC(x) ((x) << USB0_USBCMD_D_ITC_SHIFT) + +/* --- USB0_USBCMD_H values ------------------------------------- */ + +/* RS: Run/Stop */ +#define USB0_USBCMD_H_RS_SHIFT (0) +#define USB0_USBCMD_H_RS (1 << USB0_USBCMD_H_RS_SHIFT) + +/* RST: Controller reset */ +#define USB0_USBCMD_H_RST_SHIFT (1) +#define USB0_USBCMD_H_RST (1 << USB0_USBCMD_H_RST_SHIFT) + +/* FS0: Bit 0 of the Frame List Size bits */ +#define USB0_USBCMD_H_FS0_SHIFT (2) +#define USB0_USBCMD_H_FS0 (1 << USB0_USBCMD_H_FS0_SHIFT) + +/* FS1: Bit 1 of the Frame List Size bits */ +#define USB0_USBCMD_H_FS1_SHIFT (3) +#define USB0_USBCMD_H_FS1 (1 << USB0_USBCMD_H_FS1_SHIFT) + +/* PSE: This bit controls whether the host controller skips processing the +periodic schedule */ +#define USB0_USBCMD_H_PSE_SHIFT (4) +#define USB0_USBCMD_H_PSE (1 << USB0_USBCMD_H_PSE_SHIFT) + +/* ASE: This bit controls whether the host controller skips processing the +asynchronous schedule */ +#define USB0_USBCMD_H_ASE_SHIFT (5) +#define USB0_USBCMD_H_ASE (1 << USB0_USBCMD_H_ASE_SHIFT) + +/* IAA: This bit is used as a doorbell by software to tell the host controller +to issue an interrupt the next time it advances asynchronous schedule */ +#define USB0_USBCMD_H_IAA_SHIFT (6) +#define USB0_USBCMD_H_IAA (1 << USB0_USBCMD_H_IAA_SHIFT) + +/* ASP1_0: Asynchronous schedule park mode */ +#define USB0_USBCMD_H_ASP1_0_SHIFT (8) +#define USB0_USBCMD_H_ASP1_0_MASK (0x3 << USB0_USBCMD_H_ASP1_0_SHIFT) +#define USB0_USBCMD_H_ASP1_0(x) ((x) << USB0_USBCMD_H_ASP1_0_SHIFT) + +/* ASPE: Asynchronous Schedule Park Mode Enable */ +#define USB0_USBCMD_H_ASPE_SHIFT (11) +#define USB0_USBCMD_H_ASPE (1 << USB0_USBCMD_H_ASPE_SHIFT) + +/* FS2: Bit 2 of the Frame List Size bits */ +#define USB0_USBCMD_H_FS2_SHIFT (15) +#define USB0_USBCMD_H_FS2 (1 << USB0_USBCMD_H_FS2_SHIFT) + +/* ITC: Interrupt threshold control */ +#define USB0_USBCMD_H_ITC_SHIFT (16) +#define USB0_USBCMD_H_ITC_MASK (0xff << USB0_USBCMD_H_ITC_SHIFT) +#define USB0_USBCMD_H_ITC(x) ((x) << USB0_USBCMD_H_ITC_SHIFT) + +/* --- USB0_USBSTS_D values ------------------------------------- */ + +/* UI: USB interrupt */ +#define USB0_USBSTS_D_UI_SHIFT (0) +#define USB0_USBSTS_D_UI (1 << USB0_USBSTS_D_UI_SHIFT) + +/* UEI: USB error interrupt */ +#define USB0_USBSTS_D_UEI_SHIFT (1) +#define USB0_USBSTS_D_UEI (1 << USB0_USBSTS_D_UEI_SHIFT) + +/* PCI: Port change detect */ +#define USB0_USBSTS_D_PCI_SHIFT (2) +#define USB0_USBSTS_D_PCI (1 << USB0_USBSTS_D_PCI_SHIFT) + +/* URI: USB reset received */ +#define USB0_USBSTS_D_URI_SHIFT (6) +#define USB0_USBSTS_D_URI (1 << USB0_USBSTS_D_URI_SHIFT) + +/* SRI: SOF received */ +#define USB0_USBSTS_D_SRI_SHIFT (7) +#define USB0_USBSTS_D_SRI (1 << USB0_USBSTS_D_SRI_SHIFT) + +/* SLI: DCSuspend */ +#define USB0_USBSTS_D_SLI_SHIFT (8) +#define USB0_USBSTS_D_SLI (1 << USB0_USBSTS_D_SLI_SHIFT) + +/* NAKI: NAK interrupt bit */ +#define USB0_USBSTS_D_NAKI_SHIFT (16) +#define USB0_USBSTS_D_NAKI (1 << USB0_USBSTS_D_NAKI_SHIFT) + +/* --- USB0_USBSTS_H values ------------------------------------- */ + +/* UI: USB interrupt */ +#define USB0_USBSTS_H_UI_SHIFT (0) +#define USB0_USBSTS_H_UI (1 << USB0_USBSTS_H_UI_SHIFT) + +/* UEI: USB error interrupt */ +#define USB0_USBSTS_H_UEI_SHIFT (1) +#define USB0_USBSTS_H_UEI (1 << USB0_USBSTS_H_UEI_SHIFT) + +/* PCI: Port change detect */ +#define USB0_USBSTS_H_PCI_SHIFT (2) +#define USB0_USBSTS_H_PCI (1 << USB0_USBSTS_H_PCI_SHIFT) + +/* FRI: Frame list roll-over */ +#define USB0_USBSTS_H_FRI_SHIFT (3) +#define USB0_USBSTS_H_FRI (1 << USB0_USBSTS_H_FRI_SHIFT) + +/* AAI: Interrupt on async advance */ +#define USB0_USBSTS_H_AAI_SHIFT (5) +#define USB0_USBSTS_H_AAI (1 << USB0_USBSTS_H_AAI_SHIFT) + +/* SRI: SOF received */ +#define USB0_USBSTS_H_SRI_SHIFT (7) +#define USB0_USBSTS_H_SRI (1 << USB0_USBSTS_H_SRI_SHIFT) + +/* HCH: HCHalted */ +#define USB0_USBSTS_H_HCH_SHIFT (12) +#define USB0_USBSTS_H_HCH (1 << USB0_USBSTS_H_HCH_SHIFT) + +/* RCL: Reclamation */ +#define USB0_USBSTS_H_RCL_SHIFT (13) +#define USB0_USBSTS_H_RCL (1 << USB0_USBSTS_H_RCL_SHIFT) + +/* PS: Periodic schedule status */ +#define USB0_USBSTS_H_PS_SHIFT (14) +#define USB0_USBSTS_H_PS (1 << USB0_USBSTS_H_PS_SHIFT) + +/* AS: Asynchronous schedule status */ +#define USB0_USBSTS_H_AS_SHIFT (15) +#define USB0_USBSTS_H_AS (1 << USB0_USBSTS_H_AS_SHIFT) + +/* UAI: USB host asynchronous interrupt (USBHSTASYNCINT) */ +#define USB0_USBSTS_H_UAI_SHIFT (18) +#define USB0_USBSTS_H_UAI (1 << USB0_USBSTS_H_UAI_SHIFT) + +/* UPI: USB host periodic interrupt (USBHSTPERINT) */ +#define USB0_USBSTS_H_UPI_SHIFT (19) +#define USB0_USBSTS_H_UPI (1 << USB0_USBSTS_H_UPI_SHIFT) + +/* --- USB0_USBINTR_D values ------------------------------------ */ + +/* UE: USB interrupt enable */ +#define USB0_USBINTR_D_UE_SHIFT (0) +#define USB0_USBINTR_D_UE (1 << USB0_USBINTR_D_UE_SHIFT) + +/* UEE: USB error interrupt enable */ +#define USB0_USBINTR_D_UEE_SHIFT (1) +#define USB0_USBINTR_D_UEE (1 << USB0_USBINTR_D_UEE_SHIFT) + +/* PCE: Port change detect enable */ +#define USB0_USBINTR_D_PCE_SHIFT (2) +#define USB0_USBINTR_D_PCE (1 << USB0_USBINTR_D_PCE_SHIFT) + +/* URE: USB reset enable */ +#define USB0_USBINTR_D_URE_SHIFT (6) +#define USB0_USBINTR_D_URE (1 << USB0_USBINTR_D_URE_SHIFT) + +/* SRE: SOF received enable */ +#define USB0_USBINTR_D_SRE_SHIFT (7) +#define USB0_USBINTR_D_SRE (1 << USB0_USBINTR_D_SRE_SHIFT) + +/* SLE: Sleep enable */ +#define USB0_USBINTR_D_SLE_SHIFT (8) +#define USB0_USBINTR_D_SLE (1 << USB0_USBINTR_D_SLE_SHIFT) + +/* NAKE: NAK interrupt enable */ +#define USB0_USBINTR_D_NAKE_SHIFT (16) +#define USB0_USBINTR_D_NAKE (1 << USB0_USBINTR_D_NAKE_SHIFT) + +/* --- USB0_USBINTR_H values ------------------------------------ */ + +/* UE: USB interrupt enable */ +#define USB0_USBINTR_H_UE_SHIFT (0) +#define USB0_USBINTR_H_UE (1 << USB0_USBINTR_H_UE_SHIFT) + +/* UEE: USB error interrupt enable */ +#define USB0_USBINTR_H_UEE_SHIFT (1) +#define USB0_USBINTR_H_UEE (1 << USB0_USBINTR_H_UEE_SHIFT) + +/* PCE: Port change detect enable */ +#define USB0_USBINTR_H_PCE_SHIFT (2) +#define USB0_USBINTR_H_PCE (1 << USB0_USBINTR_H_PCE_SHIFT) + +/* FRE: Frame list rollover enable */ +#define USB0_USBINTR_H_FRE_SHIFT (3) +#define USB0_USBINTR_H_FRE (1 << USB0_USBINTR_H_FRE_SHIFT) + +/* AAE: Interrupt on asynchronous advance enable */ +#define USB0_USBINTR_H_AAE_SHIFT (5) +#define USB0_USBINTR_H_AAE (1 << USB0_USBINTR_H_AAE_SHIFT) + +/* SRE: SOF received enable */ +#define USB0_USBINTR_H_SRE_SHIFT (7) +#define USB0_USBINTR_H_SRE (1 << USB0_USBINTR_H_SRE_SHIFT) + +/* UAIE: USB host asynchronous interrupt enable */ +#define USB0_USBINTR_H_UAIE_SHIFT (18) +#define USB0_USBINTR_H_UAIE (1 << USB0_USBINTR_H_UAIE_SHIFT) + +/* UPIA: USB host periodic interrupt enable */ +#define USB0_USBINTR_H_UPIA_SHIFT (19) +#define USB0_USBINTR_H_UPIA (1 << USB0_USBINTR_H_UPIA_SHIFT) + +/* --- USB0_FRINDEX_D values ------------------------------------ */ + +/* FRINDEX2_0: Current micro frame number */ +#define USB0_FRINDEX_D_FRINDEX2_0_SHIFT (0) +#define USB0_FRINDEX_D_FRINDEX2_0_MASK (0x7 << USB0_FRINDEX_D_FRINDEX2_0_SHIFT) +#define USB0_FRINDEX_D_FRINDEX2_0(x) ((x) << USB0_FRINDEX_D_FRINDEX2_0_SHIFT) + +/* FRINDEX13_3: Current frame number of the last frame transmitted */ +#define USB0_FRINDEX_D_FRINDEX13_3_SHIFT (3) +#define USB0_FRINDEX_D_FRINDEX13_3_MASK \ + (0x7ff << USB0_FRINDEX_D_FRINDEX13_3_SHIFT) +#define USB0_FRINDEX_D_FRINDEX13_3(x) ((x) << USB0_FRINDEX_D_FRINDEX13_3_SHIFT) + +/* --- USB0_FRINDEX_H values ------------------------------------ */ + +/* FRINDEX2_0: Current micro frame number */ +#define USB0_FRINDEX_H_FRINDEX2_0_SHIFT (0) +#define USB0_FRINDEX_H_FRINDEX2_0_MASK (0x7 << USB0_FRINDEX_H_FRINDEX2_0_SHIFT) +#define USB0_FRINDEX_H_FRINDEX2_0(x) ((x) << USB0_FRINDEX_H_FRINDEX2_0_SHIFT) + +/* FRINDEX12_3: Frame list current index */ +#define USB0_FRINDEX_H_FRINDEX12_3_SHIFT (3) +#define USB0_FRINDEX_H_FRINDEX12_3_MASK \ + (0x3ff << USB0_FRINDEX_H_FRINDEX12_3_SHIFT) +#define USB0_FRINDEX_H_FRINDEX12_3(x) ((x) << USB0_FRINDEX_H_FRINDEX12_3_SHIFT) + +/* --- USB0_DEVICEADDR values ----------------------------------- */ + +/* USBADRA: Device address advance */ +#define USB0_DEVICEADDR_USBADRA_SHIFT (24) +#define USB0_DEVICEADDR_USBADRA (1 << USB0_DEVICEADDR_USBADRA_SHIFT) + +/* USBADR: USB device address */ +#define USB0_DEVICEADDR_USBADR_SHIFT (25) +#define USB0_DEVICEADDR_USBADR_MASK (0x7f << USB0_DEVICEADDR_USBADR_SHIFT) +#define USB0_DEVICEADDR_USBADR(x) ((x) << USB0_DEVICEADDR_USBADR_SHIFT) + +/* --- USB0_PERIODICLISTBASE values ----------------------------- */ + +/* PERBASE31_12: Base Address (Low) */ +#define USB0_PERIODICLISTBASE_PERBASE31_12_SHIFT (12) +#define USB0_PERIODICLISTBASE_PERBASE31_12_MASK \ + (0xfffff << USB0_PERIODICLISTBASE_PERBASE31_12_SHIFT) +#define USB0_PERIODICLISTBASE_PERBASE31_12(x) \ + ((x) << USB0_PERIODICLISTBASE_PERBASE31_12_SHIFT) + +/* --- USB0_ENDPOINTLISTADDR values ----------------------------- */ + +/* EPBASE31_11: Endpoint list pointer (low) */ +#define USB0_ENDPOINTLISTADDR_EPBASE31_11_SHIFT (11) +#define USB0_ENDPOINTLISTADDR_EPBASE31_11_MASK \ + (0x1fffff << USB0_ENDPOINTLISTADDR_EPBASE31_11_SHIFT) +#define USB0_ENDPOINTLISTADDR_EPBASE31_11(x) \ + ((x) << USB0_ENDPOINTLISTADDR_EPBASE31_11_SHIFT) + +/* --- USB0_ASYNCLISTADDR values -------------------------------- */ + +/* ASYBASE31_5: Link pointer (Low) LPL */ +#define USB0_ASYNCLISTADDR_ASYBASE31_5_SHIFT (5) +#define USB0_ASYNCLISTADDR_ASYBASE31_5_MASK \ + (0x7ffffff << USB0_ASYNCLISTADDR_ASYBASE31_5_SHIFT) +#define USB0_ASYNCLISTADDR_ASYBASE31_5(x) \ + ((x) << USB0_ASYNCLISTADDR_ASYBASE31_5_SHIFT) + +/* --- USB0_TTCTRL values --------------------------------------- */ + +/* TTHA: Hub address when FS or LS device are connected directly */ +#define USB0_TTCTRL_TTHA_SHIFT (24) +#define USB0_TTCTRL_TTHA_MASK (0x7f << USB0_TTCTRL_TTHA_SHIFT) +#define USB0_TTCTRL_TTHA(x) ((x) << USB0_TTCTRL_TTHA_SHIFT) + +/* --- USB0_BURSTSIZE values ------------------------------------ */ + +/* RXPBURST: Programmable RX burst length */ +#define USB0_BURSTSIZE_RXPBURST_SHIFT (0) +#define USB0_BURSTSIZE_RXPBURST_MASK (0xff << USB0_BURSTSIZE_RXPBURST_SHIFT) +#define USB0_BURSTSIZE_RXPBURST(x) ((x) << USB0_BURSTSIZE_RXPBURST_SHIFT) + +/* TXPBURST: Programmable TX burst length */ +#define USB0_BURSTSIZE_TXPBURST_SHIFT (8) +#define USB0_BURSTSIZE_TXPBURST_MASK (0xff << USB0_BURSTSIZE_TXPBURST_SHIFT) +#define USB0_BURSTSIZE_TXPBURST(x) ((x) << USB0_BURSTSIZE_TXPBURST_SHIFT) + +/* --- USB0_TXFILLTUNING values --------------------------------- */ + +/* TXSCHOH: FIFO burst threshold */ +#define USB0_TXFILLTUNING_TXSCHOH_SHIFT (0) +#define USB0_TXFILLTUNING_TXSCHOH_MASK (0xff << USB0_TXFILLTUNING_TXSCHOH_SHIFT) +#define USB0_TXFILLTUNING_TXSCHOH(x) ((x) << USB0_TXFILLTUNING_TXSCHOH_SHIFT) + +/* TXSCHEATLTH: Scheduler health counter */ +#define USB0_TXFILLTUNING_TXSCHEATLTH_SHIFT (8) +#define USB0_TXFILLTUNING_TXSCHEATLTH_MASK \ + (0x1f << USB0_TXFILLTUNING_TXSCHEATLTH_SHIFT) +#define USB0_TXFILLTUNING_TXSCHEATLTH(x) \ + ((x) << USB0_TXFILLTUNING_TXSCHEATLTH_SHIFT) + +/* TXFIFOTHRES: Scheduler overhead */ +#define USB0_TXFILLTUNING_TXFIFOTHRES_SHIFT (16) +#define USB0_TXFILLTUNING_TXFIFOTHRES_MASK \ + (0x3f << USB0_TXFILLTUNING_TXFIFOTHRES_SHIFT) +#define USB0_TXFILLTUNING_TXFIFOTHRES(x) \ + ((x) << USB0_TXFILLTUNING_TXFIFOTHRES_SHIFT) + +/* --- USB0_BINTERVAL values ------------------------------------ */ + +/* BINT: bInterval value */ +#define USB0_BINTERVAL_BINT_SHIFT (0) +#define USB0_BINTERVAL_BINT_MASK (0xf << USB0_BINTERVAL_BINT_SHIFT) +#define USB0_BINTERVAL_BINT(x) ((x) << USB0_BINTERVAL_BINT_SHIFT) + +/* --- USB0_ENDPTNAK values ------------------------------------- */ + +/* EPRN: Rx endpoint NAK */ +#define USB0_ENDPTNAK_EPRN_SHIFT (0) +#define USB0_ENDPTNAK_EPRN_MASK (0x3f << USB0_ENDPTNAK_EPRN_SHIFT) +#define USB0_ENDPTNAK_EPRN(x) ((x) << USB0_ENDPTNAK_EPRN_SHIFT) + +/* EPTN: Tx endpoint NAK */ +#define USB0_ENDPTNAK_EPTN_SHIFT (16) +#define USB0_ENDPTNAK_EPTN_MASK (0x3f << USB0_ENDPTNAK_EPTN_SHIFT) +#define USB0_ENDPTNAK_EPTN(x) ((x) << USB0_ENDPTNAK_EPTN_SHIFT) + +/* --- USB0_ENDPTNAKEN values ----------------------------------- */ + +/* EPRNE: Rx endpoint NAK enable */ +#define USB0_ENDPTNAKEN_EPRNE_SHIFT (0) +#define USB0_ENDPTNAKEN_EPRNE_MASK (0x3f << USB0_ENDPTNAKEN_EPRNE_SHIFT) +#define USB0_ENDPTNAKEN_EPRNE(x) ((x) << USB0_ENDPTNAKEN_EPRNE_SHIFT) + +/* EPTNE: Tx endpoint NAK */ +#define USB0_ENDPTNAKEN_EPTNE_SHIFT (16) +#define USB0_ENDPTNAKEN_EPTNE_MASK (0x3f << USB0_ENDPTNAKEN_EPTNE_SHIFT) +#define USB0_ENDPTNAKEN_EPTNE(x) ((x) << USB0_ENDPTNAKEN_EPTNE_SHIFT) + +/* --- USB0_PORTSC1_D values ------------------------------------ */ + +/* CCS: Current connect status */ +#define USB0_PORTSC1_D_CCS_SHIFT (0) +#define USB0_PORTSC1_D_CCS (1 << USB0_PORTSC1_D_CCS_SHIFT) + +/* PE: Port enable */ +#define USB0_PORTSC1_D_PE_SHIFT (2) +#define USB0_PORTSC1_D_PE (1 << USB0_PORTSC1_D_PE_SHIFT) + +/* PEC: Port enable/disable change */ +#define USB0_PORTSC1_D_PEC_SHIFT (3) +#define USB0_PORTSC1_D_PEC (1 << USB0_PORTSC1_D_PEC_SHIFT) + +/* FPR: Force port resume */ +#define USB0_PORTSC1_D_FPR_SHIFT (6) +#define USB0_PORTSC1_D_FPR (1 << USB0_PORTSC1_D_FPR_SHIFT) + +/* SUSP: Suspend */ +#define USB0_PORTSC1_D_SUSP_SHIFT (7) +#define USB0_PORTSC1_D_SUSP (1 << USB0_PORTSC1_D_SUSP_SHIFT) + +/* PR: Port reset */ +#define USB0_PORTSC1_D_PR_SHIFT (8) +#define USB0_PORTSC1_D_PR (1 << USB0_PORTSC1_D_PR_SHIFT) + +/* HSP: High-speed status */ +#define USB0_PORTSC1_D_HSP_SHIFT (9) +#define USB0_PORTSC1_D_HSP (1 << USB0_PORTSC1_D_HSP_SHIFT) + +/* PIC1_0: Port indicator control */ +#define USB0_PORTSC1_D_PIC1_0_SHIFT (14) +#define USB0_PORTSC1_D_PIC1_0_MASK (0x3 << USB0_PORTSC1_D_PIC1_0_SHIFT) +#define USB0_PORTSC1_D_PIC1_0(x) ((x) << USB0_PORTSC1_D_PIC1_0_SHIFT) + +/* PTC3_0: Port test control */ +#define USB0_PORTSC1_D_PTC3_0_SHIFT (16) +#define USB0_PORTSC1_D_PTC3_0_MASK (0xf << USB0_PORTSC1_D_PTC3_0_SHIFT) +#define USB0_PORTSC1_D_PTC3_0(x) ((x) << USB0_PORTSC1_D_PTC3_0_SHIFT) + +/* PHCD: PHY low power suspend - clock disable (PLPSCD) */ +#define USB0_PORTSC1_D_PHCD_SHIFT (23) +#define USB0_PORTSC1_D_PHCD (1 << USB0_PORTSC1_D_PHCD_SHIFT) + +/* PFSC: Port force full speed connect */ +#define USB0_PORTSC1_D_PFSC_SHIFT (24) +#define USB0_PORTSC1_D_PFSC (1 << USB0_PORTSC1_D_PFSC_SHIFT) + +/* PSPD: Port speed */ +#define USB0_PORTSC1_D_PSPD_SHIFT (26) +#define USB0_PORTSC1_D_PSPD_MASK (0x3 << USB0_PORTSC1_D_PSPD_SHIFT) +#define USB0_PORTSC1_D_PSPD(x) ((x) << USB0_PORTSC1_D_PSPD_SHIFT) + +/* --- USB0_PORTSC1_H values ------------------------------------ */ + +/* CCS: Current connect status */ +#define USB0_PORTSC1_H_CCS_SHIFT (0) +#define USB0_PORTSC1_H_CCS (1 << USB0_PORTSC1_H_CCS_SHIFT) + +/* CSC: Connect status change */ +#define USB0_PORTSC1_H_CSC_SHIFT (1) +#define USB0_PORTSC1_H_CSC (1 << USB0_PORTSC1_H_CSC_SHIFT) + +/* PE: Port enable */ +#define USB0_PORTSC1_H_PE_SHIFT (2) +#define USB0_PORTSC1_H_PE (1 << USB0_PORTSC1_H_PE_SHIFT) + +/* PEC: Port disable/enable change */ +#define USB0_PORTSC1_H_PEC_SHIFT (3) +#define USB0_PORTSC1_H_PEC (1 << USB0_PORTSC1_H_PEC_SHIFT) + +/* OCA: Over-current active */ +#define USB0_PORTSC1_H_OCA_SHIFT (4) +#define USB0_PORTSC1_H_OCA (1 << USB0_PORTSC1_H_OCA_SHIFT) + +/* OCC: Over-current change */ +#define USB0_PORTSC1_H_OCC_SHIFT (5) +#define USB0_PORTSC1_H_OCC (1 << USB0_PORTSC1_H_OCC_SHIFT) + +/* FPR: Force port resume */ +#define USB0_PORTSC1_H_FPR_SHIFT (6) +#define USB0_PORTSC1_H_FPR (1 << USB0_PORTSC1_H_FPR_SHIFT) + +/* SUSP: Suspend */ +#define USB0_PORTSC1_H_SUSP_SHIFT (7) +#define USB0_PORTSC1_H_SUSP (1 << USB0_PORTSC1_H_SUSP_SHIFT) + +/* PR: Port reset */ +#define USB0_PORTSC1_H_PR_SHIFT (8) +#define USB0_PORTSC1_H_PR (1 << USB0_PORTSC1_H_PR_SHIFT) + +/* HSP: High-speed status */ +#define USB0_PORTSC1_H_HSP_SHIFT (9) +#define USB0_PORTSC1_H_HSP (1 << USB0_PORTSC1_H_HSP_SHIFT) + +/* LS: Line status */ +#define USB0_PORTSC1_H_LS_SHIFT (10) +#define USB0_PORTSC1_H_LS_MASK (0x3 << USB0_PORTSC1_H_LS_SHIFT) +#define USB0_PORTSC1_H_LS(x) ((x) << USB0_PORTSC1_H_LS_SHIFT) + +/* PP: Port power control */ +#define USB0_PORTSC1_H_PP_SHIFT (12) +#define USB0_PORTSC1_H_PP (1 << USB0_PORTSC1_H_PP_SHIFT) + +/* PIC1_0: Port indicator control */ +#define USB0_PORTSC1_H_PIC1_0_SHIFT (14) +#define USB0_PORTSC1_H_PIC1_0_MASK (0x3 << USB0_PORTSC1_H_PIC1_0_SHIFT) +#define USB0_PORTSC1_H_PIC1_0(x) ((x) << USB0_PORTSC1_H_PIC1_0_SHIFT) + +/* PTC3_0: Port test control */ +#define USB0_PORTSC1_H_PTC3_0_SHIFT (16) +#define USB0_PORTSC1_H_PTC3_0_MASK (0xf << USB0_PORTSC1_H_PTC3_0_SHIFT) +#define USB0_PORTSC1_H_PTC3_0(x) ((x) << USB0_PORTSC1_H_PTC3_0_SHIFT) + +/* WKCN: Wake on connect enable (WKCNNT_E) */ +#define USB0_PORTSC1_H_WKCN_SHIFT (20) +#define USB0_PORTSC1_H_WKCN (1 << USB0_PORTSC1_H_WKCN_SHIFT) + +/* WKDC: Wake on disconnect enable (WKDSCNNT_E) */ +#define USB0_PORTSC1_H_WKDC_SHIFT (21) +#define USB0_PORTSC1_H_WKDC (1 << USB0_PORTSC1_H_WKDC_SHIFT) + +/* WKOC: Wake on over-current enable (WKOC_E) */ +#define USB0_PORTSC1_H_WKOC_SHIFT (22) +#define USB0_PORTSC1_H_WKOC (1 << USB0_PORTSC1_H_WKOC_SHIFT) + +/* PHCD: PHY low power suspend - clock disable (PLPSCD) */ +#define USB0_PORTSC1_H_PHCD_SHIFT (23) +#define USB0_PORTSC1_H_PHCD (1 << USB0_PORTSC1_H_PHCD_SHIFT) + +/* PFSC: Port force full speed connect */ +#define USB0_PORTSC1_H_PFSC_SHIFT (24) +#define USB0_PORTSC1_H_PFSC (1 << USB0_PORTSC1_H_PFSC_SHIFT) + +/* PSPD: Port speed */ +#define USB0_PORTSC1_H_PSPD_SHIFT (26) +#define USB0_PORTSC1_H_PSPD_MASK (0x3 << USB0_PORTSC1_H_PSPD_SHIFT) +#define USB0_PORTSC1_H_PSPD(x) ((x) << USB0_PORTSC1_H_PSPD_SHIFT) + +/* --- USB0_OTGSC values ---------------------------------------- */ + +/* VD: VBUS_Discharge */ +#define USB0_OTGSC_VD_SHIFT (0) +#define USB0_OTGSC_VD (1 << USB0_OTGSC_VD_SHIFT) + +/* VC: VBUS_Charge */ +#define USB0_OTGSC_VC_SHIFT (1) +#define USB0_OTGSC_VC (1 << USB0_OTGSC_VC_SHIFT) + +/* HAAR: Hardware assist auto_reset */ +#define USB0_OTGSC_HAAR_SHIFT (2) +#define USB0_OTGSC_HAAR (1 << USB0_OTGSC_HAAR_SHIFT) + +/* OT: OTG termination */ +#define USB0_OTGSC_OT_SHIFT (3) +#define USB0_OTGSC_OT (1 << USB0_OTGSC_OT_SHIFT) + +/* DP: Data pulsing */ +#define USB0_OTGSC_DP_SHIFT (4) +#define USB0_OTGSC_DP (1 << USB0_OTGSC_DP_SHIFT) + +/* IDPU: ID pull-up */ +#define USB0_OTGSC_IDPU_SHIFT (5) +#define USB0_OTGSC_IDPU (1 << USB0_OTGSC_IDPU_SHIFT) + +/* HADP: Hardware assist data pulse */ +#define USB0_OTGSC_HADP_SHIFT (6) +#define USB0_OTGSC_HADP (1 << USB0_OTGSC_HADP_SHIFT) + +/* HABA: Hardware assist B-disconnect to A-connect */ +#define USB0_OTGSC_HABA_SHIFT (7) +#define USB0_OTGSC_HABA (1 << USB0_OTGSC_HABA_SHIFT) + +/* ID: USB ID */ +#define USB0_OTGSC_ID_SHIFT (8) +#define USB0_OTGSC_ID (1 << USB0_OTGSC_ID_SHIFT) + +/* AVV: A-VBUS valid */ +#define USB0_OTGSC_AVV_SHIFT (9) +#define USB0_OTGSC_AVV (1 << USB0_OTGSC_AVV_SHIFT) + +/* ASV: A-session valid */ +#define USB0_OTGSC_ASV_SHIFT (10) +#define USB0_OTGSC_ASV (1 << USB0_OTGSC_ASV_SHIFT) + +/* BSV: B-session valid */ +#define USB0_OTGSC_BSV_SHIFT (11) +#define USB0_OTGSC_BSV (1 << USB0_OTGSC_BSV_SHIFT) + +/* BSE: B-session end */ +#define USB0_OTGSC_BSE_SHIFT (12) +#define USB0_OTGSC_BSE (1 << USB0_OTGSC_BSE_SHIFT) + +/* MS1T: 1 millisecond timer toggle */ +#define USB0_OTGSC_MS1T_SHIFT (13) +#define USB0_OTGSC_MS1T (1 << USB0_OTGSC_MS1T_SHIFT) + +/* DPS: Data bus pulsing status */ +#define USB0_OTGSC_DPS_SHIFT (14) +#define USB0_OTGSC_DPS (1 << USB0_OTGSC_DPS_SHIFT) + +/* IDIS: USB ID interrupt status */ +#define USB0_OTGSC_IDIS_SHIFT (16) +#define USB0_OTGSC_IDIS (1 << USB0_OTGSC_IDIS_SHIFT) + +/* AVVIS: A-VBUS valid interrupt status */ +#define USB0_OTGSC_AVVIS_SHIFT (17) +#define USB0_OTGSC_AVVIS (1 << USB0_OTGSC_AVVIS_SHIFT) + +/* ASVIS: A-Session valid interrupt status */ +#define USB0_OTGSC_ASVIS_SHIFT (18) +#define USB0_OTGSC_ASVIS (1 << USB0_OTGSC_ASVIS_SHIFT) + +/* BSVIS: B-Session valid interrupt status */ +#define USB0_OTGSC_BSVIS_SHIFT (19) +#define USB0_OTGSC_BSVIS (1 << USB0_OTGSC_BSVIS_SHIFT) + +/* BSEIS: B-Session end interrupt status */ +#define USB0_OTGSC_BSEIS_SHIFT (20) +#define USB0_OTGSC_BSEIS (1 << USB0_OTGSC_BSEIS_SHIFT) + +/* MS1S: 1 millisecond timer interrupt status */ +#define USB0_OTGSC_MS1S_SHIFT (21) +#define USB0_OTGSC_MS1S (1 << USB0_OTGSC_MS1S_SHIFT) + +/* DPIS: Data pulse interrupt status */ +#define USB0_OTGSC_DPIS_SHIFT (22) +#define USB0_OTGSC_DPIS (1 << USB0_OTGSC_DPIS_SHIFT) + +/* IDIE: USB ID interrupt enable */ +#define USB0_OTGSC_IDIE_SHIFT (24) +#define USB0_OTGSC_IDIE (1 << USB0_OTGSC_IDIE_SHIFT) + +/* AVVIE: A-VBUS valid interrupt enable */ +#define USB0_OTGSC_AVVIE_SHIFT (25) +#define USB0_OTGSC_AVVIE (1 << USB0_OTGSC_AVVIE_SHIFT) + +/* ASVIE: A-session valid interrupt enable */ +#define USB0_OTGSC_ASVIE_SHIFT (26) +#define USB0_OTGSC_ASVIE (1 << USB0_OTGSC_ASVIE_SHIFT) + +/* BSVIE: B-session valid interrupt enable */ +#define USB0_OTGSC_BSVIE_SHIFT (27) +#define USB0_OTGSC_BSVIE (1 << USB0_OTGSC_BSVIE_SHIFT) + +/* BSEIE: B-session end interrupt enable */ +#define USB0_OTGSC_BSEIE_SHIFT (28) +#define USB0_OTGSC_BSEIE (1 << USB0_OTGSC_BSEIE_SHIFT) + +/* MS1E: 1 millisecond timer interrupt enable */ +#define USB0_OTGSC_MS1E_SHIFT (29) +#define USB0_OTGSC_MS1E (1 << USB0_OTGSC_MS1E_SHIFT) + +/* DPIE: Data pulse interrupt enable */ +#define USB0_OTGSC_DPIE_SHIFT (30) +#define USB0_OTGSC_DPIE (1 << USB0_OTGSC_DPIE_SHIFT) + +/* --- USB0_USBMODE_D values ------------------------------------ */ + +/* CM1_0: Controller mode */ +#define USB0_USBMODE_D_CM1_0_SHIFT (0) +#define USB0_USBMODE_D_CM1_0_MASK (0x3 << USB0_USBMODE_D_CM1_0_SHIFT) +#define USB0_USBMODE_D_CM1_0(x) ((x) << USB0_USBMODE_D_CM1_0_SHIFT) + +/* ES: Endian select */ +#define USB0_USBMODE_D_ES_SHIFT (2) +#define USB0_USBMODE_D_ES (1 << USB0_USBMODE_D_ES_SHIFT) + +/* SLOM: Setup Lockout mode */ +#define USB0_USBMODE_D_SLOM_SHIFT (3) +#define USB0_USBMODE_D_SLOM (1 << USB0_USBMODE_D_SLOM_SHIFT) + +/* SDIS: Setup Lockout mode */ +#define USB0_USBMODE_D_SDIS_SHIFT (4) +#define USB0_USBMODE_D_SDIS (1 << USB0_USBMODE_D_SDIS_SHIFT) + +/* --- USB0_USBMODE_H values ------------------------------------ */ + +/* CM: Controller mode */ +#define USB0_USBMODE_H_CM_SHIFT (0) +#define USB0_USBMODE_H_CM_MASK (0x3 << USB0_USBMODE_H_CM_SHIFT) +#define USB0_USBMODE_H_CM(x) ((x) << USB0_USBMODE_H_CM_SHIFT) + +/* ES: Endian select */ +#define USB0_USBMODE_H_ES_SHIFT (2) +#define USB0_USBMODE_H_ES (1 << USB0_USBMODE_H_ES_SHIFT) + +/* SDIS: Stream disable mode */ +#define USB0_USBMODE_H_SDIS_SHIFT (4) +#define USB0_USBMODE_H_SDIS (1 << USB0_USBMODE_H_SDIS_SHIFT) + +/* VBPS: VBUS power select */ +#define USB0_USBMODE_H_VBPS_SHIFT (5) +#define USB0_USBMODE_H_VBPS (1 << USB0_USBMODE_H_VBPS_SHIFT) + +/* --- USB0_ENDPTSETUPSTAT values ------------------------------- */ + +/* ENDPSETUPSTAT: Setup endpoint status for logical endpoints 0 to 5 */ +#define USB0_ENDPTSETUPSTAT_ENDPTSETUPSTAT_SHIFT (0) +#define USB0_ENDPTSETUPSTAT_ENDPTSETUPSTAT_MASK \ + (0x3f << USB0_ENDPTSETUPSTAT_ENDPTSETUPSTAT_SHIFT) +#define USB0_ENDPTSETUPSTAT_ENDPTSETUPSTAT(x) \ + ((x) << USB0_ENDPTSETUPSTAT_ENDPTSETUPSTAT_SHIFT) + +/* --- USB0_ENDPTPRIME values ----------------------------------- */ + +/* PERB: Prime endpoint receive buffer for physical OUT endpoints 5 to 0 */ +#define USB0_ENDPTPRIME_PERB_SHIFT (0) +#define USB0_ENDPTPRIME_PERB_MASK (0x3f << USB0_ENDPTPRIME_PERB_SHIFT) +#define USB0_ENDPTPRIME_PERB(x) ((x) << USB0_ENDPTPRIME_PERB_SHIFT) + +/* PETB: Prime endpoint transmit buffer for physical IN endpoints 5 to 0 */ +#define USB0_ENDPTPRIME_PETB_SHIFT (16) +#define USB0_ENDPTPRIME_PETB_MASK (0x3f << USB0_ENDPTPRIME_PETB_SHIFT) +#define USB0_ENDPTPRIME_PETB(x) ((x) << USB0_ENDPTPRIME_PETB_SHIFT) + +/* --- USB0_ENDPTFLUSH values ----------------------------------- */ + +/* FERB: Flush endpoint receive buffer for physical OUT endpoints 5 to 0 */ +#define USB0_ENDPTFLUSH_FERB_SHIFT (0) +#define USB0_ENDPTFLUSH_FERB_MASK (0x3f << USB0_ENDPTFLUSH_FERB_SHIFT) +#define USB0_ENDPTFLUSH_FERB(x) ((x) << USB0_ENDPTFLUSH_FERB_SHIFT) + +/* FETB: Flush endpoint transmit buffer for physical IN endpoints 5 to 0 */ +#define USB0_ENDPTFLUSH_FETB_SHIFT (16) +#define USB0_ENDPTFLUSH_FETB_MASK (0x3f << USB0_ENDPTFLUSH_FETB_SHIFT) +#define USB0_ENDPTFLUSH_FETB(x) ((x) << USB0_ENDPTFLUSH_FETB_SHIFT) + +/* --- USB0_ENDPTSTAT values ------------------------------------ */ + +/* ERBR: Endpoint receive buffer ready for physical OUT endpoints 5 to 0 */ +#define USB0_ENDPTSTAT_ERBR_SHIFT (0) +#define USB0_ENDPTSTAT_ERBR_MASK (0x3f << USB0_ENDPTSTAT_ERBR_SHIFT) +#define USB0_ENDPTSTAT_ERBR(x) ((x) << USB0_ENDPTSTAT_ERBR_SHIFT) + +/* ETBR: Endpoint transmit buffer ready for physical IN endpoints 3 to 0 */ +#define USB0_ENDPTSTAT_ETBR_SHIFT (16) +#define USB0_ENDPTSTAT_ETBR_MASK (0x3f << USB0_ENDPTSTAT_ETBR_SHIFT) +#define USB0_ENDPTSTAT_ETBR(x) ((x) << USB0_ENDPTSTAT_ETBR_SHIFT) + +/* --- USB0_ENDPTCOMPLETE values -------------------------------- */ + +/* ERCE: Endpoint receive complete event for physical OUT endpoints 5 to 0 */ +#define USB0_ENDPTCOMPLETE_ERCE_SHIFT (0) +#define USB0_ENDPTCOMPLETE_ERCE_MASK (0x3f << USB0_ENDPTCOMPLETE_ERCE_SHIFT) +#define USB0_ENDPTCOMPLETE_ERCE(x) ((x) << USB0_ENDPTCOMPLETE_ERCE_SHIFT) + +/* ETCE: Endpoint transmit complete event for physical IN endpoints 5 to 0 */ +#define USB0_ENDPTCOMPLETE_ETCE_SHIFT (16) +#define USB0_ENDPTCOMPLETE_ETCE_MASK (0x3f << USB0_ENDPTCOMPLETE_ETCE_SHIFT) +#define USB0_ENDPTCOMPLETE_ETCE(x) ((x) << USB0_ENDPTCOMPLETE_ETCE_SHIFT) + +/* --- USB0_ENDPTCTRL0 values ----------------------------------- */ + +/* RXS: Rx endpoint stall */ +#define USB0_ENDPTCTRL0_RXS_SHIFT (0) +#define USB0_ENDPTCTRL0_RXS (1 << USB0_ENDPTCTRL0_RXS_SHIFT) + +/* RXT1_0: Endpoint type */ +#define USB0_ENDPTCTRL0_RXT1_0_SHIFT (2) +#define USB0_ENDPTCTRL0_RXT1_0_MASK (0x3 << USB0_ENDPTCTRL0_RXT1_0_SHIFT) +#define USB0_ENDPTCTRL0_RXT1_0(x) ((x) << USB0_ENDPTCTRL0_RXT1_0_SHIFT) + +/* RXE: Rx endpoint enable */ +#define USB0_ENDPTCTRL0_RXE_SHIFT (7) +#define USB0_ENDPTCTRL0_RXE (1 << USB0_ENDPTCTRL0_RXE_SHIFT) + +/* TXS: Tx endpoint stall */ +#define USB0_ENDPTCTRL0_TXS_SHIFT (16) +#define USB0_ENDPTCTRL0_TXS (1 << USB0_ENDPTCTRL0_TXS_SHIFT) + +/* TXT1_0: Endpoint type */ +#define USB0_ENDPTCTRL0_TXT1_0_SHIFT (18) +#define USB0_ENDPTCTRL0_TXT1_0_MASK (0x3 << USB0_ENDPTCTRL0_TXT1_0_SHIFT) +#define USB0_ENDPTCTRL0_TXT1_0(x) ((x) << USB0_ENDPTCTRL0_TXT1_0_SHIFT) + +/* TXE: Tx endpoint enable */ +#define USB0_ENDPTCTRL0_TXE_SHIFT (23) +#define USB0_ENDPTCTRL0_TXE (1 << USB0_ENDPTCTRL0_TXE_SHIFT) + +/* --- USB0_ENDPTCTRL1 values ----------------------------------- */ + +/* RXS: Rx endpoint stall */ +#define USB0_ENDPTCTRL1_RXS_SHIFT (0) +#define USB0_ENDPTCTRL1_RXS (1 << USB0_ENDPTCTRL1_RXS_SHIFT) + +/* RXT: Endpoint type */ +#define USB0_ENDPTCTRL1_RXT_SHIFT (2) +#define USB0_ENDPTCTRL1_RXT_MASK (0x3 << USB0_ENDPTCTRL1_RXT_SHIFT) +#define USB0_ENDPTCTRL1_RXT(x) ((x) << USB0_ENDPTCTRL1_RXT_SHIFT) + +/* RXI: Rx data toggle inhibit */ +#define USB0_ENDPTCTRL1_RXI_SHIFT (5) +#define USB0_ENDPTCTRL1_RXI (1 << USB0_ENDPTCTRL1_RXI_SHIFT) + +/* RXR: Rx data toggle reset */ +#define USB0_ENDPTCTRL1_RXR_SHIFT (6) +#define USB0_ENDPTCTRL1_RXR (1 << USB0_ENDPTCTRL1_RXR_SHIFT) + +/* RXE: Rx endpoint enable */ +#define USB0_ENDPTCTRL1_RXE_SHIFT (7) +#define USB0_ENDPTCTRL1_RXE (1 << USB0_ENDPTCTRL1_RXE_SHIFT) + +/* TXS: Tx endpoint stall */ +#define USB0_ENDPTCTRL1_TXS_SHIFT (16) +#define USB0_ENDPTCTRL1_TXS (1 << USB0_ENDPTCTRL1_TXS_SHIFT) + +/* TXT1_0: Tx Endpoint type */ +#define USB0_ENDPTCTRL1_TXT1_0_SHIFT (18) +#define USB0_ENDPTCTRL1_TXT1_0_MASK (0x3 << USB0_ENDPTCTRL1_TXT1_0_SHIFT) +#define USB0_ENDPTCTRL1_TXT1_0(x) ((x) << USB0_ENDPTCTRL1_TXT1_0_SHIFT) + +/* TXI: Tx data toggle inhibit */ +#define USB0_ENDPTCTRL1_TXI_SHIFT (21) +#define USB0_ENDPTCTRL1_TXI (1 << USB0_ENDPTCTRL1_TXI_SHIFT) + +/* TXR: Tx data toggle reset */ +#define USB0_ENDPTCTRL1_TXR_SHIFT (22) +#define USB0_ENDPTCTRL1_TXR (1 << USB0_ENDPTCTRL1_TXR_SHIFT) + +/* TXE: Tx endpoint enable */ +#define USB0_ENDPTCTRL1_TXE_SHIFT (23) +#define USB0_ENDPTCTRL1_TXE (1 << USB0_ENDPTCTRL1_TXE_SHIFT) + +/* --- USB0_ENDPTCTRL2 values ----------------------------------- */ + +/* RXS: Rx endpoint stall */ +#define USB0_ENDPTCTRL2_RXS_SHIFT (0) +#define USB0_ENDPTCTRL2_RXS (1 << USB0_ENDPTCTRL2_RXS_SHIFT) + +/* RXT: Endpoint type */ +#define USB0_ENDPTCTRL2_RXT_SHIFT (2) +#define USB0_ENDPTCTRL2_RXT_MASK (0x3 << USB0_ENDPTCTRL2_RXT_SHIFT) +#define USB0_ENDPTCTRL2_RXT(x) ((x) << USB0_ENDPTCTRL2_RXT_SHIFT) + +/* RXI: Rx data toggle inhibit */ +#define USB0_ENDPTCTRL2_RXI_SHIFT (5) +#define USB0_ENDPTCTRL2_RXI (1 << USB0_ENDPTCTRL2_RXI_SHIFT) + +/* RXR: Rx data toggle reset */ +#define USB0_ENDPTCTRL2_RXR_SHIFT (6) +#define USB0_ENDPTCTRL2_RXR (1 << USB0_ENDPTCTRL2_RXR_SHIFT) + +/* RXE: Rx endpoint enable */ +#define USB0_ENDPTCTRL2_RXE_SHIFT (7) +#define USB0_ENDPTCTRL2_RXE (1 << USB0_ENDPTCTRL2_RXE_SHIFT) + +/* TXS: Tx endpoint stall */ +#define USB0_ENDPTCTRL2_TXS_SHIFT (16) +#define USB0_ENDPTCTRL2_TXS (1 << USB0_ENDPTCTRL2_TXS_SHIFT) + +/* TXT1_0: Tx Endpoint type */ +#define USB0_ENDPTCTRL2_TXT1_0_SHIFT (18) +#define USB0_ENDPTCTRL2_TXT1_0_MASK (0x3 << USB0_ENDPTCTRL2_TXT1_0_SHIFT) +#define USB0_ENDPTCTRL2_TXT1_0(x) ((x) << USB0_ENDPTCTRL2_TXT1_0_SHIFT) + +/* TXI: Tx data toggle inhibit */ +#define USB0_ENDPTCTRL2_TXI_SHIFT (21) +#define USB0_ENDPTCTRL2_TXI (1 << USB0_ENDPTCTRL2_TXI_SHIFT) + +/* TXR: Tx data toggle reset */ +#define USB0_ENDPTCTRL2_TXR_SHIFT (22) +#define USB0_ENDPTCTRL2_TXR (1 << USB0_ENDPTCTRL2_TXR_SHIFT) + +/* TXE: Tx endpoint enable */ +#define USB0_ENDPTCTRL2_TXE_SHIFT (23) +#define USB0_ENDPTCTRL2_TXE (1 << USB0_ENDPTCTRL2_TXE_SHIFT) + +/* --- USB0_ENDPTCTRL3 values ----------------------------------- */ + +/* RXS: Rx endpoint stall */ +#define USB0_ENDPTCTRL3_RXS_SHIFT (0) +#define USB0_ENDPTCTRL3_RXS (1 << USB0_ENDPTCTRL3_RXS_SHIFT) + +/* RXT: Endpoint type */ +#define USB0_ENDPTCTRL3_RXT_SHIFT (2) +#define USB0_ENDPTCTRL3_RXT_MASK (0x3 << USB0_ENDPTCTRL3_RXT_SHIFT) +#define USB0_ENDPTCTRL3_RXT(x) ((x) << USB0_ENDPTCTRL3_RXT_SHIFT) + +/* RXI: Rx data toggle inhibit */ +#define USB0_ENDPTCTRL3_RXI_SHIFT (5) +#define USB0_ENDPTCTRL3_RXI (1 << USB0_ENDPTCTRL3_RXI_SHIFT) + +/* RXR: Rx data toggle reset */ +#define USB0_ENDPTCTRL3_RXR_SHIFT (6) +#define USB0_ENDPTCTRL3_RXR (1 << USB0_ENDPTCTRL3_RXR_SHIFT) + +/* RXE: Rx endpoint enable */ +#define USB0_ENDPTCTRL3_RXE_SHIFT (7) +#define USB0_ENDPTCTRL3_RXE (1 << USB0_ENDPTCTRL3_RXE_SHIFT) + +/* TXS: Tx endpoint stall */ +#define USB0_ENDPTCTRL3_TXS_SHIFT (16) +#define USB0_ENDPTCTRL3_TXS (1 << USB0_ENDPTCTRL3_TXS_SHIFT) + +/* TXT1_0: Tx Endpoint type */ +#define USB0_ENDPTCTRL3_TXT1_0_SHIFT (18) +#define USB0_ENDPTCTRL3_TXT1_0_MASK (0x3 << USB0_ENDPTCTRL3_TXT1_0_SHIFT) +#define USB0_ENDPTCTRL3_TXT1_0(x) ((x) << USB0_ENDPTCTRL3_TXT1_0_SHIFT) + +/* TXI: Tx data toggle inhibit */ +#define USB0_ENDPTCTRL3_TXI_SHIFT (21) +#define USB0_ENDPTCTRL3_TXI (1 << USB0_ENDPTCTRL3_TXI_SHIFT) + +/* TXR: Tx data toggle reset */ +#define USB0_ENDPTCTRL3_TXR_SHIFT (22) +#define USB0_ENDPTCTRL3_TXR (1 << USB0_ENDPTCTRL3_TXR_SHIFT) + +/* TXE: Tx endpoint enable */ +#define USB0_ENDPTCTRL3_TXE_SHIFT (23) +#define USB0_ENDPTCTRL3_TXE (1 << USB0_ENDPTCTRL3_TXE_SHIFT) + +/* --- USB0_ENDPTCTRL4 values ----------------------------------- */ + +/* RXS: Rx endpoint stall */ +#define USB0_ENDPTCTRL4_RXS_SHIFT (0) +#define USB0_ENDPTCTRL4_RXS (1 << USB0_ENDPTCTRL4_RXS_SHIFT) + +/* RXT: Endpoint type */ +#define USB0_ENDPTCTRL4_RXT_SHIFT (2) +#define USB0_ENDPTCTRL4_RXT_MASK (0x3 << USB0_ENDPTCTRL4_RXT_SHIFT) +#define USB0_ENDPTCTRL4_RXT(x) ((x) << USB0_ENDPTCTRL4_RXT_SHIFT) + +/* RXI: Rx data toggle inhibit */ +#define USB0_ENDPTCTRL4_RXI_SHIFT (5) +#define USB0_ENDPTCTRL4_RXI (1 << USB0_ENDPTCTRL4_RXI_SHIFT) + +/* RXR: Rx data toggle reset */ +#define USB0_ENDPTCTRL4_RXR_SHIFT (6) +#define USB0_ENDPTCTRL4_RXR (1 << USB0_ENDPTCTRL4_RXR_SHIFT) + +/* RXE: Rx endpoint enable */ +#define USB0_ENDPTCTRL4_RXE_SHIFT (7) +#define USB0_ENDPTCTRL4_RXE (1 << USB0_ENDPTCTRL4_RXE_SHIFT) + +/* TXS: Tx endpoint stall */ +#define USB0_ENDPTCTRL4_TXS_SHIFT (16) +#define USB0_ENDPTCTRL4_TXS (1 << USB0_ENDPTCTRL4_TXS_SHIFT) + +/* TXT1_0: Tx Endpoint type */ +#define USB0_ENDPTCTRL4_TXT1_0_SHIFT (18) +#define USB0_ENDPTCTRL4_TXT1_0_MASK (0x3 << USB0_ENDPTCTRL4_TXT1_0_SHIFT) +#define USB0_ENDPTCTRL4_TXT1_0(x) ((x) << USB0_ENDPTCTRL4_TXT1_0_SHIFT) + +/* TXI: Tx data toggle inhibit */ +#define USB0_ENDPTCTRL4_TXI_SHIFT (21) +#define USB0_ENDPTCTRL4_TXI (1 << USB0_ENDPTCTRL4_TXI_SHIFT) + +/* TXR: Tx data toggle reset */ +#define USB0_ENDPTCTRL4_TXR_SHIFT (22) +#define USB0_ENDPTCTRL4_TXR (1 << USB0_ENDPTCTRL4_TXR_SHIFT) + +/* TXE: Tx endpoint enable */ +#define USB0_ENDPTCTRL4_TXE_SHIFT (23) +#define USB0_ENDPTCTRL4_TXE (1 << USB0_ENDPTCTRL4_TXE_SHIFT) + +/* --- USB0_ENDPTCTRL5 values ----------------------------------- */ + +/* RXS: Rx endpoint stall */ +#define USB0_ENDPTCTRL5_RXS_SHIFT (0) +#define USB0_ENDPTCTRL5_RXS (1 << USB0_ENDPTCTRL5_RXS_SHIFT) + +/* RXT: Endpoint type */ +#define USB0_ENDPTCTRL5_RXT_SHIFT (2) +#define USB0_ENDPTCTRL5_RXT_MASK (0x3 << USB0_ENDPTCTRL5_RXT_SHIFT) +#define USB0_ENDPTCTRL5_RXT(x) ((x) << USB0_ENDPTCTRL5_RXT_SHIFT) + +/* RXI: Rx data toggle inhibit */ +#define USB0_ENDPTCTRL5_RXI_SHIFT (5) +#define USB0_ENDPTCTRL5_RXI (1 << USB0_ENDPTCTRL5_RXI_SHIFT) + +/* RXR: Rx data toggle reset */ +#define USB0_ENDPTCTRL5_RXR_SHIFT (6) +#define USB0_ENDPTCTRL5_RXR (1 << USB0_ENDPTCTRL5_RXR_SHIFT) + +/* RXE: Rx endpoint enable */ +#define USB0_ENDPTCTRL5_RXE_SHIFT (7) +#define USB0_ENDPTCTRL5_RXE (1 << USB0_ENDPTCTRL5_RXE_SHIFT) + +/* TXS: Tx endpoint stall */ +#define USB0_ENDPTCTRL5_TXS_SHIFT (16) +#define USB0_ENDPTCTRL5_TXS (1 << USB0_ENDPTCTRL5_TXS_SHIFT) + +/* TXT1_0: Tx Endpoint type */ +#define USB0_ENDPTCTRL5_TXT1_0_SHIFT (18) +#define USB0_ENDPTCTRL5_TXT1_0_MASK (0x3 << USB0_ENDPTCTRL5_TXT1_0_SHIFT) +#define USB0_ENDPTCTRL5_TXT1_0(x) ((x) << USB0_ENDPTCTRL5_TXT1_0_SHIFT) + +/* TXI: Tx data toggle inhibit */ +#define USB0_ENDPTCTRL5_TXI_SHIFT (21) +#define USB0_ENDPTCTRL5_TXI (1 << USB0_ENDPTCTRL5_TXI_SHIFT) + +/* TXR: Tx data toggle reset */ +#define USB0_ENDPTCTRL5_TXR_SHIFT (22) +#define USB0_ENDPTCTRL5_TXR (1 << USB0_ENDPTCTRL5_TXR_SHIFT) + +/* TXE: Tx endpoint enable */ +#define USB0_ENDPTCTRL5_TXE_SHIFT (23) +#define USB0_ENDPTCTRL5_TXE (1 << USB0_ENDPTCTRL5_TXE_SHIFT) + +/* -------------------------------------------------------------- */ + + +/* --- USB0_ENDPTCTRL common values ----------------------------- */ + +/* RXS: Rx endpoint stall */ +#define USB0_ENDPTCTRL_RXS_SHIFT (0) +#define USB0_ENDPTCTRL_RXS (1 << USB0_ENDPTCTRL_RXS_SHIFT) + +/* RXT: Endpoint type */ +#define USB0_ENDPTCTRL_RXT_SHIFT (2) +#define USB0_ENDPTCTRL_RXT_MASK (0x3 << USB0_ENDPTCTRL_RXT_SHIFT) +#define USB0_ENDPTCTRL_RXT(x) ((x) << USB0_ENDPTCTRL_RXT_SHIFT) + +/* RXI: Rx data toggle inhibit */ +#define USB0_ENDPTCTRL_RXI_SHIFT (5) +#define USB0_ENDPTCTRL_RXI (1 << USB0_ENDPTCTRL_RXI_SHIFT) + +/* RXR: Rx data toggle reset */ +#define USB0_ENDPTCTRL_RXR_SHIFT (6) +#define USB0_ENDPTCTRL_RXR (1 << USB0_ENDPTCTRL_RXR_SHIFT) + +/* RXE: Rx endpoint enable */ +#define USB0_ENDPTCTRL_RXE_SHIFT (7) +#define USB0_ENDPTCTRL_RXE (1 << USB0_ENDPTCTRL_RXE_SHIFT) + +/* TXS: Tx endpoint stall */ +#define USB0_ENDPTCTRL_TXS_SHIFT (16) +#define USB0_ENDPTCTRL_TXS (1 << USB0_ENDPTCTRL_TXS_SHIFT) + +/* TXT1_0: Tx Endpoint type */ +#define USB0_ENDPTCTRL_TXT1_0_SHIFT (18) +#define USB0_ENDPTCTRL_TXT1_0_MASK (0x3 << USB0_ENDPTCTRL_TXT1_0_SHIFT) +#define USB0_ENDPTCTRL_TXT1_0(x) ((x) << USB0_ENDPTCTRL_TXT1_0_SHIFT) + +/* TXI: Tx data toggle inhibit */ +#define USB0_ENDPTCTRL_TXI_SHIFT (21) +#define USB0_ENDPTCTRL_TXI (1 << USB0_ENDPTCTRL_TXI_SHIFT) + +/* TXR: Tx data toggle reset */ +#define USB0_ENDPTCTRL_TXR_SHIFT (22) +#define USB0_ENDPTCTRL_TXR (1 << USB0_ENDPTCTRL_TXR_SHIFT) + +/* TXE: Tx endpoint enable */ +#define USB0_ENDPTCTRL_TXE_SHIFT (23) +#define USB0_ENDPTCTRL_TXE (1 << USB0_ENDPTCTRL_TXE_SHIFT) + + + + + +/* --- USB1 registers ------------------------------------------------------ */ +/* TODO */ + +#endif diff --git a/libopencm3/include/libopencm3/lpc43xx/wwdt.h b/libopencm3/include/libopencm3/lpc43xx/wwdt.h new file mode 100644 index 0000000..30ff6a7 --- /dev/null +++ b/libopencm3/include/libopencm3/lpc43xx/wwdt.h @@ -0,0 +1,65 @@ +/** @defgroup wwdt_defines Windowed Watchdog Timer + +@brief <b>Defined Constants and Types for the LPC43xx Windowed Watchdog +Timer</b> + +@ingroup LPC43xx_defines + +@version 1.0.0 + +@author @htmlonly © @endhtmlonly 2012 Michael Ossmann <mike@ossmann.com> + +@date 10 March 2013 + +LGPL License Terms @ref lgpl_license + */ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2012 Michael Ossmann <mike@ossmann.com> + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see <http://www.gnu.org/licenses/>. + */ + +#ifndef LPC43XX_WWDT_H +#define LPC43XX_WWDT_H + +/**@{*/ + +#include <libopencm3/cm3/common.h> +#include <libopencm3/lpc43xx/memorymap.h> + +/* --- Windowed Watchdog Timer (WWDT) registers ---------------------------- */ + +/* Watchdog mode register */ +#define WWDT_MOD MMIO32(WWDT_BASE + 0x000) + +/* Watchdog timer constant register */ +#define WWDT_TC MMIO32(WWDT_BASE + 0x004) + +/* Watchdog feed sequence register */ +#define WWDT_FEED MMIO32(WWDT_BASE + 0x008) + +/* Watchdog timer value register */ +#define WWDT_TV MMIO32(WWDT_BASE + 0x00C) + +/* Watchdog warning interrupt register */ +#define WWDT_WARNINT MMIO32(WWDT_BASE + 0x014) + +/* Watchdog timer window register */ +#define WWDT_WINDOW MMIO32(WWDT_BASE + 0x018) + +/**@}*/ + +#endif |