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* Optimizing DFFs whose initial value prevents their value from changingBogdan Vukobratovic2019-05-282-0/+19
* Fix initEddie Hung2019-05-241-27/+27
* Fix typosEddie Hung2019-05-241-6/+6
* Add more testsEddie Hung2019-05-242-20/+41
* Call procEddie Hung2019-05-241-1/+1
* Fix duplicate driverEddie Hung2019-05-241-15/+15
* Add opt_rmdff testsEddie Hung2019-05-232-0/+55
* Added tests for Verilog frontent for attributes on parameters and localparamsMaciej Kurc2019-05-162-0/+22
* Add test case from #997Clifford Wolf2019-05-071-0/+12
* Merge pull request #946 from YosysHQ/clifford/specifyClifford Wolf2019-05-062-0/+86
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| * Improve tests/various/specify.ysClifford Wolf2019-05-061-2/+32
| * More testingEddie Hung2019-05-032-2/+5
| * Fix spacingEddie Hung2019-05-031-6/+6
| * Add quick-and-dirty specify testsEddie Hung2019-05-032-0/+53
* | Merge pull request #975 from YosysHQ/clifford/fix968Clifford Wolf2019-05-061-0/+25
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| * | Merge branch 'master' of github.com:YosysHQ/yosys into clifford/fix968Clifford Wolf2019-05-066-5/+60
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| * | Add additional test cases for for-loopsClifford Wolf2019-05-011-0/+25
* | | Merge pull request #871 from YosysHQ/verific_importClifford Wolf2019-05-061-0/+52
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| * | Add tests/various/chparam.shClifford Wolf2019-05-061-0/+52
* | | iverilog with simcells.v as wellEddie Hung2019-05-031-1/+2
* | | Merge pull request #969 from YosysHQ/clifford/pmgenstuffClifford Wolf2019-05-031-0/+9
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| * | Add peepopt_muldiv, fixes #930Clifford Wolf2019-04-301-0/+9
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* | Merge pull request #976 from YosysHQ/clifford/fix974Clifford Wolf2019-05-031-0/+22
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| * | Add splitcmplxassign test case and silence splitcmplxassign warningClifford Wolf2019-05-011-0/+22
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* | Fix typo in tests/svinterfaces/runone.shClifford Wolf2019-05-031-2/+2
* | fail svinterfaces testcases on yosys error exitJakob Wenzel2019-05-021-2/+2
* | Fix #938 - Crash occurs in case when use write_firrtl commandJim Lawson2019-05-012-0/+23
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* Updaye pmux2shiftx testClifford Wolf2019-04-221-2/+2
* Merge pull request #909 from zachjs/masterClifford Wolf2019-04-222-0/+48
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| * support repeat loops with constant repeat counts outside of constant functionsZachary Snow2019-04-092-0/+48
* | Merge pull request #944 from YosysHQ/clifford/pmux2shiftxClifford Wolf2019-04-222-0/+62
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| * | Improve "pmux2shiftx"Clifford Wolf2019-04-201-1/+1
| * | Improvements in "pmux2shiftx"Clifford Wolf2019-04-201-1/+1
| * | Improvements in pmux2shiftxClifford Wolf2019-04-202-20/+30
| * | Add test for pmux2shiftxClifford Wolf2019-04-202-0/+52
* | | Fix testsClifford Wolf2019-04-212-2/+3
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* | Add tests/aiger/.gitignoreClifford Wolf2019-04-191-0/+2
* | Add retime testEddie Hung2019-04-051-0/+6
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* Liberty file parser now accepts superfluous ;Niels Moseley2019-03-271-1/+1
* Liberty file parser now accepts superfluous ;Niels Moseley2019-03-273-2/+97
* Fix "verific -extnets" for more complex situationsClifford Wolf2019-03-261-0/+22
* Updated the liberty parser to accept [A:B] ranges (AST has not been updated)....Niels Moseley2019-03-246-0/+541
* Merge https://github.com/YosysHQ/yosys into read_aigerEddie Hung2019-03-1911-31/+175
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| * fix local name resolution in prefix constructsZachary Snow2019-03-181-0/+56
| * Fix handling of task output ports in clocked always blocks, fixes #857Clifford Wolf2019-03-071-0/+19
| * Ensure fid() calls make_id() for consistency; tests/simple/dff_init.v failsJim Lawson2019-03-041-0/+1
| * Hotfix for "make test"Clifford Wolf2019-02-281-1/+1
| * Add "write_verilog -siminit"Clifford Wolf2019-02-281-1/+1
| * Fix FIRRTL to Verilog process instance subfield assignment.Jim Lawson2019-02-253-3/+1
| * Merge pull request #812 from ucb-bar/arrayhierarchyfixesClifford Wolf2019-02-242-1/+68
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