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| author | Eddie Hung <eddie@fpgeh.com> | 2019-05-03 14:03:51 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-05-03 14:03:51 -0700 |
| commit | 1e5f072c0556158924387dedbb78b4cc61bfcf7a (patch) | |
| tree | c87f02f0838efab1965bbb7f95a19743cfe539ab /tests | |
| parent | 373b236108b254e3c01daa56a2b5ab75f2f87da2 (diff) | |
| download | yosys-1e5f072c0556158924387dedbb78b4cc61bfcf7a.tar.gz yosys-1e5f072c0556158924387dedbb78b4cc61bfcf7a.tar.bz2 yosys-1e5f072c0556158924387dedbb78b4cc61bfcf7a.zip | |
iverilog with simcells.v as well
Diffstat (limited to 'tests')
| -rwxr-xr-x | tests/tools/autotest.sh | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/tests/tools/autotest.sh b/tests/tools/autotest.sh index bb9c3bfb5..920474a84 100755 --- a/tests/tools/autotest.sh +++ b/tests/tools/autotest.sh @@ -147,7 +147,8 @@ do fi if $genvcd; then sed -i 's,// \$dump,$dump,g' ${bn}_tb.v; fi compile_and_run ${bn}_tb_ref ${bn}_out_ref ${bn}_tb.v ${bn}_ref.v $libs \ - "$toolsdir"/../../techlibs/common/simlib.v + "$toolsdir"/../../techlibs/common/simlib.v \ + "$toolsdir"/../../techlibs/common/simcells.v if $genvcd; then mv testbench.vcd ${bn}_ref.vcd; fi test_count=0 |