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| author | Clifford Wolf <clifford@clifford.at> | 2019-05-06 20:57:15 +0200 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2019-05-06 20:57:15 +0200 |
| commit | 752553d8e91643228714e04d9887d32f5d47870a (patch) | |
| tree | e7e427b9e6558800b6131022c880af8ccc053845 /tests | |
| parent | 1706798f4e595266a8758ae6d0ff9d978299de10 (diff) | |
| parent | 8c6e94d57c430fc516dbcfbde312dbd7c860477b (diff) | |
| download | yosys-752553d8e91643228714e04d9887d32f5d47870a.tar.gz yosys-752553d8e91643228714e04d9887d32f5d47870a.tar.bz2 yosys-752553d8e91643228714e04d9887d32f5d47870a.zip | |
Merge pull request #946 from YosysHQ/clifford/specify
Add specify parser
Diffstat (limited to 'tests')
| -rw-r--r-- | tests/various/specify.v | 30 | ||||
| -rw-r--r-- | tests/various/specify.ys | 56 |
2 files changed, 86 insertions, 0 deletions
diff --git a/tests/various/specify.v b/tests/various/specify.v new file mode 100644 index 000000000..afc421da8 --- /dev/null +++ b/tests/various/specify.v @@ -0,0 +1,30 @@ +module test ( + input EN, CLK, + input [3:0] D, + output reg [3:0] Q +); + always @(posedge CLK) + if (EN) Q <= D; + + specify + if (EN) (CLK *> (Q : D)) = (1, 2:3:4); + $setup(D, posedge CLK &&& EN, 5); + $hold(posedge CLK, D &&& EN, 6); + endspecify +endmodule + +module test2 ( + input A, B, + output Q +); + xor (Q, A, B); + specify + //specparam T_rise = 1; + //specparam T_fall = 2; + `define T_rise 1 + `define T_fall 2 + (A => Q) = (`T_rise,`T_fall); + //(B => Q) = (`T_rise+`T_fall)/2.0; + (B => Q) = 1.5; + endspecify +endmodule diff --git a/tests/various/specify.ys b/tests/various/specify.ys new file mode 100644 index 000000000..a5ca07219 --- /dev/null +++ b/tests/various/specify.ys @@ -0,0 +1,56 @@ +read_verilog -specify specify.v +prep +cd test +select t:$specify2 -assert-count 0 +select t:$specify3 -assert-count 1 +select t:$specrule -assert-count 2 +cd test2 +select t:$specify2 -assert-count 2 +select t:$specify3 -assert-count 0 +select t:$specrule -assert-count 0 +cd +write_verilog specify.out +design -stash gold + +read_verilog -specify specify.out +prep +cd test +select t:$specify2 -assert-count 0 +select t:$specify3 -assert-count 1 +select t:$specrule -assert-count 2 +cd test2 +select t:$specify2 -assert-count 2 +select t:$specify3 -assert-count 0 +select t:$specrule -assert-count 0 +cd +design -stash gate + +design -copy-from gold -as gold test +design -copy-from gate -as gate test +rename -hide +rename -enumerate -pattern A_% t:$specify3 +rename -enumerate -pattern B_% t:$specrule r:TYPE=$setup %i +rename -enumerate -pattern C_% t:$specrule r:TYPE=$hold %i +select n:A_* -assert-count 2 +select n:B_* -assert-count 2 +select n:C_* -assert-count 2 +equiv_make gold gate equiv +hierarchy -top equiv +equiv_struct +equiv_induct -seq 5 +equiv_status -assert +design -reset + +design -copy-from gold -as gold test2 +design -copy-from gate -as gate test2 +rename -hide +rename -enumerate -pattern A_% t:$specify2 r:T_RISE_TYP=1 %i +rename -enumerate -pattern B_% t:$specify2 n:A_* %d +select n:A_* -assert-count 2 +select n:B_* -assert-count 2 +equiv_make gold gate equiv +hierarchy -top equiv +equiv_struct +equiv_induct -seq 5 +equiv_status -assert +design -reset |