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| author | Jim Lawson <ucbjrl@berkeley.edu> | 2019-02-25 16:18:13 -0800 |
|---|---|---|
| committer | Jim Lawson <ucbjrl@berkeley.edu> | 2019-02-25 16:18:13 -0800 |
| commit | 171c425cf9addb61ef3f03596fd26355ed8af76d (patch) | |
| tree | e620f9838187ab70fd65b5d6554c3b9252777fd8 /tests | |
| parent | c258b99040c8414952a3aceae874dc47563540dc (diff) | |
| download | yosys-171c425cf9addb61ef3f03596fd26355ed8af76d.tar.gz yosys-171c425cf9addb61ef3f03596fd26355ed8af76d.tar.bz2 yosys-171c425cf9addb61ef3f03596fd26355ed8af76d.zip | |
Fix FIRRTL to Verilog process instance subfield assignment.
Don't emit subfield assignments: bits(x, y, z) <= ... - but instead, add them to the reverse-wire-map where they'll be treated at the end of the module.
Enable tests which were disabled due to incorrect treatment of subfields.
Assume the `$firrtl2verilog` variable contains any additional switches to control verilog generation (i.e. `--no-dedup -X mverilog`)
Diffstat (limited to 'tests')
| -rw-r--r-- | tests/asicworld/xfirrtl | 1 | ||||
| -rw-r--r-- | tests/simple/xfirrtl | 1 | ||||
| -rwxr-xr-x | tests/tools/autotest.sh | 2 |
3 files changed, 1 insertions, 3 deletions
diff --git a/tests/asicworld/xfirrtl b/tests/asicworld/xfirrtl index c782a2bd6..08bf4ccd8 100644 --- a/tests/asicworld/xfirrtl +++ b/tests/asicworld/xfirrtl @@ -6,7 +6,6 @@ code_hdl_models_d_latch_gates.v combinational loop code_hdl_models_dff_async_reset.v $adff code_hdl_models_tff_async_reset.v $adff code_hdl_models_uart.v $adff -code_specman_switch_fabric.v subfield assignment (bits() <= ...) code_tidbits_asyn_reset.v $adff code_tidbits_reg_seq_example.v $adff code_verilog_tutorial_always_example.v empty module diff --git a/tests/simple/xfirrtl b/tests/simple/xfirrtl index 00e89b389..5bc75347b 100644 --- a/tests/simple/xfirrtl +++ b/tests/simple/xfirrtl @@ -12,7 +12,6 @@ multiplier.v inst id[0] of muxtree.v drops modules omsp_dbg_uart.v $adff operators.v $pow -paramods.v subfield assignment (bits() <= ...) partsel.v drops modules process.v drops modules realexpr.v drops modules diff --git a/tests/tools/autotest.sh b/tests/tools/autotest.sh index 218edf931..99ec3e7cd 100755 --- a/tests/tools/autotest.sh +++ b/tests/tools/autotest.sh @@ -175,7 +175,7 @@ do if [ -n "$firrtl2verilog" ]; then if test -z "$xfirrtl" || ! grep "$fn" "$xfirrtl" ; then "$toolsdir"/../../yosys -b "firrtl" -o ${bn}_ref.fir -f "$frontend $include_opts" -p "prep -nordff; proc; opt; memory; opt; fsm; opt -full -fine; pmuxtree" ${bn}_ref.v - $firrtl2verilog -i ${bn}_ref.fir -o ${bn}_ref.fir.v -X verilog + $firrtl2verilog -i ${bn}_ref.fir -o ${bn}_ref.fir.v test_passes -f "$frontend $include_opts" -p "hierarchy; proc; opt; memory; opt; fsm; opt -full -fine" ${bn}_ref.fir.v fi fi |