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* Merge pull request #1213 from YosysHQ/eddie/wreduce_addClifford Wolf2019-08-072-0/+196
|\ | | | | wreduce/opt_expr: improve width reduction for $add and $sub cells
| * Add signed opt_expr testsEddie Hung2019-08-061-0/+50
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| * Add signed testEddie Hung2019-08-061-0/+26
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| * Move LSB tests from wreduce to opt_exprEddie Hung2019-08-062-99/+101
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| * Merge remote-tracking branch 'origin/master' into eddie/wreduce_addEddie Hung2019-08-064-0/+20
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| * | Add another testEddie Hung2019-07-191-1/+24
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| * | Add one more test with trimming Y_WIDTH of $subEddie Hung2019-07-191-11/+14
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| * | Be more explicitEddie Hung2019-07-191-6/+29
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| * | Add tests for sub tooEddie Hung2019-07-191-1/+48
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| * | Add testEddie Hung2019-07-191-0/+22
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* | | Merge pull request #1240 from ucb-bar/firrtl-properties+pow+xnorClifford Wolf2019-08-071-1/+3
|\ \ \ | |_|/ |/| | Support explicit FIRRTL properties for better accommodation of FIRRTL/Verilog semantic differences.
| * | Support explicit FIRRTL properties for better accommodation of ↵Jim Lawson2019-07-311-1/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | FIRRTL/Verilog semantic differences. Use FIRRTL spec vlaues for definition of FIRRTL widths. Added support for '$pos`, `$pow` and `$xnor` cells. Enable tests/simple/operators.v since all operators tested there are now supported. Disable FIRRTL tests of tests/simple/{defvalue.sv,implicit_ports.v,wandwor.v} since they currently generate FIRRTL compilation errors.
* | | Add test for writing gzip-compressed filesDavid Shah2019-08-062-0/+18
|/ / | | | | | | Signed-off-by: David Shah <dave@ds0.me>
* / Add support for reading gzip'd input filesDavid Shah2019-07-262-0/+2
|/ | | | Signed-off-by: David Shah <dave@ds0.me>
* Forgot to commitEddie Hung2019-07-161-0/+7
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* Add tests for cmp2lut on LUT6Eddie Hung2019-07-162-23/+29
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* Update test with more accurate LUT maskEddie Hung2019-07-121-1/+1
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* Fix tests/various/async FFL testClifford Wolf2019-07-091-1/+1
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Improve tests/various/async, disable failing ffl testClifford Wolf2019-07-092-7/+38
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Add tests/various/async.{sh,v}Clifford Wolf2019-07-092-0/+88
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Improve tests/various/run-test.shClifford Wolf2019-07-091-8/+6
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Add tests/simple_abc9/.gitignoreClifford Wolf2019-07-091-0/+3
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Merge pull request #1156 from YosysHQ/eddie/fix_abc9_unknown_cellEddie Hung2019-07-032-0/+14
|\ | | | | write_xaiger to treat unknown cell connections as keep-s
| * Add testEddie Hung2019-07-022-0/+14
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* | Merge pull request #1147 from YosysHQ/clifford/fix1144Clifford Wolf2019-07-032-1/+12
|\ \ | | | | | | Improve specify dummy parser
| * | Fix tests/various/specify.vClifford Wolf2019-07-032-8/+3
| | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * | Some cleanups in "ignore specify parser"Clifford Wolf2019-07-031-1/+1
| | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * | Comment out invalid syntaxEddie Hung2019-06-301-2/+2
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| * | Add test from #1144, and try reading without '-specify' flagEddie Hung2019-06-282-0/+16
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* | | Merge pull request #1150 from YosysHQ/eddie/script_from_wireEddie Hung2019-07-021-0/+20
|\ \ \ | |_|/ |/| | Add "script -select [selection]" to allow commands to be taken from wires
| * | Update test for Pass::call_on_module()Eddie Hung2019-07-021-1/+1
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| * | Update test tooEddie Hung2019-07-021-2/+2
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| * | Merge branch 'master' into eddie/script_from_wireEddie Hung2019-06-281-1/+1
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| * | | Try command in another moduleEddie Hung2019-06-281-0/+3
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| * | | Add testEddie Hung2019-06-281-0/+17
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* | | | memory_dff: Fix checking of feedback mux input when more than one muxDavid Shah2019-07-022-0/+20
| |/ / |/| | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
* | | autotest.sh to define _AUTOTB when test_autotbEddie Hung2019-06-281-1/+1
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* | Merge pull request #1098 from YosysHQ/xaigEddie Hung2019-06-285-0/+312
|\ \ | | | | | | "abc9" pass for timing-aware techmapping (experimental, FPGA only, no FFs)
| * \ Merge remote-tracking branch 'origin/master' into xaigEddie Hung2019-06-271-0/+18
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| * \ \ Merge remote-tracking branch 'origin/master' into xaigEddie Hung2019-06-272-5/+26
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| * | | | Merge origin/masterEddie Hung2019-06-271-0/+320
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| * | | | Merge remote-tracking branch 'origin/master' into xaigEddie Hung2019-06-255-1/+577
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| * | | | | Add tests/various/abc9.{v,ys} with SCC testEddie Hung2019-06-242-0/+19
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| * | | | | Merge remote-tracking branch 'origin/master' into xaigEddie Hung2019-06-215-1/+298
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| * \ \ \ \ \ Merge remote-tracking branch 'origin/master' into xaigEddie Hung2019-06-206-21/+62
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| * | | | | | | Fix issue with part of PI being 1'bxEddie Hung2019-06-201-0/+5
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| * | | | | | | Revert "Merge remote-tracking branch 'origin/eddie/muxpack' into xc7mux"Eddie Hung2019-06-122-247/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This reverts commit 2223ca91b0cc559bb876e8e97372a8f77da1603e, reversing changes made to eaee250a6e63e58dfef63fa30c4120db78223e24.
| * | | | | | | Add a couple more testsEddie Hung2019-06-121-0/+12
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| * | | | | | | Revert "Merge remote-tracking branch 'origin/eddie/shregmap_improve' into ↵Eddie Hung2019-06-122-53/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | xc7mux" This reverts commit a138381ac3f2c820d187f08531ffd823d6cbcfd5, reversing changes made to b77c5da76919f7f99f171a0a2775896fbc8debc2.
| * | | | | | | Revert "Merge remote-tracking branch 'origin/eddie/muxpack' into xc7mux"Eddie Hung2019-06-122-41/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This reverts commit 2223ca91b0cc559bb876e8e97372a8f77da1603e, reversing changes made to eaee250a6e63e58dfef63fa30c4120db78223e24.
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