aboutsummaryrefslogtreecommitdiffstats
path: root/tests
Commit message (Expand)AuthorAgeFilesLines
* Revert "Wrap SB_LUT+SB_CARRY into $__ICE40_CARRY_WRAPPER"David Shah2019-08-109-34/+29
* Remove dump callEddie Hung2019-08-071-1/+0
* Move tests/various/opt* into tests/opt/Eddie Hung2019-08-075-1/+1
* Remove ice40_unlut call, simply do equiv_opt on synth_ice40Eddie Hung2019-08-071-3/+1
* Add testcase from removed opt_ff.{v,ys}Eddie Hung2019-08-071-0/+32
* Remove tests/opt/opt_ff.{v,ys} as they don't seem to do anything but runEddie Hung2019-08-072-24/+0
* Merge pull request #1213 from YosysHQ/eddie/wreduce_addClifford Wolf2019-08-072-0/+196
|\
| * Add signed opt_expr testsEddie Hung2019-08-061-0/+50
| * Add signed testEddie Hung2019-08-061-0/+26
| * Move LSB tests from wreduce to opt_exprEddie Hung2019-08-062-99/+101
| * Merge remote-tracking branch 'origin/master' into eddie/wreduce_addEddie Hung2019-08-064-0/+20
| |\
| * | Add another testEddie Hung2019-07-191-1/+24
| * | Add one more test with trimming Y_WIDTH of $subEddie Hung2019-07-191-11/+14
| * | Be more explicitEddie Hung2019-07-191-6/+29
| * | Add tests for sub tooEddie Hung2019-07-191-1/+48
| * | Add testEddie Hung2019-07-191-0/+22
* | | Merge pull request #1240 from ucb-bar/firrtl-properties+pow+xnorClifford Wolf2019-08-071-1/+3
|\ \ \ | |_|/ |/| |
| * | Support explicit FIRRTL properties for better accommodation of FIRRTL/Verilog...Jim Lawson2019-07-311-1/+3
* | | Add test for writing gzip-compressed filesDavid Shah2019-08-062-0/+18
|/ /
* / Add support for reading gzip'd input filesDavid Shah2019-07-262-0/+2
|/
* Forgot to commitEddie Hung2019-07-161-0/+7
* Add tests for cmp2lut on LUT6Eddie Hung2019-07-162-23/+29
* Update test with more accurate LUT maskEddie Hung2019-07-121-1/+1
* Fix tests/various/async FFL testClifford Wolf2019-07-091-1/+1
* Improve tests/various/async, disable failing ffl testClifford Wolf2019-07-092-7/+38
* Add tests/various/async.{sh,v}Clifford Wolf2019-07-092-0/+88
* Improve tests/various/run-test.shClifford Wolf2019-07-091-8/+6
* Add tests/simple_abc9/.gitignoreClifford Wolf2019-07-091-0/+3
* Merge pull request #1156 from YosysHQ/eddie/fix_abc9_unknown_cellEddie Hung2019-07-032-0/+14
|\
| * Add testEddie Hung2019-07-022-0/+14
* | Merge pull request #1147 from YosysHQ/clifford/fix1144Clifford Wolf2019-07-032-1/+12
|\ \
| * | Fix tests/various/specify.vClifford Wolf2019-07-032-8/+3
| * | Some cleanups in "ignore specify parser"Clifford Wolf2019-07-031-1/+1
| * | Comment out invalid syntaxEddie Hung2019-06-301-2/+2
| * | Add test from #1144, and try reading without '-specify' flagEddie Hung2019-06-282-0/+16
* | | Merge pull request #1150 from YosysHQ/eddie/script_from_wireEddie Hung2019-07-021-0/+20
|\ \ \ | |_|/ |/| |
| * | Update test for Pass::call_on_module()Eddie Hung2019-07-021-1/+1
| * | Update test tooEddie Hung2019-07-021-2/+2
| * | Merge branch 'master' into eddie/script_from_wireEddie Hung2019-06-281-1/+1
| |\ \
| * | | Try command in another moduleEddie Hung2019-06-281-0/+3
| * | | Add testEddie Hung2019-06-281-0/+17
* | | | memory_dff: Fix checking of feedback mux input when more than one muxDavid Shah2019-07-022-0/+20
| |/ / |/| |
* | | autotest.sh to define _AUTOTB when test_autotbEddie Hung2019-06-281-1/+1
|/ /
* | Merge pull request #1098 from YosysHQ/xaigEddie Hung2019-06-285-0/+312
|\ \
| * \ Merge remote-tracking branch 'origin/master' into xaigEddie Hung2019-06-271-0/+18
| |\ \
| * \ \ Merge remote-tracking branch 'origin/master' into xaigEddie Hung2019-06-272-5/+26
| |\ \ \
| * | | | Merge origin/masterEddie Hung2019-06-271-0/+320
| * | | | Merge remote-tracking branch 'origin/master' into xaigEddie Hung2019-06-255-1/+577
| |\ \ \ \
| * | | | | Add tests/various/abc9.{v,ys} with SCC testEddie Hung2019-06-242-0/+19
| * | | | | Merge remote-tracking branch 'origin/master' into xaigEddie Hung2019-06-215-1/+298
| |\ \ \ \ \