| Commit message (Collapse) | Author | Age | Files | Lines |
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Fixes #1854.
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Fixes #2765.
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Signed-off-by: gatecat <gatecat@ds0.me>
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Signed-off-by: gatecat <gatecat@ds0.me>
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Signed-off-by: gatecat <gatecat@ds0.me>
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Fixes #2729.
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Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
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* abc9_ops: uniquify blackboxes too
* abc9_ops: update comment
* abc9_ops: allow bypass for param-less blackboxes
* Add tests
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* xilinx: add SCC test for DSP48E1
* xilinx: Gate DSP48E1 being a whitebox behind ALLOW_WHITEBOX_DSP48E1
Have a test that checks it works through ABC9 when enabled
* abc9 to break SCCs using $__ABC9_SCC_BREAKER module
* Add test
* abc9_ops: remove refs to (* abc9_keep *) on wires
* abc9_ops: do not bypass cells in an SCC
* Add myself to CODEOWNERS for abc9*
* Fix compile
* abc9_ops: run -prep_hier before scc
* Fix tests
* Remove bug reference pending fix
* abc9: fix for -prep_hier -dff
* xaiger: restore PI handling
* abc9_ops: -prep_xaiger sigmap
* abc9_ops: -mark_scc -> -break_scc
* abc9: eliminate hard-coded abc9.box from tests
Also tidy up
* Address review
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Co-authored-by: Grzegorz Latosiński <glatosinski@antmicro.com>
Co-authored-by: Maciej Kurc <mkurc@antmicro.com>
Co-authored-by: Tarachand Pagarani <tpagarani@quicklogic.com>
Co-authored-by: Lalit Sharma <lsharma@quicklogic.com>
Co-authored-by: kkumar23 <kkumar@quicklogic.com>
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Calling log_signal is problematic for several reasons:
- with recent changes, empty string is serialized as { }, which violates
the "no spaces in IdString" rule
- the type (plain / real / signed / string) is dropped, wrongly conflating
functionally different values and potentially introducing a subtle
elaboration bug
Instead, use a custom simple serialization scheme.
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This prevents issues like processes in whiteboxes triggering an error in
the JSON backend.
Signed-off-by: gatecat <gatecat@ds0.me>
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This breaks the ability to use a global typename as a standard
identifier in a subsequent input file. This is otherwise backwards
compatible, including for sources which previously included conflicting
typedefs in each input file.
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From IEEE1364-2005, section 7.3 buf and not gates:
> These two logic gates shall have one input and one or more outputs.
> The last terminal in the terminal list shall connect to the input of the
> logic gate, and the other terminals shall connect to the outputs of
> the logic gate.
yosys does not follow this and instead interprets the first argument as
the output, the second as the input and ignores the rest.
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Signed-off-by: gatecat <gatecat@ds0.me>
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The already-existing special case for conditionals on clock has been
remade as follows:
- now triggered for the last remaining edge trigger after all others
have been converted to async reset, not just when there is only one
sync rule in the first place
- does not require all contained assignments to be constant, as opposed
to a reset conditional — merely const-folds the condition
In addition, the code has been refactored a bit; as a bonus, the
priority order of async resets found is now preserved in resulting sync
rule ordering (though this is not yet respected by proc_dff).
Fixes #2656.
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Fixes #2546.
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Among other problems, this also fixes equality comparisons between
SigSpec by enforcing a canonical form.
Also fix another minor issue with possible non-canonical SigSpec.
Fixes #2623.
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This defers the simplification of globals so that globals in one file
may depend on globals in other files. Adds a simplify() call downstream
because globals are appended at the end.
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It was previously possible to override global parameters on a
per-instance basis. This could be dangerous when using positional
parameter bindings, hiding oversupplied parameters.
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Fixes #2619.
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These have no defined semantics, making the tests non-deterministic.
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sv: support for parameters without default values
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- Modules with a parameter without a default value will be automatically
deferred until the hierarchy pass
- Allows for parameters without defaults as module items, rather than
just int the `parameter_port_list`, despite being forbidden in the LRM
- Check for parameters without defaults that haven't been overriden
- Add location info to parameter/localparam declarations
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verilog: impose limit on maximum expression width
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Designs with unreasonably wide expressions would previously get stuck
allocating memory forever.
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- Fix explicit size cast of unbased unsized literals
- Fix unbased unsized literal bound directly to port
- Output `is_unsized` flag in `dumpAst`
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Declaring the ports as standard module items already worked as expected.
This adds a missing usage of `checkRange()` so that headers such as
`module m(output integer x);` now work correctly.
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- track depth so we know whether to consider higher-level elsifs
- error on unmatched endif/elsif/else
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New test cases on one branch may be automatically copied from simple/ to
simple_abc9/, causing failures when switching to another branch. This
updates the simple_abc9 script to set aside extraneous tests in a
non-destructive way.
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genrtlil: improve name conflict error messaging
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- Standard data declarations can now use any integer type
- Parameters and localparams can now use any integer type
- Function returns types can now use any integer type
- Fix `parameter logic`, `localparam reg`, etc. to be 1 bit (previously 32 bits)
- Added longint type (64 bits)
- Unified parser source for integer type widths
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turn-off (#2566)
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verilog: fix sizing of constant args for tasks/functions
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- Simplify synthetic localparams for normal calls to update their width
- This step was inadvertently removed alongside `added_mod_children`
- Support redeclaration of constant function arguments
- `eval_const_function` never correctly handled this, but the issue
was not exposed in the existing tests until the recent change to
always attempt constant function evaluation when all-const args
are used
- Check asserts in const_arg_loop and const_func tests
- Add coverage for width mismatch error cases
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values.
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