iCE40/yosys - [no description]

	Commit message (Expand)	Author	Age	Files	Lines
*	Add new helper class for merging FFs into cells, use for memory_dff.	Marcelina Kościelnicka	2021-05-23	1	-0/+17
*	opt_mem: Remove write ports with const-0 EN.	Marcelina Kościelnicka	2021-05-23	1	-0/+34
*	tests/blif: Add missing gitignore	Marcelina Kościelnicka	2021-05-20	1	-0/+1
*	intel_alm: Fix illegal carry chains	gatecat	2021-05-15	2	-4/+4
*	intel_alm: Add global buffer insertion	gatecat	2021-05-15	13	-41/+41
*	intel_alm: Add IO buffer insertion	gatecat	2021-05-15	13	-39/+39
*	sv: check validity of package end label	Zachary Snow	2021-05-10	1	-0/+15
*	blif: Use library cells' start_offset and upto for wideports.	Marcelina Kościelnicka	2021-05-08	2	-0/+26
*	opt_dff: Fix NOT gates wired in reverse.	Marcelina Kościelnicka	2021-05-04	1	-8/+13
*	Add default assignments to SB_LUT4	Claire Xenia Wolf	2021-04-20	1	-1/+1
*	quicklogic: ABC9 synthesis	Lofty	2021-04-17	6	-17/+17
*	preproc: test coverage for #2712	Zachary Snow	2021-03-30	3	-0/+18
*	abc9: uniquify blackboxes like whiteboxes (#2695)	Eddie Hung	2021-03-29	1	-1/+56
*	abc9: fix SCC issues (#2694)	Eddie Hung	2021-03-29	3	-12/+27
*	quicklogic: Add .gitignore file for test outputs.	Marcelina Kościelnicka	2021-03-23	1	-0/+4
*	verilog: check entire user type stack for type definition	Xiretza	2021-03-21	1	-0/+10
*	sv: allow typenames as function return types	Zachary Snow	2021-03-19	2	-0/+40
*	quicklogic: PolarPro 3 support	Lofty	2021-03-18	10	-0/+262
*	ast: Use better parameter serialization for paramod names.	Marcelina Kościelnicka	2021-03-18	1	-3/+3
*	Blackbox all whiteboxes after synthesis	gatecat	2021-03-17	1	-9/+9
*	sv: carry over global typedefs from previous files	Zachary Snow	2021-03-17	2	-0/+60
*	verilog: fix buf/not primitives with multiple outputs	Xiretza	2021-03-17	1	-0/+15
*	blackbox: Include whiteboxed modules	gatecat	2021-03-17	1	-0/+14
*	verilog: support module scope identifiers in parametric modules	Zachary Snow	2021-03-16	1	-0/+29
*	proc_arst: Add special-casing of clock signal in conditionals.	Marcelina Kościelnicka	2021-03-15	1	-0/+31
*	opt_clean: Remove init attribute bits together with removed DFFs.	Marcelina Kościelnicka	2021-03-15	1	-11/+20
*	rtlil: Disallow 0-width chunks in SigSpec.	Marcelina Kościelnicka	2021-03-15	1	-0/+14
*	sv: allow globals in one file to depend on globals in another	Zachary Snow	2021-03-12	1	-0/+20
*	verilog: disallow overriding global parameters	Zachary Snow	2021-03-11	1	-0/+16
*	memory_dff: Remove now-useless write port handling.	Marcelina Kościelnicka	2021-03-08	2	-2/+1
*	proc_dff: Fix emitted FF when a register is not assigned in async reset	Marcelina Kościelnicka	2021-03-08	1	-0/+23
*	tests/bram: Do not generate write address collisions.	Marcelina Kościelnicka	2021-03-08	1	-5/+23
*	Merge pull request #2626 from zachjs/param-no-default	whitequark	2021-03-07	10	-0/+177
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\| *	sv: support for parameters without default values	Zachary Snow	2021-03-02	10	-0/+177
* \|	Merge pull request #2632 from zachjs/width-limit	whitequark	2021-03-07	2	-0/+33
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\| * \|	verilog: impose limit on maximum expression width	Zachary Snow	2021-03-04	2	-0/+33
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* /	sv: fix some edge cases for unbased unsized literals	Zachary Snow	2021-03-06	2	-0/+47
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*	verilog: fix sizing of ports with int types in module headers	Zachary Snow	2021-03-01	2	-0/+61
*	verilog: fix handling of nested ifdef directives	Zachary Snow	2021-03-01	7	-0/+159
*	Set aside extraneous tests in simple_abc9 test suite	Zachary Snow	2021-03-01	2	-0/+19
*	Merge pull request #2615 from zachjs/genrtlil-conflict	whitequark	2021-03-01	6	-0/+56
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\| *	genrtlil: improve name conflict error messaging	Zachary Snow	2021-02-26	6	-0/+56
* \|	sv: extended support for integer types	Zachary Snow	2021-02-28	4	-0/+78
* \|	Add tests for $countbits	Michael Singer	2021-02-26	2	-0/+76
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*	Extend "delay" expressions to handle pair and triplet, i.e. rise, fall and tu...	TimRudy	2021-02-24	2	-0/+438
*	Add tests for some common techmap files.	Marcelina Kościelnicka	2021-02-24	3	-0/+50
*	Merge pull request #2594 from zachjs/func-arg-width	whitequark	2021-02-23	8	-37/+94
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\| *	verilog: fix sizing of constant args for tasks/functions	Zachary Snow	2021-02-21	8	-37/+94
* \|	machxo2: Switch to LUT4 sim model which propagates less undefined/don't care ...	William D. Jones	2021-02-23	1	-1/+1
* \|	machxo2: Update tribuf test to reflect active-low OE.	William D. Jones	2021-02-23	1	-1/+2