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| author | Xiretza <xiretza@xiretza.xyz> | 2021-03-17 00:18:36 +0100 |
|---|---|---|
| committer | Zachary Snow <zachary.j.snow@gmail.com> | 2021-03-17 11:44:03 -0400 |
| commit | 092e923330ce23adffa7843a27bdba8a0b139e58 (patch) | |
| tree | 08bed305ed18522ae38b0718de8fdffa04814d1f /tests | |
| parent | dd6d34f461910a120ac95c485fe34cca6485b95e (diff) | |
| download | yosys-092e923330ce23adffa7843a27bdba8a0b139e58.tar.gz yosys-092e923330ce23adffa7843a27bdba8a0b139e58.tar.bz2 yosys-092e923330ce23adffa7843a27bdba8a0b139e58.zip | |
verilog: fix buf/not primitives with multiple outputs
From IEEE1364-2005, section 7.3 buf and not gates:
> These two logic gates shall have one input and one or more outputs.
> The last terminal in the terminal list shall connect to the input of the
> logic gate, and the other terminals shall connect to the outputs of
> the logic gate.
yosys does not follow this and instead interprets the first argument as
the output, the second as the input and ignores the rest.
Diffstat (limited to 'tests')
| -rw-r--r-- | tests/simple/verilog_primitives.v | 15 |
1 files changed, 15 insertions, 0 deletions
diff --git a/tests/simple/verilog_primitives.v b/tests/simple/verilog_primitives.v new file mode 100644 index 000000000..0ee07393b --- /dev/null +++ b/tests/simple/verilog_primitives.v @@ -0,0 +1,15 @@ +module verilog_primitives ( + input wire in1, in2, in3, + output wire out_buf0, out_buf1, out_buf2, out_buf3, out_buf4, + output wire out_not0, out_not1, out_not2, + output wire out_xnor +); + +buf u_buf0 (out_buf0, in1); +buf u_buf1 (out_buf1, out_buf2, out_buf3, out_buf4, in2); + +not u_not0 (out_not0, out_not1, out_not2, in1); + +xnor u_xnor0 (out_xnor, in1, in2, in3); + +endmodule |