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| author | Marcelina Kościelnicka <mwk@0x04.net> | 2021-03-06 03:59:03 +0100 |
|---|---|---|
| committer | Marcelina Kościelnicka <mwk@0x04.net> | 2021-03-08 17:01:43 +0100 |
| commit | 760284033d6f255790d44bfcda0d1625a0c7bc87 (patch) | |
| tree | e23050e2e3c0c85fd560d0f63dca347832d8e24f /tests | |
| parent | bc717abad2187b2aacaac7e9b8e152462769056a (diff) | |
| download | yosys-760284033d6f255790d44bfcda0d1625a0c7bc87.tar.gz yosys-760284033d6f255790d44bfcda0d1625a0c7bc87.tar.bz2 yosys-760284033d6f255790d44bfcda0d1625a0c7bc87.zip | |
proc_dff: Fix emitted FF when a register is not assigned in async reset
Fixes #2619.
Diffstat (limited to 'tests')
| -rw-r--r-- | tests/proc/bug2619.ys | 23 |
1 files changed, 23 insertions, 0 deletions
diff --git a/tests/proc/bug2619.ys b/tests/proc/bug2619.ys new file mode 100644 index 000000000..a080b94f5 --- /dev/null +++ b/tests/proc/bug2619.ys @@ -0,0 +1,23 @@ +read_verilog << EOT + +module top(...); + +input D1, D2, R, CLK; +output reg Q1, Q2; + +always @(posedge CLK, posedge R) begin + Q1 <= 0; + if (!R) begin + Q1 <= D1; + Q2 <= D2; + end +end + +endmodule + +EOT + +proc +opt +select -assert-count 1 t:$adff +select -assert-count 1 t:$dffe |