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author | whitequark <whitequark@whitequark.org> | 2021-03-01 08:10:19 -0800 |
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committer | GitHub <noreply@github.com> | 2021-03-01 08:10:19 -0800 |
commit | ca5f5ffcd63bc18a5e0ae1bdb1065f148ce3c4da (patch) | |
tree | d6fb01c328a9da739b2f2c0b448fe47791258e5d /tests | |
parent | 0fb4224ebca86156a1296b9210116d9a9cbebeed (diff) | |
parent | bbff844acd15c274a6619050d1251aea4698ef56 (diff) | |
download | yosys-ca5f5ffcd63bc18a5e0ae1bdb1065f148ce3c4da.tar.gz yosys-ca5f5ffcd63bc18a5e0ae1bdb1065f148ce3c4da.tar.bz2 yosys-ca5f5ffcd63bc18a5e0ae1bdb1065f148ce3c4da.zip |
Merge pull request #2615 from zachjs/genrtlil-conflict
genrtlil: improve name conflict error messaging
Diffstat (limited to 'tests')
-rw-r--r-- | tests/verilog/conflict_assert.ys | 8 | ||||
-rw-r--r-- | tests/verilog/conflict_cell_memory.ys | 9 | ||||
-rw-r--r-- | tests/verilog/conflict_interface_port.ys | 17 | ||||
-rw-r--r-- | tests/verilog/conflict_memory_wire.ys | 7 | ||||
-rw-r--r-- | tests/verilog/conflict_pwire.ys | 8 | ||||
-rw-r--r-- | tests/verilog/conflict_wire_memory.ys | 7 |
6 files changed, 56 insertions, 0 deletions
diff --git a/tests/verilog/conflict_assert.ys b/tests/verilog/conflict_assert.ys new file mode 100644 index 000000000..121a0cf51 --- /dev/null +++ b/tests/verilog/conflict_assert.ys @@ -0,0 +1,8 @@ +logger -expect error "Cannot add procedural assertion `\\x' because a signal with the same name was already created" 1 +read_verilog -sv <<EOT +module top; + wire x, y; + always @* + x: assert(y == 1); +endmodule +EOT diff --git a/tests/verilog/conflict_cell_memory.ys b/tests/verilog/conflict_cell_memory.ys new file mode 100644 index 000000000..ddc67596f --- /dev/null +++ b/tests/verilog/conflict_cell_memory.ys @@ -0,0 +1,9 @@ +logger -expect error "Cannot add cell `\\x' because a memory with the same name was already created" 1 +read_verilog <<EOT +module mod; +endmodule +module top; + reg [2:0] x [0:0]; + mod x(); +endmodule +EOT diff --git a/tests/verilog/conflict_interface_port.ys b/tests/verilog/conflict_interface_port.ys new file mode 100644 index 000000000..b97ec029e --- /dev/null +++ b/tests/verilog/conflict_interface_port.ys @@ -0,0 +1,17 @@ +logger -expect error "Cannot add interface port `\\i' because a signal with the same name was already created" 1 +read_verilog -sv <<EOT +interface intf; + logic x; + assign x = 1; + modport m(input x); +endinterface +module mod(intf.m i); + wire x; + assign x = i.x; + wire i; +endmodule +module top; + intf i(); + mod m(i); +endmodule +EOT diff --git a/tests/verilog/conflict_memory_wire.ys b/tests/verilog/conflict_memory_wire.ys new file mode 100644 index 000000000..5c296074f --- /dev/null +++ b/tests/verilog/conflict_memory_wire.ys @@ -0,0 +1,7 @@ +logger -expect error "Cannot add memory `\\x' because a signal with the same name was already created" 1 +read_verilog <<EOT +module top; + reg [2:0] x; + reg [2:0] x [0:0]; +endmodule +EOT diff --git a/tests/verilog/conflict_pwire.ys b/tests/verilog/conflict_pwire.ys new file mode 100644 index 000000000..ecc30d33a --- /dev/null +++ b/tests/verilog/conflict_pwire.ys @@ -0,0 +1,8 @@ +logger -expect error "Cannot add pwire `\\x' because a signal with the same name was already created" 1 +read_verilog -pwires <<EOT +module top; + wire x; + assign x = 1; + localparam x = 2; +endmodule +EOT diff --git a/tests/verilog/conflict_wire_memory.ys b/tests/verilog/conflict_wire_memory.ys new file mode 100644 index 000000000..77520fea9 --- /dev/null +++ b/tests/verilog/conflict_wire_memory.ys @@ -0,0 +1,7 @@ +logger -expect error "Cannot add signal `\\x' because a memory with the same name was already created" 1 +read_verilog <<EOT +module top; + reg [2:0] x [0:0]; + reg [2:0] x; +endmodule +EOT |