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* Merge remote-tracking branch 'origin/eddie/muxpack' into xc7muxEddie Hung2019-06-062-0/+41
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| * Fix and test for balanced caseEddie Hung2019-06-062-0/+41
* | Merge remote-tracking branch 'origin/eddie/muxpack' into xc7muxEddie Hung2019-06-0615-0/+512
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| * Fix warningsEddie Hung2019-06-062-3/+3
| * Support cascading $pmux.A with $mux.A and $mux.BEddie Hung2019-06-062-0/+40
| * Add non exclusive testEddie Hung2019-06-062-0/+56
| * One more and tidy upEddie Hung2019-06-062-6/+28
| * Add a few more special case testsEddie Hung2019-06-062-0/+51
| * Add tests, fix for !=Eddie Hung2019-06-062-0/+78
| * Moved tests that fail with Icarus Verilog to /tests/various. Those tests are ...Maciej Kurc2019-06-044-0/+46
| * Added tests for attributesMaciej Kurc2019-06-039-0/+219
* | Merge remote-tracking branch 'origin/master' into xc7muxEddie Hung2019-06-031-0/+4
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| * Merge pull request #1049 from YosysHQ/clifford/fix1047Clifford Wolf2019-05-281-0/+4
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| | * Do not use shiftmul peepopt pattern when mul result is truncated, fixes #1047Clifford Wolf2019-05-281-0/+4
* | | Rename to #23Eddie Hung2019-05-291-3/+3
* | | Add abc_test024Eddie Hung2019-05-291-6/+19
* | | Add abc9_test022Eddie Hung2019-05-281-0/+22
* | | From masterEddie Hung2019-05-281-1/+1
* | | Merge remote-tracking branch 'origin/master' into xc7muxEddie Hung2019-05-283-27/+84
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| * | Add actual wandwor test that is part of "make test"Clifford Wolf2019-05-282-33/+36
| * | Merge branch 'master' into wandworStefan Biereigel2019-05-272-0/+76
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| | * Fix initEddie Hung2019-05-241-27/+27
| | * Fix typosEddie Hung2019-05-241-6/+6
| | * Add more testsEddie Hung2019-05-242-20/+41
| | * Call procEddie Hung2019-05-241-1/+1
| | * Fix duplicate driverEddie Hung2019-05-241-15/+15
| * | reformat wand/wor testStefan Biereigel2019-05-271-22/+21
| * | remove port direction workaround from test caseStefan Biereigel2019-05-271-2/+1
| * | add simple test case for wand/worStefan Biereigel2019-05-231-0/+35
* | | Merge remote-tracking branch 'origin/eddie/opt_rmdff' into xc7muxEddie Hung2019-05-232-0/+55
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| * | Add opt_rmdff testsEddie Hung2019-05-232-0/+55
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* | Merge remote-tracking branch 'origin/master' into xc7muxEddie Hung2019-05-2110-5/+225
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| * Added tests for Verilog frontent for attributes on parameters and localparamsMaciej Kurc2019-05-162-0/+22
| * Add test case from #997Clifford Wolf2019-05-071-0/+12
| * Merge pull request #946 from YosysHQ/clifford/specifyClifford Wolf2019-05-062-0/+86
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| | * Improve tests/various/specify.ysClifford Wolf2019-05-061-2/+32
| | * More testingEddie Hung2019-05-032-2/+5
| | * Fix spacingEddie Hung2019-05-031-6/+6
| | * Add quick-and-dirty specify testsEddie Hung2019-05-032-0/+53
| * | Merge pull request #975 from YosysHQ/clifford/fix968Clifford Wolf2019-05-061-0/+25
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| | * | Merge branch 'master' of github.com:YosysHQ/yosys into clifford/fix968Clifford Wolf2019-05-066-5/+60
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| | * | Add additional test cases for for-loopsClifford Wolf2019-05-011-0/+25
| * | | Merge pull request #871 from YosysHQ/verific_importClifford Wolf2019-05-061-0/+52
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| | * | Add tests/various/chparam.shClifford Wolf2019-05-061-0/+52
| * | | iverilog with simcells.v as wellEddie Hung2019-05-031-1/+2
| * | | Merge pull request #969 from YosysHQ/clifford/pmgenstuffClifford Wolf2019-05-031-0/+9
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| * | | Merge pull request #976 from YosysHQ/clifford/fix974Clifford Wolf2019-05-031-0/+22
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| | * | | Add splitcmplxassign test case and silence splitcmplxassign warningClifford Wolf2019-05-011-0/+22
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| * | | Fix typo in tests/svinterfaces/runone.shClifford Wolf2019-05-031-2/+2
| * | | fail svinterfaces testcases on yosys error exitJakob Wenzel2019-05-021-2/+2