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* Merge remote-tracking branch 'origin/eddie/submod_po' into xaig_dffEddie Hung2019-11-221-3/+0
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| * Remove redundant flattenEddie Hung2019-11-221-2/+0
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| * Stray dumpEddie Hung2019-11-221-1/+0
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* | Merge remote-tracking branch 'origin/eddie/submod_po' into xaig_dffEddie Hung2019-11-221-0/+28
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| * Add another test with constant driverEddie Hung2019-11-221-0/+28
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* | Add testcase for signal used as part input part outputEddie Hung2019-11-221-0/+5
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* | Merge remote-tracking branch 'origin/eddie/submod_po' into xaig_dffEddie Hung2019-11-221-0/+25
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| * Cleanup spacingEddie Hung2019-11-221-2/+1
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| * Add testcaseEddie Hung2019-11-221-0/+26
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* | Merge branch 'eddie/clkpart' into xaig_dffEddie Hung2019-11-222-1/+63
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| * Merge pull request #1511 from YosysHQ/dave/alwaysClifford Wolf2019-11-221-0/+63
| |\ | | | | | | sv: Error checking for always_comb, always_latch and always_ff
| | * sv: Add tests for SV always typesDavid Shah2019-11-211-0/+63
| | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
| * | gowin: Remove show command from tests.Marcin Kościelnicki2019-11-221-1/+0
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* | Missing endmoduleEddie Hung2019-11-221-0/+1
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* | Merge branch 'eddie/xaig_dff_adff' into xaig_dffEddie Hung2019-11-213-3/+37
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| * | Add a equiv test tooEddie Hung2019-11-192-0/+23
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| * | Add two testsEddie Hung2019-11-191-0/+12
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* | Add testEddie Hung2019-11-211-1/+6
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* | Add multi clock testEddie Hung2019-11-201-0/+5
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* Merge pull request #1449 from pepijndevos/gowinClifford Wolf2019-11-1912-0/+248
|\ | | | | Improvements for gowin support
| * Merge branch 'master' of https://github.com/YosysHQ/yosys into gowinPepijn de Vos2019-11-165-17/+34
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| * | fix fsm test with proper clock enable polarityPepijn de Vos2019-11-111-0/+11
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| * | fix wide lutsPepijn de Vos2019-11-061-7/+10
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| * | don't cound exact luts in big muxes; futile and fragilePepijn de Vos2019-10-301-3/+0
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| * | add tristate buffer and testPepijn de Vos2019-10-281-0/+13
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| * | do not use wide luts in testcasePepijn de Vos2019-10-281-3/+3
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| * | ALU sim tweaksPepijn de Vos2019-10-241-2/+2
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| * | Add some testsPepijn de Vos2019-10-2110-0/+224
| | | | | | | | | | | | | | | | | | | | | | | | Copied from Efinix. * fsm is broken * latch and tribuf are not implemented yet * memory maps to dram
* | | Fix #1462, #1480.Marcin Kościelnicki2019-11-192-0/+29
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* | | Fix #1496.Marcin Kościelnicki2019-11-181-0/+13
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* | Fixed testsMiodrag Milanovic2019-11-115-17/+34
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* fixed errorMiodrag Milanovic2019-10-181-1/+1
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* Unify verilog styleMiodrag Milanovic2019-10-1811-191/+157
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* Common memory test now sharedMiodrag Milanovic2019-10-1810-89/+5
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* Remove not needed testsMiodrag Milanovic2019-10-184-52/+0
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* Share common testsMiodrag Milanovic2019-10-18103-1316/+178
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* fix yosys pathMiodrag Milanovic2019-10-181-2/+2
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* Fix path to yosysMiodrag Milanovic2019-10-185-5/+5
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* Moved all tests in arch sub directoryMiodrag Milanovic2019-10-18150-0/+0
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* Add async2syncMiodrag Milanovic2019-10-182-8/+8
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* Merge branch 'master' into mmicko/efinixMiodrag Milanović2019-10-1893-59/+1832
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| * Merge branch 'master' into mmicko/anlogicMiodrag Milanović2019-10-1873-59/+1403
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| | * Merge branch 'master' into eddie/pr1352Miodrag Milanović2019-10-1843-59/+763
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| | | * hierarchy - proc reorderMiodrag Milanovic2019-10-1810-17/+21
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| | | * Make equivalence work with latest masterMiodrag Milanovic2019-10-173-8/+8
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| | | * remove not needed top moduleMiodrag Milanovic2019-10-172-20/+2
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| | | * remove not needed top moduleMiodrag Milanovic2019-10-172-17/+2
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| | | * split muxes synth per typeMiodrag Milanovic2019-10-172-39/+39
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| | | * Test dffs separetelyMiodrag Milanovic2019-10-172-26/+19
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| | | * Split latches into separete testsMiodrag Milanovic2019-10-172-42/+27
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