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author | Clifford Wolf <clifford@clifford.at> | 2019-11-22 15:32:29 +0100 |
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committer | GitHub <noreply@github.com> | 2019-11-22 15:32:29 +0100 |
commit | 72d2ef6fd071a8b2b9e1a77ddab3a9d632aa0f3d (patch) | |
tree | b499121c6a6f5bd269c871ba08d52656784e03c9 /tests | |
parent | e110df9c484d5c87429c55da1c1d83fd509a78b3 (diff) | |
parent | b60f32c6ecc27e0fa1f81a1055cfd1105ed647bd (diff) | |
download | yosys-72d2ef6fd071a8b2b9e1a77ddab3a9d632aa0f3d.tar.gz yosys-72d2ef6fd071a8b2b9e1a77ddab3a9d632aa0f3d.tar.bz2 yosys-72d2ef6fd071a8b2b9e1a77ddab3a9d632aa0f3d.zip |
Merge pull request #1511 from YosysHQ/dave/always
sv: Error checking for always_comb, always_latch and always_ff
Diffstat (limited to 'tests')
-rwxr-xr-x | tests/various/svalways.sh | 63 |
1 files changed, 63 insertions, 0 deletions
diff --git a/tests/various/svalways.sh b/tests/various/svalways.sh new file mode 100755 index 000000000..2cc09f801 --- /dev/null +++ b/tests/various/svalways.sh @@ -0,0 +1,63 @@ +#!/bin/bash + +trap 'echo "ERROR in svalways.sh" >&2; exit 1' ERR + +# Good case +../../yosys -f "verilog -sv" -qp proc - <<EOT +module top(input clk, en, d, output reg p, q, r); + +always_ff @(posedge clk) + p <= d; + +always_comb + q = ~d; + +always_latch + if (en) r = d; + +endmodule +EOT + +# Incorrect always_comb syntax +((../../yosys -f "verilog -sv" -qp proc -|| true) <<EOT +module top(input d, output reg q); + +always_comb @(d) + q = ~d; + +endmodule +EOT +) 2>&1 | grep -F "<stdin>:3: ERROR: syntax error, unexpected '@'" > /dev/null + +# Incorrect use of always_comb +((../../yosys -f "verilog -sv" -qp proc -|| true) <<EOT +module top(input en, d, output reg q); + +always_comb + if (en) q = d; + +endmodule +EOT +) 2>&1 | grep -F "ERROR: Latch inferred for signal \`\\top.\\q' from always_comb process" > /dev/null + +# Incorrect use of always_latch +((../../yosys -f "verilog -sv" -qp proc -|| true) <<EOT +module top(input en, d, output reg q); + +always_latch + q = !d; + +endmodule +EOT +) 2>&1 | grep -F "ERROR: No latch inferred for signal \`\\top.\\q' from always_latch process" > /dev/null + +# Incorrect use of always_ff +((../../yosys -f "verilog -sv" -qp proc -|| true) <<EOT +module top(input en, d, output reg q); + +always_ff @(*) + q = !d; + +endmodule +EOT +) 2>&1 | grep -F "ERROR: Found non edge/level sensitive event in always_ff process" > /dev/null |