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author | Clifford Wolf <clifford@clifford.at> | 2019-11-19 17:29:27 +0100 |
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committer | GitHub <noreply@github.com> | 2019-11-19 17:29:27 +0100 |
commit | 7ea0a5937ba2572f6d9d62e73e24df480c49561d (patch) | |
tree | 7825f438b83fdc730764ba15016eeeac9eb0cf41 /tests | |
parent | 15232a48af60fb7da3c3afdd144882ace2194197 (diff) | |
parent | 8ab412eb16b1d4f98117247bf85e0c37627ee459 (diff) | |
download | yosys-7ea0a5937ba2572f6d9d62e73e24df480c49561d.tar.gz yosys-7ea0a5937ba2572f6d9d62e73e24df480c49561d.tar.bz2 yosys-7ea0a5937ba2572f6d9d62e73e24df480c49561d.zip |
Merge pull request #1449 from pepijndevos/gowin
Improvements for gowin support
Diffstat (limited to 'tests')
-rw-r--r-- | tests/arch/gowin/.gitignore | 3 | ||||
-rw-r--r-- | tests/arch/gowin/add_sub.ys | 13 | ||||
-rw-r--r-- | tests/arch/gowin/adffs.ys | 55 | ||||
-rw-r--r-- | tests/arch/gowin/counter.ys | 15 | ||||
-rw-r--r-- | tests/arch/gowin/dffs.ys | 25 | ||||
-rw-r--r-- | tests/arch/gowin/fsm.ys | 11 | ||||
-rw-r--r-- | tests/arch/gowin/logic.ys | 13 | ||||
-rw-r--r-- | tests/arch/gowin/memory.ys | 18 | ||||
-rw-r--r-- | tests/arch/gowin/mux.ys | 50 | ||||
-rwxr-xr-x | tests/arch/gowin/run-test.sh | 20 | ||||
-rw-r--r-- | tests/arch/gowin/shifter.ys | 12 | ||||
-rw-r--r-- | tests/arch/gowin/tribuf.ys | 13 |
12 files changed, 248 insertions, 0 deletions
diff --git a/tests/arch/gowin/.gitignore b/tests/arch/gowin/.gitignore new file mode 100644 index 000000000..b48f808a1 --- /dev/null +++ b/tests/arch/gowin/.gitignore @@ -0,0 +1,3 @@ +/*.log +/*.out +/run-test.mk diff --git a/tests/arch/gowin/add_sub.ys b/tests/arch/gowin/add_sub.ys new file mode 100644 index 000000000..9b53dc0a9 --- /dev/null +++ b/tests/arch/gowin/add_sub.ys @@ -0,0 +1,13 @@ +read_verilog ../common/add_sub.v +hierarchy -top top +proc +equiv_opt -assert -map +/gowin/cells_sim.v synth_gowin # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd top # Constrain all select calls below inside the top module +select -assert-count 8 t:ALU +select -assert-count 8 t:OBUF +select -assert-count 8 t:IBUF +select -assert-count 1 t:GND +select -assert-count 1 t:VCC +select -assert-none t:ALU t:OBUF t:IBUF t:GND t:VCC %% t:* %D + diff --git a/tests/arch/gowin/adffs.ys b/tests/arch/gowin/adffs.ys new file mode 100644 index 000000000..fc7ee01f2 --- /dev/null +++ b/tests/arch/gowin/adffs.ys @@ -0,0 +1,55 @@ +read_verilog ../common/adffs.v +design -save read + +hierarchy -top adff +proc +equiv_opt -async2sync -assert -map +/gowin/cells_sim.v synth_gowin # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd adff # Constrain all select calls below inside the top module +stat +select -assert-count 1 t:DFFC +select -assert-count 3 t:IBUF +select -assert-count 1 t:OBUF + +select -assert-none t:DFFC t:IBUF t:OBUF %% t:* %D + + +design -load read +hierarchy -top adffn +proc +equiv_opt -async2sync -assert -map +/gowin/cells_sim.v synth_gowin # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd adffn # Constrain all select calls below inside the top module +select -assert-count 1 t:DFFC +select -assert-count 1 t:LUT1 +select -assert-count 3 t:IBUF +select -assert-count 1 t:OBUF + +select -assert-none t:DFFC t:IBUF t:OBUF t:LUT1 %% t:* %D + + +design -load read +hierarchy -top dffs +proc +equiv_opt -async2sync -assert -map +/gowin/cells_sim.v synth_gowin # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd dffs # Constrain all select calls below inside the top module +select -assert-count 1 t:DFFS +select -assert-count 4 t:IBUF +select -assert-count 1 t:OBUF + +select -assert-none t:DFFS t:IBUF t:OBUF %% t:* %D + + +design -load read +hierarchy -top ndffnr +proc +equiv_opt -async2sync -assert -map +/gowin/cells_sim.v synth_gowin # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd ndffnr # Constrain all select calls below inside the top module +select -assert-count 1 t:DFFNR +select -assert-count 1 t:LUT1 +select -assert-count 4 t:IBUF +select -assert-count 1 t:OBUF + +select -assert-none t:DFFNR t:IBUF t:OBUF t:LUT1 %% t:* %D diff --git a/tests/arch/gowin/counter.ys b/tests/arch/gowin/counter.ys new file mode 100644 index 000000000..920479d44 --- /dev/null +++ b/tests/arch/gowin/counter.ys @@ -0,0 +1,15 @@ +read_verilog ../common/counter.v +hierarchy -top top +proc +flatten +equiv_opt -map +/gowin/cells_sim.v synth_gowin # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd top # Constrain all select calls below inside the top module + +select -assert-count 8 t:DFFC +select -assert-count 8 t:ALU +select -assert-count 1 t:GND +select -assert-count 1 t:VCC +select -assert-count 2 t:IBUF +select -assert-count 8 t:OBUF +select -assert-none t:DFFC t:ALU t:GND t:VCC t:IBUF t:OBUF %% t:* %D diff --git a/tests/arch/gowin/dffs.ys b/tests/arch/gowin/dffs.ys new file mode 100644 index 000000000..9c012213f --- /dev/null +++ b/tests/arch/gowin/dffs.ys @@ -0,0 +1,25 @@ +read_verilog ../common/dffs.v +design -save read + +hierarchy -top dff +proc +equiv_opt -assert -map +/gowin/cells_sim.v synth_gowin # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd dff # Constrain all select calls below inside the top module +select -assert-count 1 t:DFF +select -assert-count 2 t:IBUF +select -assert-count 1 t:OBUF + +select -assert-none t:DFF t:IBUF t:OBUF %% t:* %D + +design -load read +hierarchy -top dffe +proc +equiv_opt -assert -map +/gowin/cells_sim.v synth_gowin # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd dffe # Constrain all select calls below inside the top module +select -assert-count 1 t:DFFE +select -assert-count 3 t:IBUF +select -assert-count 1 t:OBUF + +select -assert-none t:DFFE t:IBUF t:OBUF %% t:* %D diff --git a/tests/arch/gowin/fsm.ys b/tests/arch/gowin/fsm.ys new file mode 100644 index 000000000..ce4504522 --- /dev/null +++ b/tests/arch/gowin/fsm.ys @@ -0,0 +1,11 @@ +read_verilog ../common/fsm.v +hierarchy -top fsm +proc +flatten + +equiv_opt -run :prove -map +/gowin/cells_sim.v synth_gowin # equivalency check +miter -equiv -make_assert -flatten gold gate miter +sat -verify -show-all -dump_vcd x.vcd -prove-asserts -set-at 1 in_reset 1 -seq 20 -prove-skip 1 miter + +#design -load postopt +#shell diff --git a/tests/arch/gowin/logic.ys b/tests/arch/gowin/logic.ys new file mode 100644 index 000000000..d2b9e4540 --- /dev/null +++ b/tests/arch/gowin/logic.ys @@ -0,0 +1,13 @@ +read_verilog ../common/logic.v +hierarchy -top top +proc +equiv_opt -assert -map +/gowin/cells_sim.v synth_gowin # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd top # Constrain all select calls below inside the top module + +select -assert-count 1 t:LUT1 +select -assert-count 6 t:LUT2 +select -assert-count 2 t:LUT4 +select -assert-count 8 t:IBUF +select -assert-count 10 t:OBUF +select -assert-none t:LUT1 t:LUT2 t:LUT4 t:IBUF t:OBUF %% t:* %D diff --git a/tests/arch/gowin/memory.ys b/tests/arch/gowin/memory.ys new file mode 100644 index 000000000..8f88cdd7c --- /dev/null +++ b/tests/arch/gowin/memory.ys @@ -0,0 +1,18 @@ +read_verilog ../common/memory.v +hierarchy -top top +proc +memory -nomap +equiv_opt -run :prove -map +/gowin/cells_sim.v synth_gowin +memory +opt -full + +miter -equiv -flatten -make_assert -make_outputs gold gate miter +#ERROR: Called with -verify and proof did fail! +#sat -verify -prove-asserts -seq 5 -set-init-zero -show-inputs -show-outputs miter +sat -prove-asserts -seq 5 -set-init-zero -show-inputs -show-outputs miter + +design -load postopt +cd top +select -assert-count 8 t:RAM16S4 +# other logic present that is not simple +#select -assert-none t:RAM16S4 %% t:* %D diff --git a/tests/arch/gowin/mux.ys b/tests/arch/gowin/mux.ys new file mode 100644 index 000000000..4990be421 --- /dev/null +++ b/tests/arch/gowin/mux.ys @@ -0,0 +1,50 @@ +read_verilog ../common/mux.v +design -save read + +hierarchy -top mux2 +proc +equiv_opt -assert -map +/gowin/cells_sim.v synth_gowin # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd mux2 # Constrain all select calls below inside the top module +select -assert-count 1 t:LUT3 +select -assert-count 3 t:IBUF +select -assert-count 1 t:OBUF + +select -assert-none t:LUT3 t:IBUF t:OBUF %% t:* %D + +design -load read +hierarchy -top mux4 +proc +equiv_opt -assert -map +/gowin/cells_sim.v synth_gowin # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd mux4 # Constrain all select calls below inside the top module +select -assert-count 4 t:LUT4 +select -assert-count 2 t:MUX2_LUT5 +select -assert-count 1 t:MUX2_LUT6 +select -assert-count 6 t:IBUF +select -assert-count 1 t:OBUF + +select -assert-none t:LUT4 t:MUX2_LUT6 t:MUX2_LUT5 t:IBUF t:OBUF %% t:* %D + +design -load read +hierarchy -top mux8 +proc +equiv_opt -assert -map +/gowin/cells_sim.v synth_gowin # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd mux8 # Constrain all select calls below inside the top module +select -assert-count 11 t:IBUF +select -assert-count 1 t:OBUF + +select -assert-none t:LUT4 t:MUX2_LUT6 t:MUX2_LUT5 t:IBUF t:OBUF %% t:* %D + +design -load read +hierarchy -top mux16 +proc +equiv_opt -assert -map +/gowin/cells_sim.v synth_gowin # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd mux16 # Constrain all select calls below inside the top module +select -assert-count 20 t:IBUF +select -assert-count 1 t:OBUF +show + +select -assert-none t:LUT4 t:MUX2_LUT6 t:MUX2_LUT5 t:MUX2_LUT6 t:MUX2_LUT7 t:MUX2_LUT8 t:IBUF t:OBUF %% t:* %D diff --git a/tests/arch/gowin/run-test.sh b/tests/arch/gowin/run-test.sh new file mode 100755 index 000000000..bf19b887d --- /dev/null +++ b/tests/arch/gowin/run-test.sh @@ -0,0 +1,20 @@ +#!/usr/bin/env bash +set -e +{ +echo "all::" +for x in *.ys; do + echo "all:: run-$x" + echo "run-$x:" + echo " @echo 'Running $x..'" + echo " @../../../yosys -ql ${x%.ys}.log -w 'Yosys has only limited support for tri-state logic at the moment.' $x" +done +for s in *.sh; do + if [ "$s" != "run-test.sh" ]; then + echo "all:: run-$s" + echo "run-$s:" + echo " @echo 'Running $s..'" + echo " @bash $s" + fi +done +} > run-test.mk +exec ${MAKE:-make} -f run-test.mk diff --git a/tests/arch/gowin/shifter.ys b/tests/arch/gowin/shifter.ys new file mode 100644 index 000000000..b43b1e869 --- /dev/null +++ b/tests/arch/gowin/shifter.ys @@ -0,0 +1,12 @@ +read_verilog ../common/shifter.v +hierarchy -top top +proc +flatten +equiv_opt -assert -map +/gowin/cells_sim.v synth_gowin # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd top # Constrain all select calls below inside the top module + +select -assert-count 8 t:DFF +select -assert-count 2 t:IBUF +select -assert-count 8 t:OBUF +select -assert-none t:DFF t:IBUF t:OBUF %% t:* %D diff --git a/tests/arch/gowin/tribuf.ys b/tests/arch/gowin/tribuf.ys new file mode 100644 index 000000000..5855b9d97 --- /dev/null +++ b/tests/arch/gowin/tribuf.ys @@ -0,0 +1,13 @@ +read_verilog ../common/tribuf.v +hierarchy -top tristate +proc +tribuf +flatten +synth +equiv_opt -assert -map +/gowin/cells_sim.v -map +/simcells.v synth_gowin # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd tristate # Constrain all select calls below inside the top module +#Internal cell type used. Need support it. +select -assert-count 1 t:TBUF +select -assert-count 2 t:IBUF +select -assert-none t:TBUF t:IBUF %% t:* %D |