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* Merge pull request #2328 from YosysHQ/mwk/opt_dff-cleanupclairexen2020-08-201-143/+0
|\ | | | | Remove passes redundant with opt_dff
| * peepopt: Remove now-redundant dffmux pattern.Marcelina Kościelnicka2020-08-071-143/+0
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* | Merge branch 'const-func-block-var' of https://github.com/zachjs/yosys into ↵Claire Wolf2020-08-182-0/+24
|\ \ | | | | | | | | | | | | | | | zachjs-const-func-block-var Signed-off-by: Claire Wolf <claire@symbioticeda.com>
| * | Allow blocks with declarations within constant functionsZachary Snow2020-07-252-0/+24
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* | | Merge pull request #2281 from zachjs/const-realclairexen2020-08-181-0/+12
|\ \ \ | |_|/ |/| | Allow reals as constant function parameters
| * | Allow reals as constant function parametersZachary Snow2020-07-191-0/+12
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* | Merge pull request #2306 from YosysHQ/mwk/equiv_induct-undefclairexen2020-07-281-0/+35
|\ \ | | | | | | equiv_induct: Fix up assumption for $equiv cells in -undef mode.
| * | equiv_induct: Fix up assumption for $equiv cells in -undef mode.Marcelina Kościelnicka2020-07-271-0/+35
| |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Before this fix, equiv_induct only assumed that one of the following is true: - defined value of A is equal to defined value of B - A is undefined This lets through valuations where A is defined, B is undefined, and the defined (meaningless) value of B happens to match the defined value of A. Instead, tighten this up to OR of the following: - defined value of A is equal to defined value of B, and B is not undefined - A is undefined
* / Avoid generating wires for function args which are constantZachary Snow2020-07-242-0/+45
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* Revert "Revert PRs #2203 and #2244."Kamil Rakoczy2020-07-104-0/+49
| | | | This reverts commit 9c120b89ace6c111aa4677616947d18d980b9c1a.
* Revert PRs #2203 and #2244.whitequark2020-07-094-49/+0
| | | | | | | | This reverts commit 7e83a51fc96495c558a31fc3ca6c1a5ba4764f15. This reverts commit b422f2e4d0b8d5bfa97913d6b9dee488b59fc405. This reverts commit 7cb56f34b06de666935fbda315ce7c7bd45048b3. This reverts commit 6f9be939bd7653b0bdcae93a1033a086a4561b68. This reverts commit 76a34dc5f3a60c89efeaa3378ca0e2700a8aebd2.
* Add logic param and integer bad syntax testsKamil Rakoczy2020-07-063-0/+21
| | | | Signed-off-by: Kamil Rakoczy <krakoczy@antmicro.com>
* Merge pull request #2203 from antmicro/fix-grammarclairexen2020-07-011-0/+28
|\ | | | | Signed and macro grammar update
| * Add signed/unsigned testsKamil Rakoczy2020-06-261-0/+28
| | | | | | | | Signed-off-by: Kamil Rakoczy <krakoczy@antmicro.com>
* | Allow constant function calls in for loops and generate if and caseZachary Snow2020-06-292-0/+76
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* Use C++11 final/override keywords.whitequark2020-06-181-1/+1
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* Merge pull request #2077 from YosysHQ/eddie/abc9_dff_improveEddie Hung2020-06-041-1/+2
|\ | | | | abc9: -dff improvements
| * abc9_ops: -reintegrate use SigMap to remove (* init *) from $_DFF_[NP]_Eddie Hung2020-05-291-1/+2
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* | Merge pull request #2080 from YosysHQ/eddie/fix_test_warningsEddie Hung2020-06-033-4/+4
|\ \ | | | | | | tests: reduce test warnings
| * | tests: fix some test warningsEddie Hung2020-05-253-4/+4
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* / printattrs: Add test.Alberto Gonzalez2020-05-271-0/+14
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* xaiger: add testcaseEddie Hung2020-05-241-0/+13
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* abc9: preserve $_DFF_?_.Q's (* init *); rely on clean to remove itEddie Hung2020-05-141-3/+8
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* abc9: not enough to techmap_fail on (* init=1 *), hide them using $__Eddie Hung2020-05-141-2/+21
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* abc9: add flop boxes to basic $_DFF_P_ and $_DFF_N_ tooEddie Hung2020-05-141-5/+7
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* Merge pull request #2028 from zachjs/masterEddie Hung2020-05-062-0/+17
|\ | | | | verilog: allow null gen-if then block
| * verilog: allow null gen-if then blockZachary Snow2020-05-062-0/+17
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* | Merge pull request #2024 from YosysHQ/eddie/primitive_srcEddie Hung2020-05-051-0/+16
|\ \ | | | | | | verilog: set src attribute for primitives
| * | tests: add tests for primitives' srcEddie Hung2020-05-041-0/+16
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* / verilog: fix specify src attributeEddie Hung2020-05-041-0/+6
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* test: add test for #2014Eddie Hung2020-05-021-0/+12
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* Merge pull request #1973 from YosysHQ/eddie/fix1966Eddie Hung2020-04-221-1/+3
|\ | | | | tests: fix various/plugin.sh when PREFIX != /usr/local/share
| * tests: use `yosys-config --datdir` instead of hard-codedEddie Hung2020-04-221-1/+3
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* | Merge pull request #1950 from YosysHQ/eddie/design_importEddie Hung2020-04-222-5/+22
|\ \ | | | | | | design: -import to not count black/white-boxes as candidates for top
| * | design: add testEddie Hung2020-04-162-5/+22
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* | Merge pull request #1976 from YosysHQ/dave/fix-sim-constClaire Wolf2020-04-221-0/+13
|\ \ | | | | | | sim: Fix handling of constant-connected cell inputs at startup
| * | sim: Fix handling of constant-connected cell inputs at startupDavid Shah2020-04-211-0/+13
| |/ | | | | | | Signed-off-by: David Shah <dave@ds0.me>
* | hierarchy: Convert positional parameters to named.Marcelina Kościelnicka2020-04-211-0/+23
| | | | | | | | Fixes #1821.
* | Merge pull request #1851 from YosysHQ/claire/bitselwriteClaire Wolf2020-04-2113-0/+1224
|\ \ | | | | | | Improved rewrite code for writing to bit slice
| * | Remove '-ignore_unknown_cells' option from 'sat'Eddie Hung2020-04-201-6/+6
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| * | Simplify test case scriptEddie Hung2020-04-201-30/+17
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| * | Modifications of tests as per Eddie's requestdiego2020-04-2013-0/+1237
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* | | abc9: add testcase reduced from #1970Eddie Hung2020-04-201-0/+19
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* | tests: add design -delete testsEddie Hung2020-04-162-0/+18
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* | ast: Fix handling of identifiers in the global scopeDavid Shah2020-04-161-0/+18
|/ | | | Signed-off-by: David Shah <dave@ds0.me>
* tests: add testcases from #1876Eddie Hung2020-04-141-0/+60
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* tests: add a quick plugin testEddie Hung2020-04-093-0/+22
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* Add support for SystemVerilog-style `define to Verilog frontendRupert Swarbrick2020-03-274-0/+50
| | | | | | | | | | | | | | | | | | | | | | | | | | | This patch should support things like `define foo(a, b = 3, c) a+b+c `foo(1, ,2) which will evaluate to 1+3+2. It also spots mistakes like `foo(1) (the 3rd argument doesn't have a default value, so a call site is required to set it). Most of the patch is a simple parser for the format in preproc.cc, but I've also taken the opportunity to wrap up the "name -> definition" map in a type, rather than use multiple std::map's. Since this type needs to be visible to code that touches defines, I've pulled it (and the frontend_verilog_preproc declaration) out into a new file at frontends/verilog/preproc.h and included that where necessary. Finally, the patch adds a few tests in tests/various to check that we are parsing everything correctly.
* Add test for abc9+mince issueDavid Shah2020-03-201-0/+17
| | | | Signed-off-by: David Shah <dave@ds0.me>
* fsm_extract: Initialize celltypes with full design.Marcin Kościelnicki2020-03-191-0/+33
| | | | Fixes #1781.
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