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* autotest.sh to define _AUTOTB when test_autotbEddie Hung2019-06-281-1/+1
* tests: use optional ABCEXTERNAL when specifiedGabriel L. Somlo2019-06-271-2/+5
* Add defvalue test, minor autotest fixes for .sv filesClifford Wolf2019-06-191-14/+15
* Use ABC to convert from AIGER to VerilogEddie Hung2019-06-071-2/+3
* SystemVerilog support for implicit named port connectionstux32019-06-061-2/+13
* iverilog with simcells.v as wellEddie Hung2019-05-031-1/+2
* Fix testsClifford Wolf2019-04-211-2/+2
* Merge https://github.com/YosysHQ/yosys into read_aigerEddie Hung2019-03-191-7/+5
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| * Hotfix for "make test"Clifford Wolf2019-02-281-1/+1
| * Add "write_verilog -siminit"Clifford Wolf2019-02-281-1/+1
| * Fix FIRRTL to Verilog process instance subfield assignment.Jim Lawson2019-02-251-1/+1
| * Revert "Add -B option to autotest.sh to append to backend_opts"Eddie Hung2019-02-211-4/+2
| * Merge https://github.com/YosysHQ/yosys into dff_initEddie Hung2019-02-172-7/+42
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* | | One more merge conflictEddie Hung2019-02-171-6/+1
* | | Merge https://github.com/YosysHQ/yosys into read_aigerEddie Hung2019-02-172-7/+46
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| * | Update cells supported for verilog to FIRRTL conversion.Jim Lawson2019-02-152-7/+42
* | | Support and differentiate between ASCII and binary AIG testingEddie Hung2019-02-081-1/+1
* | | Merge branch 'dff_init' of https://github.com/eddiehung/yosys into xaigEddie Hung2019-02-061-2/+4
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| * | Add -B option to autotest.sh to append to backend_optsEddie Hung2019-02-061-2/+4
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* | Revert most of autotest.sh; for non *.v use Yosys to translateEddie Hung2019-02-061-7/+9
* | Add testsEddie Hung2019-02-041-8/+13
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* Fixed typo (sikp -> skip)Udi Finkelstein2018-06-051-1/+1
* autotest.sh: Change from /bin/bash to /usr/bin/env bashJohnny Sorocil2018-05-061-1/+1
* Merge branch 'master' of https://github.com/brouhaha/yosysClifford Wolf2016-09-231-1/+6
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| * Add optional SEED=n command line option to Makefile, and -S n command line op...Eric Smith2016-09-221-1/+6
* | Added autotest.sh -IClifford Wolf2016-09-201-16/+19
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* Fix for modules with big interfaces.Kaj Tuomi2016-09-131-2/+2
* Added "test_autotb -seed" (and "autotest.sh -S")Clifford Wolf2016-08-061-2/+4
* Fixed autotest.sh handling of `timescaleClifford Wolf2016-07-021-14/+10
* Improvements and fixes in autotest.sh script and test_autotbClifford Wolf2016-05-201-6/+6
* Fix for Modelsim transcript line warp issue #164Kaj Tuomi2016-05-191-4/+4
* Optionally use ${CC} when compiling test utils.Sergey Kvachonok2016-03-251-1/+1
* Switched to Python 3Clifford Wolf2015-08-221-4/+1
* Another block of spelling fixesLarry Doolittle2015-08-141-1/+1
* Spell check (by Larry Doolittle)Clifford Wolf2015-08-141-1/+1
* Some test related fixesClifford Wolf2015-02-121-1/+1
* Refactoring of memory_bram and xilinx bramsClifford Wolf2015-01-181-0/+2
* Tiny fix in vcdcd.plClifford Wolf2015-01-131-2/+2
* Added "synth" commandClifford Wolf2014-09-141-2/+2
* Fixed autotest for non-basename argumentsClifford Wolf2014-09-061-0/+3
* Added autotest -e (do not use -noexpr on write_verilog)Clifford Wolf2014-08-301-2/+4
* Added "wreduce" to some of the standard test benchesClifford Wolf2014-08-031-1/+1
* Added "test_autotb -n <num_iter>" optionClifford Wolf2014-08-011-2/+5
* Added "make -j{N}" support to "make test"Clifford Wolf2014-07-302-6/+23
* Renamed "write_autotest" to "test_autotb" and moved to passes/tests/Clifford Wolf2014-07-291-1/+1
* Added "opt_const -fine" and "opt_reduce -fine"Clifford Wolf2014-07-211-1/+1
* Also simulate unmapped memories in "make test"Clifford Wolf2014-07-171-1/+1
* Added note to "make test": use git checkout of iverilogClifford Wolf2014-07-161-2/+11
* Progress in Verific bindingsClifford Wolf2014-03-171-1/+9
* Progress in Verific bindingsClifford Wolf2014-03-141-5/+9
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