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| author | Clifford Wolf <clifford@clifford.at> | 2016-05-20 16:58:02 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2016-05-20 16:58:02 +0200 |
| commit | 1e227caf720bc5870ea9244e6b5657cf9c9717ab (patch) | |
| tree | 5a2441f68187a13f67af72ac3110f02f6e05faa1 /tests/tools | |
| parent | 884ec967871dede8d5ad6fb730a405e421a18dbe (diff) | |
| download | yosys-1e227caf720bc5870ea9244e6b5657cf9c9717ab.tar.gz yosys-1e227caf720bc5870ea9244e6b5657cf9c9717ab.tar.bz2 yosys-1e227caf720bc5870ea9244e6b5657cf9c9717ab.zip | |
Improvements and fixes in autotest.sh script and test_autotb
Diffstat (limited to 'tests/tools')
| -rwxr-xr-x | tests/tools/autotest.sh | 12 |
1 files changed, 6 insertions, 6 deletions
diff --git a/tests/tools/autotest.sh b/tests/tools/autotest.sh index feaadb1a1..bc43fb885 100755 --- a/tests/tools/autotest.sh +++ b/tests/tools/autotest.sh @@ -16,7 +16,7 @@ toolsdir="$(cd $(dirname $0); pwd)" warn_iverilog_git=false if [ ! -f $toolsdir/cmp_tbdata -o $toolsdir/cmp_tbdata.c -nt $toolsdir/cmp_tbdata ]; then - ( set -ex; ${CC:-gcc} -Wall -o $toolsdir/cmp_tbdata $toolsdir/cmp_tbdata.c; ) || exit 1 + ( set -ex; ${CC:-gcc} -Wall -o $toolsdir/cmp_tbdata $toolsdir/cmp_tbdata.c; ) || exit 1 fi while getopts xmGl:wkjvref:s:p:n: opt; do @@ -65,18 +65,18 @@ compile_and_run() { if $use_modelsim; then altver=$( ls -v /opt/altera/ | grep '^[0-9]' | tail -n1; ) /opt/altera/$altver/modelsim_ase/bin/vlib work - /opt/altera/$altver/modelsim_ase/bin/vlog +define+dmp_name=\"$output\" "$@" + /opt/altera/$altver/modelsim_ase/bin/vlog +define+outfile=\"$output\" "$@" /opt/altera/$altver/modelsim_ase/bin/vsim -c -do 'run -all; exit;' testbench elif $use_xsim; then ( set +x files=( "$@" ) xilver=$( ls -v /opt/Xilinx/Vivado/ | grep '^[0-9]' | tail -n1; ) - /opt/Xilinx/Vivado/$xilver/bin/xvlog "${files[@]}" - /opt/Xilinx/Vivado/$xilver/bin/xelab -R work.testbench | grep '#OUT#' > "$output" + /opt/Xilinx/Vivado/$xilver/bin/xvlog -d outfile=\"$output\" "${files[@]}" + /opt/Xilinx/Vivado/$xilver/bin/xelab -R work.testbench ) else - iverilog -Ddmp_name=\"$output\" -s testbench -o "$exe" "$@" + iverilog -Doutfile=\"$output\" -s testbench -o "$exe" "$@" vvp -n "$exe" fi } @@ -116,7 +116,7 @@ do fi if $genvcd; then sed -i 's,// \$dump,$dump,g' ${bn}_tb.v; fi create_ref $fn ${bn}_ref - compile_and_run ${bn}_tb_ref ${bn}_out_ref ${bn}_tb.v ${bn}_ref.v $libs + compile_and_run ${bn}_tb_ref ${bn}_out_ref ${bn}_tb.v ${bn}_ref.v $libs if $genvcd; then mv testbench.vcd ${bn}_ref.vcd; fi test_count=0 |