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| author | Eddie Hung <eddie@fpgeh.com> | 2019-06-07 11:06:57 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-06-07 11:06:57 -0700 |
| commit | abc40924ed5dc4aba91c7f1e83ca90f54e9eb455 (patch) | |
| tree | 937476067fef6b0931a63a83ef73c0add3eb0d47 /tests/tools | |
| parent | ebe29b66593414d0317879359d1f1d1f61a9ecc4 (diff) | |
| download | yosys-abc40924ed5dc4aba91c7f1e83ca90f54e9eb455.tar.gz yosys-abc40924ed5dc4aba91c7f1e83ca90f54e9eb455.tar.bz2 yosys-abc40924ed5dc4aba91c7f1e83ca90f54e9eb455.zip | |
Use ABC to convert from AIGER to Verilog
Diffstat (limited to 'tests/tools')
| -rwxr-xr-x | tests/tools/autotest.sh | 5 |
1 files changed, 3 insertions, 2 deletions
diff --git a/tests/tools/autotest.sh b/tests/tools/autotest.sh index 0a511f29c..23964a751 100755 --- a/tests/tools/autotest.sh +++ b/tests/tools/autotest.sh @@ -146,9 +146,10 @@ do rm -f ${bn}_ref.fir if [[ "$ext" == "v" ]]; then egrep -v '^\s*`timescale' ../$fn > ${bn}_ref.${ext} + elif [[ "$ext" == "aig" ]] || [[ "$ext" == "aag" ]]; then + "$toolsdir"/../../yosys-abc -c "read_aiger ../${fn}; write ${bn}_ref.v" else - "$toolsdir"/../../yosys -f "$frontend $include_opts" -b "verilog" -o ${bn}_ref.v ../${fn} - frontend="verilog -noblackbox" + cp ../${fn} ${bn}_ref.${ext} fi if [ ! -f ../${bn}_tb.v ]; then |