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* tests: Centralize test collection and Makefile generationXiretza2020-09-213-21/+5
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* flatten, techmap: don't canonicalize tpl driven bits via sigmap.whitequark2020-08-261-0/+11
| | | | | | | | | | | | | | | | | | | | For connection `assign a = b;`, `sigmap(a)` returns `b`. This is exactly the opposite of the desired canonicalization for driven bits. Consider the following code: module foo(inout a, b); assign a = b; endmodule module bar(output c); foo f(c, 1'b0); endmodule Before this commit, the inout ports would be swapped after flattening (and cause a crash while attempting to drive a constant value). This issue was introduced in 9f772eb9. Fixes #2183.
* Merge pull request #2347 from YosysHQ/mwk/techmap-shift-fixesclairexen2020-08-201-12/+0
|\ | | | | techmap/shift_shiftx: Remove the "shiftx2mux" special path.
| * techmap/shift_shiftx: Remove the "shiftx2mux" special path.Marcelina Kościelnicka2020-08-201-12/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Our techmap rules for $shift and $shiftx cells contained a special path that aimed to decompose the shift LSB-first instead of MSB-first in select cases that come up in pmux lowering. This path was needlessly overcomplicated and contained bugs. Instead of doing that, just switch over the main path to iterate LSB-first (except for the specially-handled MSB for signed shifts and overflow handling). This also makes the code consistent with shl/shr/sshl/sshr cells, which are already decomposed LSB-first. Fixes #2346.
* | Merge pull request #2333 from YosysHQ/mwk/peepopt-shiftmul-signedclairexen2020-08-201-0/+11
|\ \ | | | | | | peeopt.shiftmul: Add a signedness check.
| * | peeopt.shiftmul: Add a signedness check.Marcelina Kościelnicka2020-08-051-0/+11
| |/ | | | | | | Fixes #2332.
* | Merge pull request #2328 from YosysHQ/mwk/opt_dff-cleanupclairexen2020-08-201-50/+0
|\ \ | | | | | | Remove passes redundant with opt_dff
| * | Remove now-redundant dff2dffs pass.Marcelina Kościelnicka2020-08-071-50/+0
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* / techmap.CONSTMAP: Handle outputs before inputs.Marcelina Kościelnicka2020-08-051-0/+15
|/ | | | Fixes #2321.
* Add dffunmap pass.Marcelina Kościelnicka2020-07-311-0/+100
| | | | | To be used with backends that cannot deal with fancy FF types (like blif or smt).
* zinit: Refactor to use FfInitVals.Marcelina Kościelnicka2020-07-241-2/+2
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* clk2fflogic: Support all FF types.Marcelina Kościelnicka2020-07-2418-123/+123
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* techmap: Add _TECHMAP_CELLNAME_ special parameter.Marcelina Kościelnicka2020-07-211-0/+41
| | | | | | | This parameter will resolve to the name of the cell being mapped. The first user of this parameter will be synth_intel_alm's Quartus output, which requires a unique (and preferably descriptive) name passed as a cell parameter for the memory cells.
* dfflibmap: Refactor to use dfflegalize internally.Marcelina Kościelnicka2020-07-093-0/+135
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* clkbufmap: improve input pad handling.Marcelina Kościelnicka2020-07-091-0/+79
| | | | | | - allow inserting only the input pad cell - do not insert the usual buffer if the input pad already acts as a buffer
* clk2fflogic: Consistently treat async control signals as negative hold.Marcelina Kościelnicka2020-07-097-31/+31
| | | | | | | This fixes some dfflegalize equivalence checks, and breaks others — and I strongly suspect the others are due to bad support for multiple async inputs in `proc` (in particular, lack of proper support for dlatchsr and sketchy circuits on dffsr control inputs).
* dfflegalize: Add special support for const-D latches.Marcelina Kościelnicka2020-07-091-0/+53
| | | | | | Those can be created by `opt_dff` when optimizing `$adff` with const clock, or with D == Q. Make dfflegalize do the opposite transform when such dlatches would be otherwise unimplementable.
* dfflegalize: Add tests.Marcelina Kościelnicka2020-07-0117-0/+2957
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* Update dff2dffe, dff2dffs, zinit to new FF types.Marcelina Kościelnicka2020-06-232-76/+76
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* tests: zinit for new typesEddie Hung2020-04-141-2/+96
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* dffinit: Avoid setting init parameter to zero-length value.Marcelina Kościelnicka2020-04-141-0/+25
| | | | Fixes #1704.
* zinit: resolve one more comment by @mwkmwkmwkEddie Hung2020-04-131-1/+8
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* zinit: fix review comments from @mwkmwkmwkEddie Hung2020-04-131-4/+31
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* tests: zinit on $adffEddie Hung2020-04-131-19/+18
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* Add testcase for $_DFF_[NP][NP][01]_Eddie Hung2020-04-131-0/+24
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* Merge pull request #1648 from YosysHQ/eddie/cmp2lcuEddie Hung2020-04-031-0/+52
|\ | | | | "techmap -map +/cmp2lcu.v" for decomposing arithmetic compares to $lcu
| * +/cmp2lcu.v to work efficiently for fully/partially constant inputsEddie Hung2020-04-031-3/+31
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| * Refactor +/cmp2lcu.v into recursive techmapEddie Hung2020-04-031-1/+1
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| * techmap +/cmp2lcu.v for decomposing arithmetic compares to $lcuEddie Hung2020-04-031-0/+24
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* | iopadmap: Fix z assignment to inout portMarcin Kościelnicki2020-04-021-1/+9
|/ | | | Fixes #1841.
* techmap: Fix cell names with _TECHMAP_REPLACE_.*Marcin Kościelnicki2020-03-231-0/+18
| | | | Fixes #1804.
* iopadmap: Look harder for already-present buffers. (#1731)Marcelina Kościelnicka2020-03-021-2/+21
| | | | | iopadmap: Look harder for already-present buffers. Fixes #1720.
* Fine tune #1699 testsEddie Hung2020-02-131-14/+14
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* iopadmap: move \init attributes from outpad output to its inputEddie Hung2020-02-131-0/+37
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* shiftx2mux: fix select out of boundsEddie Hung2020-02-052-1/+12
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* Merge remote-tracking branch 'origin/master' into eddie/shiftx2muxEddie Hung2020-02-051-0/+29
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| * Merge remote-tracking branch 'origin/master' into eddie/abc9_refactorEddie Hung2020-01-151-0/+13
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| * | abc9: respect (* keep *) on cellsEddie Hung2020-01-131-0/+15
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| * | write_xaiger: add support and test for (* keep *) on wiresEddie Hung2020-01-131-0/+13
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* | | Move from +/shiftx2mux.v into +/techmap.v; cleanupEddie Hung2020-01-211-4/+4
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* | | New techmap +/shiftx2mux.v which decomposes LSB first; better for ABCEddie Hung2020-01-211-0/+110
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* | abc9: aAdd test to check $_NOT_s are absorbedEddie Hung2020-01-151-0/+12
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* Add abc9 sanity testEddie Hung2020-01-091-0/+40
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* iopadmap: Emit tristate buffers with const OE for some edge cases.Marcin Kościelnicki2019-12-251-0/+23
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* iopadmap: Refactor and fix tristate buffer mapping. (#1527)Marcin Kościelnicki2019-12-041-0/+99
| | | | | | | The previous code for rerouting wires when inserting tristate buffers was overcomplicated and didn't handle all cases correctly (in particular, only cell connections were rewired — internal connections were not).
* clkbufmap: Add support for inverters in clock path.Marcin Kościelnicki2019-11-251-5/+16
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* Merge pull request #1422 from YosysHQ/eddie/aigmap_selectClifford Wolf2019-10-031-0/+10
|\ | | | | Add -select option to aigmap
| * Add quick testEddie Hung2019-09-301-0/+10
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* | Extend test with renaming cells with prefix tooEddie Hung2019-10-021-0/+2
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* | Add testEddie Hung2019-09-301-0/+16
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