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* Fix FIRRTL to Verilog process instance subfield assignment.Jim Lawson2019-02-251-1/+0
| | | | | | Don't emit subfield assignments: bits(x, y, z) <= ... - but instead, add them to the reverse-wire-map where they'll be treated at the end of the module. Enable tests which were disabled due to incorrect treatment of subfields. Assume the `$firrtl2verilog` variable contains any additional switches to control verilog generation (i.e. `--no-dedup -X mverilog`)
* Fix handling of defparam for when default_nettype is noneClifford Wolf2019-02-241-0/+2
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Merge https://github.com/YosysHQ/yosys into dff_initEddie Hung2019-02-171-0/+26
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| * Update cells supported for verilog to FIRRTL conversion.Jim Lawson2019-02-151-0/+26
| | | | | | | | | | | | | | | | | | | | | | | | | | Issue warning messages for missing parameterized modules and attempts to set initial values. Replace simple "if (cell-type)" with "else if" chain. Fix FIRRTL shift handling. Add support for parameterized modules, $shift, $shiftx. Handle default output file. Deal with no top module. Automatically run pmuxtree pass. Allow EXTRA_FLAGS and SEED parameters to be set in the environment for tests/tools/autotest.mk. Support FIRRTL regression testing in tests/tools/autotest.sh Add xfirrtl files to test directories to exclude files from FIRRTL regression tests that are known to fail.
* | Extend testcaseEddie Hung2019-02-061-2/+34
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* | Add testcaseEddie Hung2019-02-061-0/+10
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* Basic test for checking correct synthesis of SystemVerilog interfacesRuben Undheim2018-10-181-90/+0
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* Support for 'modports' for System Verilog interfacesRuben Undheim2018-10-121-3/+17
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* Synthesis support for SystemVerilog interfacesRuben Undheim2018-10-121-0/+76
| | | | This time doing the changes mostly in AST before RTLIL generation
* Fix tests/simple/specify.vClifford Wolf2018-03-271-2/+2
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* First draft of Verilog parser support for specify blocks and parameters.Udi Finkelstein2018-03-271-0/+31
| | | | | The only functionality of this code at the moment is to accept correct specify syntax and ignore it. No part of the specify block is added to the AST
* Allow $size and $bits in verilog mode, actually check test caseClifford Wolf2017-09-291-32/+0
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* $size() now works correctly for all cases!Udi Finkelstein2017-09-261-5/+11
| | | | It seems the issues was that AST_MULTIRANGE is converted into a multirange_dimensions[] array on the AST_MEMORY node directly.
* $size() seems to work now with or without the optional parameter.Udi Finkelstein2017-09-261-8/+18
| | | | Multidimensional arrays still don't work. I suspect the problem is that the array is flattened into a 1D array before $size() is evaluated.
* Added $bits() for memories as well.Udi Finkelstein2017-09-261-6/+5
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* $size() now works with memories as well!Udi Finkelstein2017-09-261-2/+4
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* Add $size() function. At the moment it works only on expressions, not on ↵Udi Finkelstein2017-09-261-0/+15
| | | | memories.
* Squelch trailing whitespaceLarry Doolittle2017-04-121-1/+1
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* Fixed typo in tests/simple/arraycells.vClifford Wolf2017-01-041-1/+1
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* Added support for hierarchical defparamsClifford Wolf2016-11-151-0/+23
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* Add optional SEED=n command line option to Makefile, and -S n command line ↵Eric Smith2016-09-221-1/+12
| | | | option to test scripts, for deterministic regression tests.
* Fixed bug with memories that do not have a down-to-zero data widthClifford Wolf2016-08-221-0/+30
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* Added another mem2reg test caseClifford Wolf2016-08-211-0/+11
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* Another bugfix in mem2reg codeClifford Wolf2016-08-211-0/+22
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* Fixed mem assignment in left-hand-side concatenationClifford Wolf2016-07-081-0/+13
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* Fixed init issue in mem2reg_test2 test caseClifford Wolf2016-06-171-2/+6
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* Added opt_expr support for div/mod by power-of-twoClifford Wolf2016-05-291-0/+27
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* Bugfix and improvements in memory_shareClifford Wolf2016-04-211-0/+21
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* Added tests/simple/graphtest.vClifford Wolf2015-11-301-0/+34
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* More bugfixes in handling of parameters in tasks and functionsClifford Wolf2015-11-121-1/+12
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* Fixed handling of parameters and localparams in functionsClifford Wolf2015-11-111-1/+30
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* Bugfix in memory_dffClifford Wolf2015-10-311-0/+15
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* Improvements in wreduceClifford Wolf2015-10-311-0/+9
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* Another block of spelling fixesLarry Doolittle2015-08-144-6/+6
| | | | Smaller this time
* Fixed trailing whitespacesClifford Wolf2015-07-023-6/+6
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* Various fixes for memories with offsetsClifford Wolf2015-02-141-2/+2
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* Added $meminit support to "memory" commandClifford Wolf2015-02-141-15/+8
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* Added $meminit test caseClifford Wolf2015-02-141-0/+30
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* improvements in muxtree/select_leaves testClifford Wolf2015-01-181-2/+5
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* Improvements in opt_muxtreeClifford Wolf2015-01-181-0/+8
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* Added support for task and function args in parenthesesClifford Wolf2014-10-271-1/+35
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* Added multi-dim memory test (requires iverilog git head)Clifford Wolf2014-08-121-0/+11
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* Improved scope resolution of local regs in Verilog+AST frontendClifford Wolf2014-08-051-0/+63
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* Fixed AST handling of variables declared inside a functions main blockClifford Wolf2014-08-051-0/+13
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* Added "make -j{N}" support to "make test"Clifford Wolf2014-07-301-1/+1
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* Added support for "upto" wires to Verilog front- and back-endClifford Wolf2014-07-281-0/+57
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* Renamed some of the test cases in tests/simple to avoid name collisionsClifford Wolf2014-07-2515-30/+30
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* Implemented dynamic bit-/part-select for memory writesClifford Wolf2014-07-171-1/+40
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* Added support for bit/part select to mem2reg rewriterClifford Wolf2014-07-171-0/+21
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* Added support for constant bit- or part-select for memory writesClifford Wolf2014-07-171-0/+20
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