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* iopadmap: Add native support for negative-polarity output enable.Marcelina Kościelnicka2021-11-092-3/+3
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* FfData: some refactoring.Marcelina Kościelnicka2021-10-071-2/+3
| | | | | | | | | | - FfData now keeps track of the module and underlying cell, if any (so calling emit on FfData created from a cell will replace the existing cell) - FfData implementation is split off to its own .cc file for faster compilation - the "flip FF data sense by inserting inverters in front and after" functionality that zinit uses is moved onto FfData class and beefed up to have dffsr support, to support more use cases
* abc9: replace cell type/parameters if derived type already processed (#2991)Eddie Hung2021-09-091-0/+7
| | | | | | | | | | | * Add close bracket * Add testcase * Replace cell type/param if in unmap_design * Improve abc9_box error message too * Update comment as per review
* Gowin: deal with active-low tristate (#2971)Pepijn de Vos2021-08-201-1/+2
| | | | | | | | | * deal with active-low tristate * remove empty port * update sim models * add expected lut1 to tests
* test/arch/{ecp5,ice40}/memories.ys: Use read_verilog -defer.Marcelina Kościelnicka2021-08-112-78/+156
| | | | | | | | | | These parts keep rereading a Verilog module, then using chparam to test it with various parameter combinations. Since the default parameters are on the large side, this spends a lot of time needlessly elaborating the default parametrization that will then be discarded. Fix it with -deref and manual hierarchy call. Shaves 30s off the test time on my machine.
* Add v2 memory cells.Marcelina Kościelnicka2021-08-112-25/+25
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* opt_lut: Allow more than one -dlogic per cell type.Marcelina Kościelnicka2021-07-291-0/+24
| | | | Fixes #2061.
* Fix files with CRLF line endingsClaire Xenia Wolf2021-06-093-73/+73
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* memory_bram: Reuse extract_rdff helper for make_outreg.Marcelina Kościelnicka2021-05-254-17/+14
| | | | | Also properly skip read ports with init value or reset when not making use of make_outreg. Proper support for matching those will land later.
* intel_alm: Fix illegal carry chainsgatecat2021-05-152-4/+4
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* intel_alm: Add global buffer insertiongatecat2021-05-1513-41/+41
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* intel_alm: Add IO buffer insertiongatecat2021-05-1513-39/+39
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* Add default assignments to SB_LUT4Claire Xenia Wolf2021-04-201-1/+1
| | | | Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
* quicklogic: ABC9 synthesisLofty2021-04-176-17/+17
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* quicklogic: Add .gitignore file for test outputs.Marcelina Kościelnicka2021-03-231-0/+4
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* quicklogic: PolarPro 3 supportLofty2021-03-1810-0/+262
| | | | | | | | Co-authored-by: Grzegorz Latosiński <glatosinski@antmicro.com> Co-authored-by: Maciej Kurc <mkurc@antmicro.com> Co-authored-by: Tarachand Pagarani <tpagarani@quicklogic.com> Co-authored-by: Lalit Sharma <lsharma@quicklogic.com> Co-authored-by: kkumar23 <kkumar@quicklogic.com>
* ast: Use better parameter serialization for paramod names.Marcelina Kościelnicka2021-03-181-3/+3
| | | | | | | | | | | | Calling log_signal is problematic for several reasons: - with recent changes, empty string is serialized as { }, which violates the "no spaces in IdString" rule - the type (plain / real / signed / string) is dropped, wrongly conflating functionally different values and potentially introducing a subtle elaboration bug Instead, use a custom simple serialization scheme.
* Blackbox all whiteboxes after synthesisgatecat2021-03-171-9/+9
| | | | | | | This prevents issues like processes in whiteboxes triggering an error in the JSON backend. Signed-off-by: gatecat <gatecat@ds0.me>
* machxo2: Switch to LUT4 sim model which propagates less undefined/don't care ↵William D. Jones2021-02-231-1/+1
| | | | values.
* machxo2: Update tribuf test to reflect active-low OE.William D. Jones2021-02-231-1/+2
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* machxo2: Add believed-to-be-correct tribuf test.William D. Jones2021-02-231-0/+9
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* machxo2: Add passing fsm, mux, and shifter tests.William D. Jones2021-02-233-0/+65
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* machxo2: Add add_sub test. Fix tests to include FACADE_IO primitives.William D. Jones2021-02-233-3/+11
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* machxo2: Add dffe test.William D. Jones2021-02-231-0/+9
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* machxo2: Add dff.ys test, fix another cells_map.v typo.William D. Jones2021-02-231-0/+10
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* machxo2: Add test/arch/machxo2 directory (test does not pass).William D. Jones2021-02-233-0/+14
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* xilinx_dffopt: Don't crash on missing IS_*_INVERTED.Marcelina Kościelnicka2021-01-272-1/+48
| | | | | | | | The presence of IS_*_INVERTED on FD* cells follows Vivado, which apparently has been decided by a dice roll. Just assume false if the parameter doesn't exist. Fixes #2559.
* nexus: DSP inference supportDavid Shah2020-11-201-12/+34
| | | | Signed-off-by: David Shah <dave@ds0.me>
* Update nexus arch tests to new harnessXiretza2020-10-291-19/+3
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* xilinx: Fix attributes_test.ysMarcelina Kościelnicka2020-10-241-4/+2
| | | | | | | | | | This test pretty much passes by accident — the `prep` command runs memory_collect without memory_dff first, which prevents merging read register into the memory, and thus blocks block RAM inference for a reason completely unrelated to the attribute. The attribute setting didn't actually work because it was set on the containing module instead of the actual memory.
* memory_dff: Fix needlessly duplicating enable bits.Marcelina Kościelnicka2020-10-221-0/+24
| | | | | | | | | When the register being merged into the EN signal happens to be a $sdff, the current code creates a new $mux for every bit, even if they happen to be identical (as is usually the case), preventing proper grouping further down the flow. Fix this by adding a simple cache. Fixes #2409.
* Merge pull request #2397 from daveshah1/nexusMiodrag Milanović2020-10-1915-0/+298
|\ | | | | synth_nexus: Initial implementation
| * synth_nexus: Initial implementationDavid Shah2020-10-1515-0/+298
| | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
* | Merge pull request #2380 from Xiretza/parallel-testsclairexen2020-10-017-133/+21
|\ \ | |/ |/| Clean up and parallelize testsuite
| * tests: Centralize test collection and Makefile generationXiretza2020-09-217-133/+21
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* | xilinx: do not make DSP48E1 a whitebox for ABC9 by default (#2325)Eddie Hung2020-09-231-0/+37
|/ | | | | | | | | | | * xilinx: eliminate SCCs from DSP48E1 model * xilinx: add SCC test for DSP48E1 * Update techlibs/xilinx/cells_sim.v * xilinx: Gate DSP48E1 being a whitebox behind ALLOW_WHITEBOX_DSP48E1 Have a test that checks it works through ABC9 when enabled
* intel_alm: Add multiply signedness to cellsDan Ravensloft2020-08-262-6/+44
| | | | | | Quartus assumes unsigned multiplication by default, breaking signed multiplies, so add an input signedness parameter to the MISTRAL_MUL* cells to propagate to Quartus' <family>_mac cells.
* techmap/shift_shiftx: Remove the "shiftx2mux" special path.Marcelina Kościelnicka2020-08-201-2/+3
| | | | | | | | | | | | | | Our techmap rules for $shift and $shiftx cells contained a special path that aimed to decompose the shift LSB-first instead of MSB-first in select cases that come up in pmux lowering. This path was needlessly overcomplicated and contained bugs. Instead of doing that, just switch over the main path to iterate LSB-first (except for the specially-handled MSB for signed shifts and overflow handling). This also makes the code consistent with shl/shr/sshl/sshr cells, which are already decomposed LSB-first. Fixes #2346.
* Replace opt_rmdff with opt_dff.Marcelina Kościelnicka2020-08-077-31/+28
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* opt_expr: Remove -clkinv option, make it the default.Marcelina Kościelnicka2020-07-311-2/+1
| | | | | Adds -noclkinv option just in case the old behavior was actually useful to someone.
* synth_ice40: Use opt_dff.Marcelina Kościelnicka2020-07-301-1/+1
| | | | | | | | | The main part is converting ice40_dsp to recognize the new FF types created in opt_dff instead of trying to recognize the mux patterns on its own. The fsm call has been moved upwards because the passes cannot deal with $dffe/$sdff*, and other optimizations don't help it much anyway.
* synth_xilinx: Use opt_dff.Marcelina Kościelnicka2020-07-301-9/+7
| | | | | | | | | The main part is converting xilinx_dsp to recognize the new FF types created in opt_dff instead of trying to recognize the patterns on its own. The fsm call has been moved upwards because the passes cannot deal with $dffe/$sdff*, and other optimizations don't help it much anyway.
* intel_alm: direct M10K instantiationDan Ravensloft2020-07-271-0/+6
| | | | This reverts commit a3a90f6377f251d3b6c5898eb1543f8832493bb8.
* intel_alm: increase abc9 -WDan Ravensloft2020-07-261-6/+6
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* satgen: Add support for dffe, sdff, sdffe, sdffce cells.Marcelina Kościelnicka2020-07-241-2/+0
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* intel_alm: add additional ABC9 timingsDan Ravensloft2020-07-231-6/+4
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* Merge pull request #2238 from YosysHQ/mwk/dfflegalize-anlogicMiodrag Milanović2020-07-161-12/+14
|\ | | | | anlogic: Use dfflegalize.
| * anlogic: Use dfflegalize.Marcelina Kościelnicka2020-07-141-12/+14
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* | Revert "intel_alm: direct M10K instantiation"Lofty2020-07-131-6/+0
| | | | | | | | This reverts commit 09ecb9b2cf3ab76841d30712bf70dafc6d47ef67.
* | xilinx: Fix srl regression.Marcelina Kościelnicka2020-07-121-0/+41
| | | | | | | | | | | | | | Of standard yosys cells, xilinx_srl only works on $_DFF_?_ and $_DFFE_?P_, which get upgraded to $_SDFFE_?P?P_ by dfflegalize at the point where xilinx_srl is called for non-abc9. Fix this by running ff_map.v first, resulting in FDRE cells, which are handled correctly.
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