iCE40/yosys - [no description]

	Commit message (Expand)	Author	Age	Files	Lines
*	memory_bram: Reuse extract_rdff helper for make_outreg.	Marcelina Kościelnicka	2021-05-25	1	-6/+4
*	intel_alm: Fix illegal carry chains	gatecat	2021-05-15	2	-4/+4
*	intel_alm: Add global buffer insertion	gatecat	2021-05-15	13	-41/+41
*	intel_alm: Add IO buffer insertion	gatecat	2021-05-15	13	-39/+39
*	tests: Centralize test collection and Makefile generation	Xiretza	2020-09-21	1	-19/+3
*	intel_alm: Add multiply signedness to cells	Dan Ravensloft	2020-08-26	1	-3/+40
*	techmap/shift_shiftx: Remove the "shiftx2mux" special path.	Marcelina Kościelnicka	2020-08-20	1	-2/+3
*	Replace opt_rmdff with opt_dff.	Marcelina Kościelnicka	2020-08-07	2	-11/+11
*	intel_alm: direct M10K instantiation	Dan Ravensloft	2020-07-27	1	-0/+6
*	intel_alm: increase abc9 -W	Dan Ravensloft	2020-07-26	1	-6/+6
*	intel_alm: add additional ABC9 timings	Dan Ravensloft	2020-07-23	1	-6/+4
*	Revert "intel_alm: direct M10K instantiation"	Lofty	2020-07-13	1	-6/+0
*	intel_alm: direct M10K instantiation	Dan Ravensloft	2020-07-05	1	-0/+6
*	intel_alm: add Cyclone 10 GX tests	Dan Ravensloft	2020-07-05	11	-2/+236
*	intel_alm: DSP inference	Dan Ravensloft	2020-07-05	1	-0/+23
*	synth_intel_alm: Use dfflegalize.	Marcelina Kościelnicka	2020-07-04	1	-1/+1
*	Improve MISTRAL_FF specify rules	Dan Ravensloft	2020-07-04	1	-1/+2
*	tests: update fsm.ys resource count	Eddie Hung	2020-07-04	1	-4/+4
*	intel_alm: fix DFFE matching	Dan Ravensloft	2020-06-11	2	-4/+4
*	Add missing .gitignore file	Claire Wolf	2020-06-04	1	-0/+2
*	intel_alm: direct LUTRAM cell instantiation	Dan Ravensloft	2020-05-07	1	-0/+20
*	intel_alm: work around a Quartus ICE	Dan Ravensloft	2020-04-23	1	-0/+12
*	synth_intel_alm: alternative synthesis for Intel FPGAs	Dan Ravensloft	2020-04-15	10	-0/+208