iCE40/yosys - [no description]

	Commit message (Collapse)	Author	Age	Files	Lines
*	Gowin: deal with active-low tristate (#2971)	Pepijn de Vos	2021-08-20	1	-1/+2
\| \| \| \| \| \| \| \| \|	* deal with active-low tristate * remove empty port * update sim models * add expected lut1 to tests
*	tests: Centralize test collection and Makefile generation	Xiretza	2020-09-21	1	-19/+3
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*	Replace opt_rmdff with opt_dff.	Marcelina Kościelnicka	2020-08-07	1	-9/+10
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*	gowin: Use dfflegalize.	Marcelina Kościelnicka	2020-07-06	2	-13/+8
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*	synth_gowin: ABC9 support	Dan Ravensloft	2020-07-05	1	-1/+5
\| \| \| \| \|	This adds ABC9 support for synth_gowin; drastically improving synthesis quality.
*	Add opt_lut_ins pass. (#1673)	Marcelina Kościelnicka	2020-02-03	1	-4/+4
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*	Call equiv_opt with -multiclock and -assert	Eddie Hung	2019-12-31	1	-1/+1
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*	Rename memory tests to lutram, add more xilinx tests	Eddie Hung	2019-12-12	1	-3/+3
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*	update test	Pepijn de Vos	2019-12-03	1	-2/+3
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*	Use -match-init to not synth contradicting init values	Pepijn de Vos	2019-12-03	1	-10/+12
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*	attempt to fix formatting	Pepijn de Vos	2019-11-25	1	-138/+138
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*	gowin: add and test dff init values	Pepijn de Vos	2019-11-25	2	-0/+296
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*	gowin: Remove show command from tests.	Marcin Kościelnicki	2019-11-22	1	-1/+0
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*	fix fsm test with proper clock enable polarity	Pepijn de Vos	2019-11-11	1	-0/+11
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*	fix wide luts	Pepijn de Vos	2019-11-06	1	-7/+10
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*	don't cound exact luts in big muxes; futile and fragile	Pepijn de Vos	2019-10-30	1	-3/+0
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*	add tristate buffer and test	Pepijn de Vos	2019-10-28	1	-0/+13
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*	do not use wide luts in testcase	Pepijn de Vos	2019-10-28	1	-3/+3
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*	ALU sim tweaks	Pepijn de Vos	2019-10-24	1	-2/+2
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*	Add some tests	Pepijn de Vos	2019-10-21	10	-0/+224
	Copied from Efinix. * fsm is broken * latch and tribuf are not implemented yet * memory maps to dram