| Commit message (Expand) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | Merge pull request #1574 from YosysHQ/eddie/xilinx_lutram | Eddie Hung | 2019-12-16 | 2 | -21/+42 |
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| | * | Rename memory tests to lutram, add more xilinx tests | Eddie Hung | 2019-12-12 | 2 | -21/+42 |
| * | | Merge blockram tests | Eddie Hung | 2019-12-16 | 1 | -0/+0 |
| * | | Fixing compiler warning/issues. Moving test script to the correct place | Diego H | 2019-12-16 | 1 | -47/+0 |
| * | | Removing fixed attribute value to !ramstyle rules | Diego H | 2019-12-15 | 1 | -3238/+0 |
| * | | Merging attribute rules into a single match block; Adding tests | Diego H | 2019-12-15 | 3 | -0/+3373 |
| * | | Renaming BRAM memory tests for the sake of uniformity | Diego H | 2019-12-13 | 1 | -0/+0 |
| * | | Updating RAMB36E1 thresholds. Adding test for both RAMB18E1/RAMB36E1 | Diego H | 2019-12-12 | 1 | -0/+45 |
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| * | fixed error | Miodrag Milanovic | 2019-10-18 | 1 | -1/+1 |
| * | Unify verilog style | Miodrag Milanovic | 2019-10-18 | 11 | -191/+157 |
| * | Common memory test now shared | Miodrag Milanovic | 2019-10-18 | 1 | -0/+21 |
| * | Share common tests | Miodrag Milanovic | 2019-10-18 | 11 | -0/+289 |
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index : iCE40/yosys | |
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