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author | Miodrag Milanovic <mmicko@gmail.com> | 2019-10-18 12:33:35 +0200 |
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committer | Miodrag Milanovic <mmicko@gmail.com> | 2019-10-18 12:33:35 +0200 |
commit | 12383f37b2e1d72784e01db0431efc8882f25430 (patch) | |
tree | 5bd01531406aedd9ee9f1ceaaab18374a8235ec2 /tests/arch/common | |
parent | 477702b8c91bb7780ac80b25c8ad659cd40b445d (diff) | |
download | yosys-12383f37b2e1d72784e01db0431efc8882f25430.tar.gz yosys-12383f37b2e1d72784e01db0431efc8882f25430.tar.bz2 yosys-12383f37b2e1d72784e01db0431efc8882f25430.zip |
Common memory test now shared
Diffstat (limited to 'tests/arch/common')
-rw-r--r-- | tests/arch/common/memory.v | 21 |
1 files changed, 21 insertions, 0 deletions
diff --git a/tests/arch/common/memory.v b/tests/arch/common/memory.v new file mode 100644 index 000000000..cb7753f7b --- /dev/null +++ b/tests/arch/common/memory.v @@ -0,0 +1,21 @@ +module top +( + input [7:0] data_a, + input [6:1] addr_a, + input we_a, clk, + output reg [7:0] q_a +); + // Declare the RAM variable + reg [7:0] ram[63:0]; + + // Port A + always @ (posedge clk) + begin + if (we_a) + begin + ram[addr_a] <= data_a; + q_a <= data_a; + end + q_a <= ram[addr_a]; + end +endmodule |