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* Merge remote-tracking branch 'origin/master' into xaigEddie Hung2019-06-1212-406/+624
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| * ice40/cells_sim.v: Add support for RGB_DRV/LED_DRV_CUR for u4kSimon Schubert2019-06-101-0/+24
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| * Merge pull request #1073 from whitequark/ecp5-diamond-iobDavid Shah2019-06-061-0/+15
| |\ | | | | | | ECP5: implement most Diamond I/O buffer primitives
| | * ECP5: implement all Diamond I/O buffer primitives.whitequark2019-06-061-0/+15
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| * | Remove extra newlineEddie Hung2019-06-031-1/+0
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| * | Execute techmap and arith_map simultaneouslyEddie Hung2019-06-031-6/+6
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| * | Add "min bits" and "min wports" to xilinx dram rulesEddie Hung2019-05-231-0/+4
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| * | Add "wreduce -keepdc", fixes #1016Clifford Wolf2019-05-201-2/+4
| | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * | ice40/cells_sim.v: Add support for TRIM input to SB_HFOSCSylvain Munaut2019-05-131-0/+11
| |/ | | | | | | Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
| * Add "stat -tech xilinx"Clifford Wolf2019-05-111-1/+1
| | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * Fix formatting for synth_intel.ccBen Widawsky2019-05-091-222/+211
| | | | | | | | | | | | This is realized through the recently added .clang-format file. Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
| * Add "synth_xilinx -arch"Clifford Wolf2019-05-071-1/+13
| | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * Merge remote-tracking branch 'origin/master' into clifford/specifyEddie Hung2019-05-036-178/+124
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| | * Rename cells_map.v to prevent clash with ff_map.vEddie Hung2019-05-031-6/+8
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| | * Merge pull request #969 from YosysHQ/clifford/pmgenstuffClifford Wolf2019-05-032-0/+4
| | |\ | | | | | | | | Improve pmgen, Add "peepopt" pass with shift-mul pattern
| | | * Run "peepopt" in generic "synth" pass and "synth_ice40"Clifford Wolf2019-04-302-0/+4
| | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| | * | Back to passing all xc7srl tests!Eddie Hung2019-05-011-5/+4
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| | * | Merge remote-tracking branch 'origin/master' into eddie/synth_xilinx_fineEddie Hung2019-05-013-170/+104
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| | | * \ Merge pull request #966 from YosysHQ/clifford/fix956Clifford Wolf2019-04-301-1/+1
| | | |\ \ | | | | | | | | | | | | Drive dangling wires with init attr with their init value
| | | | * | Add handling of init attributes in "opt_expr -undriven"Clifford Wolf2019-04-301-1/+1
| | | | |/ | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| | | * | Refactor synth_xilinx to auto-generate docEddie Hung2019-04-261-153/+95
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| | | * | Cleanup ice40Eddie Hung2019-04-261-4/+6
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| | * | WIPEddie Hung2019-04-281-36/+22
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| | * | Move neg-pol to pos-pol mapping from ff_map to cells_map.vEddie Hung2019-04-282-9/+12
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| | * | Revert synth_xilinx 'fine' label more to how it used to be...Eddie Hung2019-04-261-21/+40
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| | * | Where did this check come from!?!Eddie Hung2019-04-261-1/+0
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| * | Improve $specrule interfaceClifford Wolf2019-04-231-2/+2
| | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * | Improve $specrule interfaceClifford Wolf2019-04-231-3/+4
| | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * | Add $specrule cells for $setup/$hold/$skew specify rulesClifford Wolf2019-04-231-0/+28
| | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * | Rename T_{RISE,FALL}_AVG to T_{RISE,FALL}_TYP to better match verilog std ↵Clifford Wolf2019-04-231-70/+70
| | | | | | | | | | | | | | | | | | nomenclature Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * | Add $specify2 and $specify3 cells to simlibClifford Wolf2019-04-231-0/+147
| |/ | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | Use nonblockingEddie Hung2019-04-231-1/+1
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* | Merge remote-tracking branch 'origin/master' into xaigEddie Hung2019-04-226-36/+222
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| * Update help messageEddie Hung2019-04-221-1/+1
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| * Move 'shregmap -tech xilinx' into map_cellsEddie Hung2019-04-221-17/+20
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| * Merge remote-tracking branch 'origin/master' into xc7srlEddie Hung2019-04-2212-21/+480
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| * | Tidy up, fix for -nosrlEddie Hung2019-04-212-12/+16
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| * | Merge branch 'map_cells_before_map_luts' into xc7srlEddie Hung2019-04-211-2/+2
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| * | | Add commentsEddie Hung2019-04-211-0/+7
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| * | | Use new pmux2shiftx from #944, remove my old attemptEddie Hung2019-04-211-3/+8
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| * | | Merge remote-tracking branch 'origin' into xc7srlEddie Hung2019-04-204-44/+69
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| * | | | Call shregmap twice -- once for variable, another for fixedEddie Hung2019-04-052-8/+14
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| * | | | Move dffinit til after abcEddie Hung2019-04-053-2/+2
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| * | | | Merge branch 'eddie/fix_retime' into xc7srlEddie Hung2019-04-054-11/+12
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| * | | | | techmap inside map_cells stageEddie Hung2019-04-052-2/+1
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| * | | | | Merge branch 'map_cells_before_map_luts' into xc7srlEddie Hung2019-04-041-0/+1
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| * | | | | | Use soft-logic, not LUT3 instantiationEddie Hung2019-04-041-4/+2
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| * | | | | | Merge branch 'map_cells_before_map_luts' into xc7srlEddie Hung2019-04-041-12/+12
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| * | | | | | | Cleanup commentsEddie Hung2019-04-041-5/+4
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| * | | | | | | t:$dff* -> t:$dff t:$dffeEddie Hung2019-04-041-2/+2
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