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| author | Eddie Hung <eddieh@ece.ubc.ca> | 2019-04-04 07:54:42 -0700 |
|---|---|---|
| committer | Eddie Hung <eddieh@ece.ubc.ca> | 2019-04-04 07:54:42 -0700 |
| commit | 572603409c3f5524f8d4d9e43a168bcfccd94465 (patch) | |
| tree | 042e21e109701a41623170c04ee3c1467a681fc9 /techlibs | |
| parent | 77755b5a662a11a3dcc18c070e6ea859104fc872 (diff) | |
| parent | d9cb787391143a1749954f9e442fd37a13668b08 (diff) | |
| download | yosys-572603409c3f5524f8d4d9e43a168bcfccd94465.tar.gz yosys-572603409c3f5524f8d4d9e43a168bcfccd94465.tar.bz2 yosys-572603409c3f5524f8d4d9e43a168bcfccd94465.zip | |
Merge branch 'map_cells_before_map_luts' into xc7srl
Diffstat (limited to 'techlibs')
| -rw-r--r-- | techlibs/xilinx/synth_xilinx.cc | 24 |
1 files changed, 12 insertions, 12 deletions
diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc index 5a3725e7d..6423e6a3f 100644 --- a/techlibs/xilinx/synth_xilinx.cc +++ b/techlibs/xilinx/synth_xilinx.cc @@ -118,17 +118,17 @@ struct SynthXilinxPass : public Pass log(" techmap -map +/techmap.v -map +/xilinx/arith_map.v -map +/xilinx/ff_map.v\n"); log(" opt -fast\n"); log("\n"); - log(" map_luts:\n"); - log(" abc -luts 2:2,3,6:5,10,20 [-dff] (without '-vpr' only!)\n"); - log(" abc -lut 5 [-dff] (with '-vpr' only!)\n"); - log(" clean\n"); - log("\n"); log(" map_cells:\n"); log(" techmap -map +/xilinx/cells_map.v\n"); log(" dffinit -ff FDRE Q INIT -ff FDCE Q INIT -ff FDPE Q INIT -ff FDSE Q INIT \\\n"); log(" -ff FDRE_1 Q INIT -ff FDCE_1 Q INIT -ff FDPE_1 Q INIT -ff FDSE_1 Q INIT\n"); log(" clean\n"); log("\n"); + log(" map_luts:\n"); + log(" abc -luts 2:2,3,6:5,10,20 [-dff] (without '-vpr' only!)\n"); + log(" abc -lut 5 [-dff] (with '-vpr' only!)\n"); + log(" clean\n"); + log("\n"); log(" check:\n"); log(" hierarchy -check\n"); log(" stat\n"); @@ -280,13 +280,6 @@ struct SynthXilinxPass : public Pass Pass::call(design, "opt -fast"); } - if (check_label(active, run_from, run_to, "map_luts")) - { - Pass::call(design, "abc -luts 2:2,3,6:5,10,20" + string(retime ? " -dff" : "")); - Pass::call(design, "clean"); - Pass::call(design, "techmap -map +/xilinx/lut_map.v"); - } - if (check_label(active, run_from, run_to, "map_cells")) { Pass::call(design, "techmap -map +/xilinx/cells_map.v"); @@ -295,6 +288,13 @@ struct SynthXilinxPass : public Pass Pass::call(design, "clean"); } + if (check_label(active, run_from, run_to, "map_luts")) + { + Pass::call(design, "abc -luts 2:2,3,6:5,10,20" + string(retime ? " -dff" : "")); + Pass::call(design, "clean"); + Pass::call(design, "techmap -map +/xilinx/lut_map.v"); + } + if (check_label(active, run_from, run_to, "check")) { Pass::call(design, "hierarchy -check"); |