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* Add -nocarry option to synth_xilinxEddie Hung2019-04-241-5/+14
* TweakEddie Hung2019-04-221-1/+1
* Fix for A_WIDTH == 2 but B_WIDTH==3Eddie Hung2019-04-221-1/+1
* Trim A_WIDTH by Y_WIDTH-1Eddie Hung2019-04-221-1/+1
* Add commentEddie Hung2019-04-221-0/+3
* Fix for mux_case_* mappingsEddie Hung2019-04-221-17/+9
* Fix for non-pow2 width muxesEddie Hung2019-04-221-9/+18
* Add synth_xilinx -nomux optionEddie Hung2019-04-222-4/+18
* Cleanup, call pmux2shiftx even without -nosrlEddie Hung2019-04-226-45/+30
* Merge branch 'xaig' into xc7muxEddie Hung2019-04-2211-38/+446
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| * Merge remote-tracking branch 'origin/master' into xaigEddie Hung2019-04-2212-29/+488
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| * | Convert to use #945Eddie Hung2019-04-212-9/+3
| * | Merge remote-tracking branch 'origin/master' into xaigEddie Hung2019-04-202-10/+12
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| * | | ABC_FLOPS -> ABC_MODEL -- only whitebox if ABC_MODEL setEddie Hung2019-04-192-4/+7
| * | | Make SB_DFF whiteboxEddie Hung2019-04-193-3/+3
| * | | Fix SB_DFF comb modelEddie Hung2019-04-182-3/+3
| * | | Missing close bracketEddie Hung2019-04-181-1/+1
| * | | Annotate SB_DFF* with abc_flop and abc_box_idEddie Hung2019-04-181-22/+49
| * | | Add SB_DFF* to boxesEddie Hung2019-04-183-6/+306
| * | | Use new -wb flag for ABC flowEddie Hung2019-04-183-19/+5
| * | | Also update Makefile.incEddie Hung2019-04-181-7/+6
| * | | Make SB_LUT4 a blackboxEddie Hung2019-04-183-3/+3
| * | | Fix renameEddie Hung2019-04-181-0/+0
| * | | Rename to abc_*.{box,lut}Eddie Hung2019-04-186-0/+0
| * | | Update Makefile.inc tooEddie Hung2019-04-171-4/+6
| * | | Reduce to three devices: hx, lp, uEddie Hung2019-04-177-4/+23
| * | | Add up5k timingsEddie Hung2019-04-172-0/+19
| * | | Fix grammarEddie Hung2019-04-171-2/+2
| * | | Update error messageEddie Hung2019-04-171-1/+1
| * | | Add "-device" argument to synth_ice40Eddie Hung2019-04-174-7/+20
| * | | Missing abc_flop_q attribute on SPRAMEddie Hung2019-04-171-1/+1
| * | | Map to SB_LUT4 from fastest input firstEddie Hung2019-04-171-7/+11
| * | | Mark seq output ports with "abc_flop_q" attrEddie Hung2019-04-171-24/+24
| * | | Also update Makefile.incEddie Hung2019-04-171-3/+3
| * | | synth_ice40 to use renamed filesEddie Hung2019-04-171-2/+2
| * | | Rename to abc.*Eddie Hung2019-04-173-0/+0
| * | | Revert "Try using an ICE40_CARRY_LUT primitive to avoid ABC issues"Eddie Hung2019-04-177-102/+35
| * | | Try using an ICE40_CARRY_LUT primitive to avoid ABC issuesEddie Hung2019-04-177-35/+102
| * | | Fix spacingEddie Hung2019-04-171-5/+5
| * | | Add SB_LUT4 to box libraryEddie Hung2019-04-163-0/+16
| * | | Add ice40 box filesEddie Hung2019-04-166-1/+27
* | | | Merge remote-tracking branch 'origin/xc7srl' into xc7muxEddie Hung2019-04-2217-52/+694
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| * | | | Update help messageEddie Hung2019-04-221-1/+1
| * | | | Move 'shregmap -tech xilinx' into map_cellsEddie Hung2019-04-221-17/+20
| * | | | Merge remote-tracking branch 'origin/master' into xc7srlEddie Hung2019-04-2212-21/+480
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| | * | | Merge pull request #941 from Wren6991/sim_lib_io_clkeClifford Wolf2019-04-221-10/+19
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| | | * | | ice40 cells_sim.v: SB_IO: update clock enable behaviour based on hardware exp...Luke Wren2019-04-211-10/+19
| | * | | | Merge branch 'master' of https://github.com/dh73/yosys_gowin into dh73-masterClifford Wolf2019-04-2210-10/+458
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| | | * | | | GoWin enablement: DRAM, initial BRAM, DRAM init, DRAM sim and synth_gowin flowDiego2019-04-1210-11/+459
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| | * | | | Re-added clean after techmap in synth_xilinxClifford Wolf2019-04-221-0/+2